blob: 004070956cca6862da7115aaf955174ae67f152a [file] [log] [blame]
Ralf Baechlec78cbf42005-09-30 13:59:37 +01001/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18/*
19 * Simulator Platform-specific hooks for SMP operation
20 */
21#include <linux/config.h>
22#include <linux/kernel.h>
23#include <linux/sched.h>
24#include <linux/cpumask.h>
25#include <linux/interrupt.h>
26#include <asm/atomic.h>
27#include <asm/cpu.h>
28#include <asm/processor.h>
29#include <asm/system.h>
30#include <asm/hardirq.h>
31#include <asm/mmu_context.h>
32#include <asm/smp.h>
33#ifdef CONFIG_MIPS_MT_SMTC
34#include <asm/smtc_ipi.h>
35#endif /* CONFIG_MIPS_MT_SMTC */
36
37/* VPE/SMP Prototype implements platform interfaces directly */
38#if !defined(CONFIG_MIPS_MT_SMP)
39
40/*
41 * Cause the specified action to be performed on a targeted "CPU"
42 */
43
44void core_send_ipi(int cpu, unsigned int action)
45{
46#ifdef CONFIG_MIPS_MT_SMTC
Ralf Baechlec78cbf42005-09-30 13:59:37 +010047 smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
48#endif /* CONFIG_MIPS_MT_SMTC */
49/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
50
51}
52
53/*
Ralf Baechlec78cbf42005-09-30 13:59:37 +010054 * Platform "CPU" startup hook
55 */
56
57void prom_boot_secondary(int cpu, struct task_struct *idle)
58{
59#ifdef CONFIG_MIPS_MT_SMTC
Ralf Baechlec78cbf42005-09-30 13:59:37 +010060 smtc_boot_secondary(cpu, idle);
61#endif /* CONFIG_MIPS_MT_SMTC */
62}
63
64/*
65 * Post-config but pre-boot cleanup entry point
66 */
67
68void prom_init_secondary(void)
69{
70#ifdef CONFIG_MIPS_MT_SMTC
71 void smtc_init_secondary(void);
72
73 smtc_init_secondary();
74#endif /* CONFIG_MIPS_MT_SMTC */
75}
76
77/*
78 * Platform SMP pre-initialization
79 */
80
81void prom_prepare_cpus(unsigned int max_cpus)
82{
83#ifdef CONFIG_MIPS_MT_SMTC
Ralf Baechlec78cbf42005-09-30 13:59:37 +010084 /*
Ralf Baechlea3dddd52006-03-11 08:18:41 +000085 * As noted above, we can assume a single CPU for now
Ralf Baechlec78cbf42005-09-30 13:59:37 +010086 * but it may be multithreaded.
87 */
88
89 if (read_c0_config3() & (1<<2)) {
90 mipsmt_prepare_cpus(max_cpus);
91 }
92#endif /* CONFIG_MIPS_MT_SMTC */
93}
94
95/*
96 * SMP initialization finalization entry point
97 */
98
99void prom_smp_finish(void)
100{
101#ifdef CONFIG_MIPS_MT_SMTC
Ralf Baechlec78cbf42005-09-30 13:59:37 +0100102 smtc_smp_finish();
103#endif /* CONFIG_MIPS_MT_SMTC */
104}
105
106/*
107 * Hook for after all CPUs are online
108 */
109
110void prom_cpus_done(void)
111{
112#ifdef CONFIG_MIPS_MT_SMTC
113
114#endif /* CONFIG_MIPS_MT_SMTC */
115}
116#endif /* CONFIG_MIPS32R2_MT_SMP */