Oscar Mateo | b20385f | 2014-07-24 17:04:10 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Ben Widawsky <ben@bwidawsk.net> |
| 25 | * Michel Thierry <michel.thierry@intel.com> |
| 26 | * Thomas Daniel <thomas.daniel@intel.com> |
| 27 | * Oscar Mateo <oscar.mateo@intel.com> |
| 28 | * |
| 29 | */ |
| 30 | |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 31 | /** |
| 32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists |
| 33 | * |
| 34 | * Motivation: |
Oscar Mateo | b20385f | 2014-07-24 17:04:10 +0100 | [diff] [blame] | 35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
| 36 | * These expanded contexts enable a number of new abilities, especially |
| 37 | * "Execlists" (also implemented in this file). |
| 38 | * |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 39 | * One of the main differences with the legacy HW contexts is that logical |
| 40 | * ring contexts incorporate many more things to the context's state, like |
| 41 | * PDPs or ringbuffer control registers: |
| 42 | * |
| 43 | * The reason why PDPs are included in the context is straightforward: as |
| 44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs |
| 45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, |
| 46 | * instead, the GPU will do it for you on the context switch. |
| 47 | * |
| 48 | * But, what about the ringbuffer control registers (head, tail, etc..)? |
| 49 | * shouldn't we just need a set of those per engine command streamer? This is |
| 50 | * where the name "Logical Rings" starts to make sense: by virtualizing the |
| 51 | * rings, the engine cs shifts to a new "ring buffer" with every context |
| 52 | * switch. When you want to submit a workload to the GPU you: A) choose your |
| 53 | * context, B) find its appropriate virtualized ring, C) write commands to it |
| 54 | * and then, finally, D) tell the GPU to switch to that context. |
| 55 | * |
| 56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch |
| 57 | * to a contexts is via a context execution list, ergo "Execlists". |
| 58 | * |
| 59 | * LRC implementation: |
| 60 | * Regarding the creation of contexts, we have: |
| 61 | * |
| 62 | * - One global default context. |
| 63 | * - One local default context for each opened fd. |
| 64 | * - One local extra context for each context create ioctl call. |
| 65 | * |
| 66 | * Now that ringbuffers belong per-context (and not per-engine, like before) |
| 67 | * and that contexts are uniquely tied to a given engine (and not reusable, |
| 68 | * like before) we need: |
| 69 | * |
| 70 | * - One ringbuffer per-engine inside each context. |
| 71 | * - One backing object per-engine inside each context. |
| 72 | * |
| 73 | * The global default context starts its life with these new objects fully |
| 74 | * allocated and populated. The local default context for each opened fd is |
| 75 | * more complex, because we don't know at creation time which engine is going |
| 76 | * to use them. To handle this, we have implemented a deferred creation of LR |
| 77 | * contexts: |
| 78 | * |
| 79 | * The local context starts its life as a hollow or blank holder, that only |
| 80 | * gets populated for a given engine once we receive an execbuffer. If later |
| 81 | * on we receive another execbuffer ioctl for the same context but a different |
| 82 | * engine, we allocate/populate a new ringbuffer and context backing object and |
| 83 | * so on. |
| 84 | * |
| 85 | * Finally, regarding local contexts created using the ioctl call: as they are |
| 86 | * only allowed with the render ring, we can allocate & populate them right |
| 87 | * away (no need to defer anything, at least for now). |
| 88 | * |
| 89 | * Execlists implementation: |
Oscar Mateo | b20385f | 2014-07-24 17:04:10 +0100 | [diff] [blame] | 90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
| 91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 92 | * This method works as follows: |
| 93 | * |
| 94 | * When a request is committed, its commands (the BB start and any leading or |
| 95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer |
| 96 | * for the appropriate context. The tail pointer in the hardware context is not |
| 97 | * updated at this time, but instead, kept by the driver in the ringbuffer |
| 98 | * structure. A structure representing this request is added to a request queue |
| 99 | * for the appropriate engine: this structure contains a copy of the context's |
| 100 | * tail after the request was written to the ring buffer and a pointer to the |
| 101 | * context itself. |
| 102 | * |
| 103 | * If the engine's request queue was empty before the request was added, the |
| 104 | * queue is processed immediately. Otherwise the queue will be processed during |
| 105 | * a context switch interrupt. In any case, elements on the queue will get sent |
| 106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a |
| 107 | * globally unique 20-bits submission ID. |
| 108 | * |
| 109 | * When execution of a request completes, the GPU updates the context status |
| 110 | * buffer with a context complete event and generates a context switch interrupt. |
| 111 | * During the interrupt handling, the driver examines the events in the buffer: |
| 112 | * for each context complete event, if the announced ID matches that on the head |
| 113 | * of the request queue, then that request is retired and removed from the queue. |
| 114 | * |
| 115 | * After processing, if any requests were retired and the queue is not empty |
| 116 | * then a new execution list can be submitted. The two requests at the front of |
| 117 | * the queue are next to be submitted but since a context may not occur twice in |
| 118 | * an execution list, if subsequent requests have the same ID as the first then |
| 119 | * the two requests must be combined. This is done simply by discarding requests |
| 120 | * at the head of the queue until either only one requests is left (in which case |
| 121 | * we use a NULL second context) or the first two requests have unique IDs. |
| 122 | * |
| 123 | * By always executing the first two requests in the queue the driver ensures |
| 124 | * that the GPU is kept as busy as possible. In the case where a single context |
| 125 | * completes but a second context is still executing, the request for this second |
| 126 | * context will be at the head of the queue when we remove the first one. This |
| 127 | * request will then be resubmitted along with a new request for a different context, |
| 128 | * which will cause the hardware to continue executing the second request and queue |
| 129 | * the new request (the GPU detects the condition of a context getting preempted |
| 130 | * with the same context and optimizes the context switch flow by not doing |
| 131 | * preemption, but just sampling the new tail pointer). |
| 132 | * |
Oscar Mateo | b20385f | 2014-07-24 17:04:10 +0100 | [diff] [blame] | 133 | */ |
| 134 | |
| 135 | #include <drm/drmP.h> |
| 136 | #include <drm/i915_drm.h> |
| 137 | #include "i915_drv.h" |
Oscar Mateo | 127f100 | 2014-07-24 17:04:11 +0100 | [diff] [blame] | 138 | |
Michael H. Nguyen | 468c681 | 2014-11-13 17:51:49 +0000 | [diff] [blame] | 139 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 140 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
| 141 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) |
| 142 | |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 143 | #define RING_EXECLIST_QFULL (1 << 0x2) |
| 144 | #define RING_EXECLIST1_VALID (1 << 0x3) |
| 145 | #define RING_EXECLIST0_VALID (1 << 0x4) |
| 146 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) |
| 147 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) |
| 148 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) |
| 149 | |
| 150 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) |
| 151 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) |
| 152 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) |
| 153 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) |
| 154 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) |
| 155 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 156 | |
| 157 | #define CTX_LRI_HEADER_0 0x01 |
| 158 | #define CTX_CONTEXT_CONTROL 0x02 |
| 159 | #define CTX_RING_HEAD 0x04 |
| 160 | #define CTX_RING_TAIL 0x06 |
| 161 | #define CTX_RING_BUFFER_START 0x08 |
| 162 | #define CTX_RING_BUFFER_CONTROL 0x0a |
| 163 | #define CTX_BB_HEAD_U 0x0c |
| 164 | #define CTX_BB_HEAD_L 0x0e |
| 165 | #define CTX_BB_STATE 0x10 |
| 166 | #define CTX_SECOND_BB_HEAD_U 0x12 |
| 167 | #define CTX_SECOND_BB_HEAD_L 0x14 |
| 168 | #define CTX_SECOND_BB_STATE 0x16 |
| 169 | #define CTX_BB_PER_CTX_PTR 0x18 |
| 170 | #define CTX_RCS_INDIRECT_CTX 0x1a |
| 171 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c |
| 172 | #define CTX_LRI_HEADER_1 0x21 |
| 173 | #define CTX_CTX_TIMESTAMP 0x22 |
| 174 | #define CTX_PDP3_UDW 0x24 |
| 175 | #define CTX_PDP3_LDW 0x26 |
| 176 | #define CTX_PDP2_UDW 0x28 |
| 177 | #define CTX_PDP2_LDW 0x2a |
| 178 | #define CTX_PDP1_UDW 0x2c |
| 179 | #define CTX_PDP1_LDW 0x2e |
| 180 | #define CTX_PDP0_UDW 0x30 |
| 181 | #define CTX_PDP0_LDW 0x32 |
| 182 | #define CTX_LRI_HEADER_2 0x41 |
| 183 | #define CTX_R_PWR_CLK_STATE 0x42 |
| 184 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 |
| 185 | |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 186 | #define GEN8_CTX_VALID (1<<0) |
| 187 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) |
| 188 | #define GEN8_CTX_FORCE_RESTORE (1<<2) |
| 189 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) |
| 190 | #define GEN8_CTX_PRIVILEGE (1<<8) |
| 191 | enum { |
| 192 | ADVANCED_CONTEXT = 0, |
| 193 | LEGACY_CONTEXT, |
| 194 | ADVANCED_AD_CONTEXT, |
| 195 | LEGACY_64B_CONTEXT |
| 196 | }; |
| 197 | #define GEN8_CTX_MODE_SHIFT 3 |
| 198 | enum { |
| 199 | FAULT_AND_HANG = 0, |
| 200 | FAULT_AND_HALT, /* Debug only */ |
| 201 | FAULT_AND_STREAM, |
| 202 | FAULT_AND_CONTINUE /* Unsupported */ |
| 203 | }; |
| 204 | #define GEN8_CTX_ID_SHIFT 32 |
| 205 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 206 | static int intel_lr_context_pin(struct intel_engine_cs *ring, |
| 207 | struct intel_context *ctx); |
| 208 | |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 209 | /** |
| 210 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists |
| 211 | * @dev: DRM device. |
| 212 | * @enable_execlists: value of i915.enable_execlists module parameter. |
| 213 | * |
| 214 | * Only certain platforms support Execlists (the prerequisites being |
| 215 | * support for Logical Ring Contexts and Aliasing PPGTT or better), |
| 216 | * and only when enabled via module parameter. |
| 217 | * |
| 218 | * Return: 1 if Execlists is supported and has to be enabled. |
| 219 | */ |
Oscar Mateo | 127f100 | 2014-07-24 17:04:11 +0100 | [diff] [blame] | 220 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
| 221 | { |
Daniel Vetter | bd84b1e | 2014-08-11 15:57:57 +0200 | [diff] [blame] | 222 | WARN_ON(i915.enable_ppgtt == -1); |
| 223 | |
Damien Lespiau | 70ee45e | 2014-11-14 15:05:59 +0000 | [diff] [blame] | 224 | if (INTEL_INFO(dev)->gen >= 9) |
| 225 | return 1; |
| 226 | |
Oscar Mateo | 127f100 | 2014-07-24 17:04:11 +0100 | [diff] [blame] | 227 | if (enable_execlists == 0) |
| 228 | return 0; |
| 229 | |
Oscar Mateo | 14bf993 | 2014-07-24 17:04:34 +0100 | [diff] [blame] | 230 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
| 231 | i915.use_mmio_flip >= 0) |
Oscar Mateo | 127f100 | 2014-07-24 17:04:11 +0100 | [diff] [blame] | 232 | return 1; |
| 233 | |
| 234 | return 0; |
| 235 | } |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 236 | |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 237 | /** |
| 238 | * intel_execlists_ctx_id() - get the Execlists Context ID |
| 239 | * @ctx_obj: Logical Ring Context backing object. |
| 240 | * |
| 241 | * Do not confuse with ctx->id! Unfortunately we have a name overload |
| 242 | * here: the old context ID we pass to userspace as a handler so that |
| 243 | * they can refer to a context, and the new context ID we pass to the |
| 244 | * ELSP so that the GPU can inform us of the context status via |
| 245 | * interrupts. |
| 246 | * |
| 247 | * Return: 20-bits globally unique context ID. |
| 248 | */ |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 249 | u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) |
| 250 | { |
| 251 | u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); |
| 252 | |
| 253 | /* LRCA is required to be 4K aligned so the more significant 20 bits |
| 254 | * are globally unique */ |
| 255 | return lrca >> 12; |
| 256 | } |
| 257 | |
| 258 | static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj) |
| 259 | { |
| 260 | uint64_t desc; |
| 261 | uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 262 | |
| 263 | WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 264 | |
| 265 | desc = GEN8_CTX_VALID; |
| 266 | desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; |
| 267 | desc |= GEN8_CTX_L3LLC_COHERENT; |
| 268 | desc |= GEN8_CTX_PRIVILEGE; |
| 269 | desc |= lrca; |
| 270 | desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; |
| 271 | |
| 272 | /* TODO: WaDisableLiteRestore when we start using semaphore |
| 273 | * signalling between Command Streamers */ |
| 274 | /* desc |= GEN8_CTX_FORCE_RESTORE; */ |
| 275 | |
| 276 | return desc; |
| 277 | } |
| 278 | |
| 279 | static void execlists_elsp_write(struct intel_engine_cs *ring, |
| 280 | struct drm_i915_gem_object *ctx_obj0, |
| 281 | struct drm_i915_gem_object *ctx_obj1) |
| 282 | { |
Tvrtko Ursulin | 6e7cc47 | 2014-11-13 17:51:51 +0000 | [diff] [blame] | 283 | struct drm_device *dev = ring->dev; |
| 284 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 285 | uint64_t temp = 0; |
| 286 | uint32_t desc[4]; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 287 | unsigned long flags; |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 288 | |
| 289 | /* XXX: You must always write both descriptors in the order below. */ |
| 290 | if (ctx_obj1) |
| 291 | temp = execlists_ctx_descriptor(ctx_obj1); |
| 292 | else |
| 293 | temp = 0; |
| 294 | desc[1] = (u32)(temp >> 32); |
| 295 | desc[0] = (u32)temp; |
| 296 | |
| 297 | temp = execlists_ctx_descriptor(ctx_obj0); |
| 298 | desc[3] = (u32)(temp >> 32); |
| 299 | desc[2] = (u32)temp; |
| 300 | |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 301 | /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes |
| 302 | * are in progress. |
| 303 | * |
| 304 | * The other problem is that we can't just call gen6_gt_force_wake_get() |
| 305 | * because that function calls intel_runtime_pm_get(), which might sleep. |
| 306 | * Instead, we do the runtime_pm_get/put when creating/destroying requests. |
| 307 | */ |
| 308 | spin_lock_irqsave(&dev_priv->uncore.lock, flags); |
Tvrtko Ursulin | 6e7cc47 | 2014-11-13 17:51:51 +0000 | [diff] [blame] | 309 | if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) { |
Deepak S | a01b0e9 | 2014-09-09 19:14:16 +0530 | [diff] [blame] | 310 | if (dev_priv->uncore.fw_rendercount++ == 0) |
| 311 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
| 312 | FORCEWAKE_RENDER); |
| 313 | if (dev_priv->uncore.fw_mediacount++ == 0) |
| 314 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
| 315 | FORCEWAKE_MEDIA); |
Tvrtko Ursulin | 6e7cc47 | 2014-11-13 17:51:51 +0000 | [diff] [blame] | 316 | if (INTEL_INFO(dev)->gen >= 9) { |
| 317 | if (dev_priv->uncore.fw_blittercount++ == 0) |
| 318 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
| 319 | FORCEWAKE_BLITTER); |
| 320 | } |
Deepak S | a01b0e9 | 2014-09-09 19:14:16 +0530 | [diff] [blame] | 321 | } else { |
| 322 | if (dev_priv->uncore.forcewake_count++ == 0) |
| 323 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
| 324 | FORCEWAKE_ALL); |
| 325 | } |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 326 | spin_unlock_irqrestore(&dev_priv->uncore.lock, flags); |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 327 | |
| 328 | I915_WRITE(RING_ELSP(ring), desc[1]); |
| 329 | I915_WRITE(RING_ELSP(ring), desc[0]); |
| 330 | I915_WRITE(RING_ELSP(ring), desc[3]); |
| 331 | /* The context is automatically loaded after the following */ |
| 332 | I915_WRITE(RING_ELSP(ring), desc[2]); |
| 333 | |
| 334 | /* ELSP is a wo register, so use another nearby reg for posting instead */ |
| 335 | POSTING_READ(RING_EXECLIST_STATUS(ring)); |
| 336 | |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 337 | /* Release Force Wakeup (see the big comment above). */ |
| 338 | spin_lock_irqsave(&dev_priv->uncore.lock, flags); |
Tvrtko Ursulin | 6e7cc47 | 2014-11-13 17:51:51 +0000 | [diff] [blame] | 339 | if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) { |
Deepak S | a01b0e9 | 2014-09-09 19:14:16 +0530 | [diff] [blame] | 340 | if (--dev_priv->uncore.fw_rendercount == 0) |
| 341 | dev_priv->uncore.funcs.force_wake_put(dev_priv, |
| 342 | FORCEWAKE_RENDER); |
| 343 | if (--dev_priv->uncore.fw_mediacount == 0) |
| 344 | dev_priv->uncore.funcs.force_wake_put(dev_priv, |
| 345 | FORCEWAKE_MEDIA); |
Tvrtko Ursulin | 6e7cc47 | 2014-11-13 17:51:51 +0000 | [diff] [blame] | 346 | if (INTEL_INFO(dev)->gen >= 9) { |
| 347 | if (--dev_priv->uncore.fw_blittercount == 0) |
| 348 | dev_priv->uncore.funcs.force_wake_put(dev_priv, |
| 349 | FORCEWAKE_BLITTER); |
| 350 | } |
Deepak S | a01b0e9 | 2014-09-09 19:14:16 +0530 | [diff] [blame] | 351 | } else { |
| 352 | if (--dev_priv->uncore.forcewake_count == 0) |
| 353 | dev_priv->uncore.funcs.force_wake_put(dev_priv, |
| 354 | FORCEWAKE_ALL); |
| 355 | } |
| 356 | |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 357 | spin_unlock_irqrestore(&dev_priv->uncore.lock, flags); |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 358 | } |
| 359 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 360 | static int execlists_update_context(struct drm_i915_gem_object *ctx_obj, |
| 361 | struct drm_i915_gem_object *ring_obj, |
| 362 | u32 tail) |
Oscar Mateo | ae1250b | 2014-07-24 17:04:37 +0100 | [diff] [blame] | 363 | { |
| 364 | struct page *page; |
| 365 | uint32_t *reg_state; |
| 366 | |
| 367 | page = i915_gem_object_get_page(ctx_obj, 1); |
| 368 | reg_state = kmap_atomic(page); |
| 369 | |
| 370 | reg_state[CTX_RING_TAIL+1] = tail; |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 371 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); |
Oscar Mateo | ae1250b | 2014-07-24 17:04:37 +0100 | [diff] [blame] | 372 | |
| 373 | kunmap_atomic(reg_state); |
| 374 | |
| 375 | return 0; |
| 376 | } |
| 377 | |
Dave Gordon | cd0707c | 2014-10-30 15:41:56 +0000 | [diff] [blame] | 378 | static void execlists_submit_contexts(struct intel_engine_cs *ring, |
| 379 | struct intel_context *to0, u32 tail0, |
| 380 | struct intel_context *to1, u32 tail1) |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 381 | { |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 382 | struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state; |
| 383 | struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf; |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 384 | struct drm_i915_gem_object *ctx_obj1 = NULL; |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 385 | struct intel_ringbuffer *ringbuf1 = NULL; |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 386 | |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 387 | BUG_ON(!ctx_obj0); |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 388 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 389 | WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj)); |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 390 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 391 | execlists_update_context(ctx_obj0, ringbuf0->obj, tail0); |
Oscar Mateo | ae1250b | 2014-07-24 17:04:37 +0100 | [diff] [blame] | 392 | |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 393 | if (to1) { |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 394 | ringbuf1 = to1->engine[ring->id].ringbuf; |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 395 | ctx_obj1 = to1->engine[ring->id].state; |
| 396 | BUG_ON(!ctx_obj1); |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 397 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1)); |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 398 | WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj)); |
Oscar Mateo | ae1250b | 2014-07-24 17:04:37 +0100 | [diff] [blame] | 399 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 400 | execlists_update_context(ctx_obj1, ringbuf1->obj, tail1); |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 401 | } |
| 402 | |
| 403 | execlists_elsp_write(ring, ctx_obj0, ctx_obj1); |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 404 | } |
| 405 | |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 406 | static void execlists_context_unqueue(struct intel_engine_cs *ring) |
| 407 | { |
| 408 | struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL; |
| 409 | struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 410 | |
| 411 | assert_spin_locked(&ring->execlist_lock); |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 412 | |
| 413 | if (list_empty(&ring->execlist_queue)) |
| 414 | return; |
| 415 | |
| 416 | /* Try to read in pairs */ |
| 417 | list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, |
| 418 | execlist_link) { |
| 419 | if (!req0) { |
| 420 | req0 = cursor; |
| 421 | } else if (req0->ctx == cursor->ctx) { |
| 422 | /* Same ctx: ignore first request, as second request |
| 423 | * will update tail past first request's workload */ |
Oscar Mateo | e1fee72 | 2014-07-24 17:04:40 +0100 | [diff] [blame] | 424 | cursor->elsp_submitted = req0->elsp_submitted; |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 425 | list_del(&req0->execlist_link); |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 426 | list_add_tail(&req0->execlist_link, |
| 427 | &ring->execlist_retired_req_list); |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 428 | req0 = cursor; |
| 429 | } else { |
| 430 | req1 = cursor; |
| 431 | break; |
| 432 | } |
| 433 | } |
| 434 | |
Oscar Mateo | e1fee72 | 2014-07-24 17:04:40 +0100 | [diff] [blame] | 435 | WARN_ON(req1 && req1->elsp_submitted); |
| 436 | |
Dave Gordon | cd0707c | 2014-10-30 15:41:56 +0000 | [diff] [blame] | 437 | execlists_submit_contexts(ring, req0->ctx, req0->tail, |
| 438 | req1 ? req1->ctx : NULL, |
| 439 | req1 ? req1->tail : 0); |
Oscar Mateo | e1fee72 | 2014-07-24 17:04:40 +0100 | [diff] [blame] | 440 | |
| 441 | req0->elsp_submitted++; |
| 442 | if (req1) |
| 443 | req1->elsp_submitted++; |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 444 | } |
| 445 | |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 446 | static bool execlists_check_remove_request(struct intel_engine_cs *ring, |
| 447 | u32 request_id) |
| 448 | { |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 449 | struct intel_ctx_submit_request *head_req; |
| 450 | |
| 451 | assert_spin_locked(&ring->execlist_lock); |
| 452 | |
| 453 | head_req = list_first_entry_or_null(&ring->execlist_queue, |
| 454 | struct intel_ctx_submit_request, |
| 455 | execlist_link); |
| 456 | |
| 457 | if (head_req != NULL) { |
| 458 | struct drm_i915_gem_object *ctx_obj = |
| 459 | head_req->ctx->engine[ring->id].state; |
| 460 | if (intel_execlists_ctx_id(ctx_obj) == request_id) { |
Oscar Mateo | e1fee72 | 2014-07-24 17:04:40 +0100 | [diff] [blame] | 461 | WARN(head_req->elsp_submitted == 0, |
| 462 | "Never submitted head request\n"); |
| 463 | |
| 464 | if (--head_req->elsp_submitted <= 0) { |
| 465 | list_del(&head_req->execlist_link); |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 466 | list_add_tail(&head_req->execlist_link, |
| 467 | &ring->execlist_retired_req_list); |
Oscar Mateo | e1fee72 | 2014-07-24 17:04:40 +0100 | [diff] [blame] | 468 | return true; |
| 469 | } |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 470 | } |
| 471 | } |
| 472 | |
| 473 | return false; |
| 474 | } |
| 475 | |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 476 | /** |
Daniel Vetter | 3f7531c | 2014-12-10 17:41:43 +0100 | [diff] [blame^] | 477 | * intel_lrc_irq_handler() - handle Context Switch interrupts |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 478 | * @ring: Engine Command Streamer to handle. |
| 479 | * |
| 480 | * Check the unread Context Status Buffers and manage the submission of new |
| 481 | * contexts to the ELSP accordingly. |
| 482 | */ |
Daniel Vetter | 3f7531c | 2014-12-10 17:41:43 +0100 | [diff] [blame^] | 483 | void intel_lrc_irq_handler(struct intel_engine_cs *ring) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 484 | { |
| 485 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 486 | u32 status_pointer; |
| 487 | u8 read_pointer; |
| 488 | u8 write_pointer; |
| 489 | u32 status; |
| 490 | u32 status_id; |
| 491 | u32 submit_contexts = 0; |
| 492 | |
| 493 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); |
| 494 | |
| 495 | read_pointer = ring->next_context_status_buffer; |
| 496 | write_pointer = status_pointer & 0x07; |
| 497 | if (read_pointer > write_pointer) |
| 498 | write_pointer += 6; |
| 499 | |
| 500 | spin_lock(&ring->execlist_lock); |
| 501 | |
| 502 | while (read_pointer < write_pointer) { |
| 503 | read_pointer++; |
| 504 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + |
| 505 | (read_pointer % 6) * 8); |
| 506 | status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + |
| 507 | (read_pointer % 6) * 8 + 4); |
| 508 | |
Oscar Mateo | e1fee72 | 2014-07-24 17:04:40 +0100 | [diff] [blame] | 509 | if (status & GEN8_CTX_STATUS_PREEMPTED) { |
| 510 | if (status & GEN8_CTX_STATUS_LITE_RESTORE) { |
| 511 | if (execlists_check_remove_request(ring, status_id)) |
| 512 | WARN(1, "Lite Restored request removed from queue\n"); |
| 513 | } else |
| 514 | WARN(1, "Preemption without Lite Restore\n"); |
| 515 | } |
| 516 | |
| 517 | if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || |
| 518 | (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 519 | if (execlists_check_remove_request(ring, status_id)) |
| 520 | submit_contexts++; |
| 521 | } |
| 522 | } |
| 523 | |
| 524 | if (submit_contexts != 0) |
| 525 | execlists_context_unqueue(ring); |
| 526 | |
| 527 | spin_unlock(&ring->execlist_lock); |
| 528 | |
| 529 | WARN(submit_contexts > 2, "More than two context complete events?\n"); |
| 530 | ring->next_context_status_buffer = write_pointer % 6; |
| 531 | |
| 532 | I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), |
| 533 | ((u32)ring->next_context_status_buffer & 0x07) << 8); |
| 534 | } |
| 535 | |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 536 | static int execlists_context_queue(struct intel_engine_cs *ring, |
| 537 | struct intel_context *to, |
| 538 | u32 tail) |
| 539 | { |
Oscar Mateo | f1ad5a1 | 2014-07-24 17:04:41 +0100 | [diff] [blame] | 540 | struct intel_ctx_submit_request *req = NULL, *cursor; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 541 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 542 | unsigned long flags; |
Oscar Mateo | f1ad5a1 | 2014-07-24 17:04:41 +0100 | [diff] [blame] | 543 | int num_elements = 0; |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 544 | |
| 545 | req = kzalloc(sizeof(*req), GFP_KERNEL); |
| 546 | if (req == NULL) |
| 547 | return -ENOMEM; |
| 548 | req->ctx = to; |
| 549 | i915_gem_context_reference(req->ctx); |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 550 | |
| 551 | if (to != ring->default_context) |
| 552 | intel_lr_context_pin(ring, to); |
| 553 | |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 554 | req->ring = ring; |
| 555 | req->tail = tail; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 556 | |
| 557 | intel_runtime_pm_get(dev_priv); |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 558 | |
| 559 | spin_lock_irqsave(&ring->execlist_lock, flags); |
| 560 | |
Oscar Mateo | f1ad5a1 | 2014-07-24 17:04:41 +0100 | [diff] [blame] | 561 | list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) |
| 562 | if (++num_elements > 2) |
| 563 | break; |
| 564 | |
| 565 | if (num_elements > 2) { |
| 566 | struct intel_ctx_submit_request *tail_req; |
| 567 | |
| 568 | tail_req = list_last_entry(&ring->execlist_queue, |
| 569 | struct intel_ctx_submit_request, |
| 570 | execlist_link); |
| 571 | |
| 572 | if (to == tail_req->ctx) { |
| 573 | WARN(tail_req->elsp_submitted != 0, |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 574 | "More than 2 already-submitted reqs queued\n"); |
Oscar Mateo | f1ad5a1 | 2014-07-24 17:04:41 +0100 | [diff] [blame] | 575 | list_del(&tail_req->execlist_link); |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 576 | list_add_tail(&tail_req->execlist_link, |
| 577 | &ring->execlist_retired_req_list); |
Oscar Mateo | f1ad5a1 | 2014-07-24 17:04:41 +0100 | [diff] [blame] | 578 | } |
| 579 | } |
| 580 | |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 581 | list_add_tail(&req->execlist_link, &ring->execlist_queue); |
Oscar Mateo | f1ad5a1 | 2014-07-24 17:04:41 +0100 | [diff] [blame] | 582 | if (num_elements == 0) |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 583 | execlists_context_unqueue(ring); |
| 584 | |
| 585 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
| 586 | |
| 587 | return 0; |
| 588 | } |
| 589 | |
Oscar Mateo | ba8b7cc | 2014-07-24 17:04:33 +0100 | [diff] [blame] | 590 | static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf) |
| 591 | { |
| 592 | struct intel_engine_cs *ring = ringbuf->ring; |
| 593 | uint32_t flush_domains; |
| 594 | int ret; |
| 595 | |
| 596 | flush_domains = 0; |
| 597 | if (ring->gpu_caches_dirty) |
| 598 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 599 | |
| 600 | ret = ring->emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains); |
| 601 | if (ret) |
| 602 | return ret; |
| 603 | |
| 604 | ring->gpu_caches_dirty = false; |
| 605 | return 0; |
| 606 | } |
| 607 | |
| 608 | static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, |
| 609 | struct list_head *vmas) |
| 610 | { |
| 611 | struct intel_engine_cs *ring = ringbuf->ring; |
| 612 | struct i915_vma *vma; |
| 613 | uint32_t flush_domains = 0; |
| 614 | bool flush_chipset = false; |
| 615 | int ret; |
| 616 | |
| 617 | list_for_each_entry(vma, vmas, exec_list) { |
| 618 | struct drm_i915_gem_object *obj = vma->obj; |
| 619 | |
| 620 | ret = i915_gem_object_sync(obj, ring); |
| 621 | if (ret) |
| 622 | return ret; |
| 623 | |
| 624 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) |
| 625 | flush_chipset |= i915_gem_clflush_object(obj, false); |
| 626 | |
| 627 | flush_domains |= obj->base.write_domain; |
| 628 | } |
| 629 | |
| 630 | if (flush_domains & I915_GEM_DOMAIN_GTT) |
| 631 | wmb(); |
| 632 | |
| 633 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
| 634 | * any residual writes from the previous batch. |
| 635 | */ |
| 636 | return logical_ring_invalidate_all_caches(ringbuf); |
| 637 | } |
| 638 | |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 639 | /** |
| 640 | * execlists_submission() - submit a batchbuffer for execution, Execlists style |
| 641 | * @dev: DRM device. |
| 642 | * @file: DRM file. |
| 643 | * @ring: Engine Command Streamer to submit to. |
| 644 | * @ctx: Context to employ for this submission. |
| 645 | * @args: execbuffer call arguments. |
| 646 | * @vmas: list of vmas. |
| 647 | * @batch_obj: the batchbuffer to submit. |
| 648 | * @exec_start: batchbuffer start virtual address pointer. |
| 649 | * @flags: translated execbuffer call flags. |
| 650 | * |
| 651 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts |
| 652 | * away the submission details of the execbuffer ioctl call. |
| 653 | * |
| 654 | * Return: non-zero if the submission fails. |
| 655 | */ |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 656 | int intel_execlists_submission(struct drm_device *dev, struct drm_file *file, |
| 657 | struct intel_engine_cs *ring, |
| 658 | struct intel_context *ctx, |
| 659 | struct drm_i915_gem_execbuffer2 *args, |
| 660 | struct list_head *vmas, |
| 661 | struct drm_i915_gem_object *batch_obj, |
| 662 | u64 exec_start, u32 flags) |
| 663 | { |
Oscar Mateo | ba8b7cc | 2014-07-24 17:04:33 +0100 | [diff] [blame] | 664 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 665 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
| 666 | int instp_mode; |
| 667 | u32 instp_mask; |
| 668 | int ret; |
| 669 | |
| 670 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
| 671 | instp_mask = I915_EXEC_CONSTANTS_MASK; |
| 672 | switch (instp_mode) { |
| 673 | case I915_EXEC_CONSTANTS_REL_GENERAL: |
| 674 | case I915_EXEC_CONSTANTS_ABSOLUTE: |
| 675 | case I915_EXEC_CONSTANTS_REL_SURFACE: |
| 676 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { |
| 677 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); |
| 678 | return -EINVAL; |
| 679 | } |
| 680 | |
| 681 | if (instp_mode != dev_priv->relative_constants_mode) { |
| 682 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { |
| 683 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); |
| 684 | return -EINVAL; |
| 685 | } |
| 686 | |
| 687 | /* The HW changed the meaning on this bit on gen6 */ |
| 688 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; |
| 689 | } |
| 690 | break; |
| 691 | default: |
| 692 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); |
| 693 | return -EINVAL; |
| 694 | } |
| 695 | |
| 696 | if (args->num_cliprects != 0) { |
| 697 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); |
| 698 | return -EINVAL; |
| 699 | } else { |
| 700 | if (args->DR4 == 0xffffffff) { |
| 701 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); |
| 702 | args->DR4 = 0; |
| 703 | } |
| 704 | |
| 705 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { |
| 706 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); |
| 707 | return -EINVAL; |
| 708 | } |
| 709 | } |
| 710 | |
| 711 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
| 712 | DRM_DEBUG("sol reset is gen7 only\n"); |
| 713 | return -EINVAL; |
| 714 | } |
| 715 | |
| 716 | ret = execlists_move_to_gpu(ringbuf, vmas); |
| 717 | if (ret) |
| 718 | return ret; |
| 719 | |
| 720 | if (ring == &dev_priv->ring[RCS] && |
| 721 | instp_mode != dev_priv->relative_constants_mode) { |
| 722 | ret = intel_logical_ring_begin(ringbuf, 4); |
| 723 | if (ret) |
| 724 | return ret; |
| 725 | |
| 726 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
| 727 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); |
| 728 | intel_logical_ring_emit(ringbuf, INSTPM); |
| 729 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); |
| 730 | intel_logical_ring_advance(ringbuf); |
| 731 | |
| 732 | dev_priv->relative_constants_mode = instp_mode; |
| 733 | } |
| 734 | |
| 735 | ret = ring->emit_bb_start(ringbuf, exec_start, flags); |
| 736 | if (ret) |
| 737 | return ret; |
| 738 | |
| 739 | i915_gem_execbuffer_move_to_active(vmas, ring); |
| 740 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); |
| 741 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 742 | return 0; |
| 743 | } |
| 744 | |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 745 | void intel_execlists_retire_requests(struct intel_engine_cs *ring) |
| 746 | { |
| 747 | struct intel_ctx_submit_request *req, *tmp; |
| 748 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 749 | unsigned long flags; |
| 750 | struct list_head retired_list; |
| 751 | |
| 752 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
| 753 | if (list_empty(&ring->execlist_retired_req_list)) |
| 754 | return; |
| 755 | |
| 756 | INIT_LIST_HEAD(&retired_list); |
| 757 | spin_lock_irqsave(&ring->execlist_lock, flags); |
| 758 | list_replace_init(&ring->execlist_retired_req_list, &retired_list); |
| 759 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
| 760 | |
| 761 | list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 762 | struct intel_context *ctx = req->ctx; |
| 763 | struct drm_i915_gem_object *ctx_obj = |
| 764 | ctx->engine[ring->id].state; |
| 765 | |
| 766 | if (ctx_obj && (ctx != ring->default_context)) |
| 767 | intel_lr_context_unpin(ring, ctx); |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 768 | intel_runtime_pm_put(dev_priv); |
| 769 | i915_gem_context_unreference(req->ctx); |
| 770 | list_del(&req->execlist_link); |
| 771 | kfree(req); |
| 772 | } |
| 773 | } |
| 774 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 775 | void intel_logical_ring_stop(struct intel_engine_cs *ring) |
| 776 | { |
Oscar Mateo | 9832b9d | 2014-07-24 17:04:30 +0100 | [diff] [blame] | 777 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 778 | int ret; |
| 779 | |
| 780 | if (!intel_ring_initialized(ring)) |
| 781 | return; |
| 782 | |
| 783 | ret = intel_ring_idle(ring); |
| 784 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) |
| 785 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 786 | ring->name, ret); |
| 787 | |
| 788 | /* TODO: Is this correct with Execlists enabled? */ |
| 789 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); |
| 790 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
| 791 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); |
| 792 | return; |
| 793 | } |
| 794 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 795 | } |
| 796 | |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 797 | int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf) |
| 798 | { |
| 799 | struct intel_engine_cs *ring = ringbuf->ring; |
| 800 | int ret; |
| 801 | |
| 802 | if (!ring->gpu_caches_dirty) |
| 803 | return 0; |
| 804 | |
| 805 | ret = ring->emit_flush(ringbuf, 0, I915_GEM_GPU_DOMAINS); |
| 806 | if (ret) |
| 807 | return ret; |
| 808 | |
| 809 | ring->gpu_caches_dirty = false; |
| 810 | return 0; |
| 811 | } |
| 812 | |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 813 | /** |
| 814 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload |
| 815 | * @ringbuf: Logical Ringbuffer to advance. |
| 816 | * |
| 817 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What |
| 818 | * really happens during submission is that the context and current tail will be placed |
| 819 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that |
| 820 | * point, the tail *inside* the context is updated and the ELSP written to. |
| 821 | */ |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 822 | void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf) |
| 823 | { |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 824 | struct intel_engine_cs *ring = ringbuf->ring; |
| 825 | struct intel_context *ctx = ringbuf->FIXME_lrc_ctx; |
| 826 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 827 | intel_logical_ring_advance(ringbuf); |
| 828 | |
Ben Widawsky | 84b790f | 2014-07-24 17:04:36 +0100 | [diff] [blame] | 829 | if (intel_ring_stopped(ring)) |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 830 | return; |
| 831 | |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 832 | execlists_context_queue(ring, ctx, ringbuf->tail); |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 833 | } |
| 834 | |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 835 | static int intel_lr_context_pin(struct intel_engine_cs *ring, |
| 836 | struct intel_context *ctx) |
| 837 | { |
| 838 | struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 839 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 840 | int ret = 0; |
| 841 | |
| 842 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
| 843 | if (ctx->engine[ring->id].unpin_count++ == 0) { |
| 844 | ret = i915_gem_obj_ggtt_pin(ctx_obj, |
| 845 | GEN8_LR_CONTEXT_ALIGN, 0); |
| 846 | if (ret) |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 847 | goto reset_unpin_count; |
| 848 | |
| 849 | ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); |
| 850 | if (ret) |
| 851 | goto unpin_ctx_obj; |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 852 | } |
| 853 | |
| 854 | return ret; |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 855 | |
| 856 | unpin_ctx_obj: |
| 857 | i915_gem_object_ggtt_unpin(ctx_obj); |
| 858 | reset_unpin_count: |
| 859 | ctx->engine[ring->id].unpin_count = 0; |
| 860 | |
| 861 | return ret; |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 862 | } |
| 863 | |
| 864 | void intel_lr_context_unpin(struct intel_engine_cs *ring, |
| 865 | struct intel_context *ctx) |
| 866 | { |
| 867 | struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 868 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 869 | |
| 870 | if (ctx_obj) { |
| 871 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 872 | if (--ctx->engine[ring->id].unpin_count == 0) { |
| 873 | intel_unpin_ringbuffer_obj(ringbuf); |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 874 | i915_gem_object_ggtt_unpin(ctx_obj); |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 875 | } |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 876 | } |
| 877 | } |
| 878 | |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 879 | static int logical_ring_alloc_request(struct intel_engine_cs *ring, |
| 880 | struct intel_context *ctx) |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 881 | { |
John Harrison | 9eba5d4 | 2014-11-24 18:49:23 +0000 | [diff] [blame] | 882 | struct drm_i915_gem_request *request; |
John Harrison | 67e2937 | 2014-12-05 13:49:35 +0000 | [diff] [blame] | 883 | struct drm_i915_private *dev_private = ring->dev->dev_private; |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 884 | int ret; |
| 885 | |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 886 | if (ring->outstanding_lazy_request) |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 887 | return 0; |
| 888 | |
John Harrison | aaeb1ba | 2014-12-05 13:49:34 +0000 | [diff] [blame] | 889 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
John Harrison | 9eba5d4 | 2014-11-24 18:49:23 +0000 | [diff] [blame] | 890 | if (request == NULL) |
| 891 | return -ENOMEM; |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 892 | |
John Harrison | 9eba5d4 | 2014-11-24 18:49:23 +0000 | [diff] [blame] | 893 | if (ctx != ring->default_context) { |
| 894 | ret = intel_lr_context_pin(ring, ctx); |
| 895 | if (ret) { |
| 896 | kfree(request); |
| 897 | return ret; |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 898 | } |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 899 | } |
| 900 | |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 901 | kref_init(&request->ref); |
John Harrison | ff79e85 | 2014-11-24 18:49:41 +0000 | [diff] [blame] | 902 | request->ring = ring; |
John Harrison | 67e2937 | 2014-12-05 13:49:35 +0000 | [diff] [blame] | 903 | request->uniq = dev_private->request_uniq++; |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 904 | |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 905 | ret = i915_gem_get_seqno(ring->dev, &request->seqno); |
John Harrison | 9eba5d4 | 2014-11-24 18:49:23 +0000 | [diff] [blame] | 906 | if (ret) { |
| 907 | intel_lr_context_unpin(ring, ctx); |
| 908 | kfree(request); |
| 909 | return ret; |
| 910 | } |
| 911 | |
| 912 | /* Hold a reference to the context this request belongs to |
| 913 | * (we will need it when the time comes to emit/retire the |
| 914 | * request). |
| 915 | */ |
| 916 | request->ctx = ctx; |
| 917 | i915_gem_context_reference(request->ctx); |
| 918 | |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 919 | ring->outstanding_lazy_request = request; |
John Harrison | 9eba5d4 | 2014-11-24 18:49:23 +0000 | [diff] [blame] | 920 | return 0; |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 921 | } |
| 922 | |
| 923 | static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, |
| 924 | int bytes) |
| 925 | { |
| 926 | struct intel_engine_cs *ring = ringbuf->ring; |
| 927 | struct drm_i915_gem_request *request; |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 928 | int ret; |
| 929 | |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 930 | if (intel_ring_space(ringbuf) >= bytes) |
| 931 | return 0; |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 932 | |
| 933 | list_for_each_entry(request, &ring->request_list, list) { |
Dave Gordon | 57e2151 | 2014-11-18 20:07:20 +0000 | [diff] [blame] | 934 | /* |
| 935 | * The request queue is per-engine, so can contain requests |
| 936 | * from multiple ringbuffers. Here, we must ignore any that |
| 937 | * aren't from the ringbuffer we're considering. |
| 938 | */ |
| 939 | struct intel_context *ctx = request->ctx; |
| 940 | if (ctx->engine[ring->id].ringbuf != ringbuf) |
| 941 | continue; |
| 942 | |
| 943 | /* Would completion of this request free enough space? */ |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 944 | if (__intel_ring_space(request->tail, ringbuf->tail, |
| 945 | ringbuf->size) >= bytes) { |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 946 | break; |
| 947 | } |
| 948 | } |
| 949 | |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 950 | if (&request->list == &ring->request_list) |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 951 | return -ENOSPC; |
| 952 | |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 953 | ret = i915_wait_request(request); |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 954 | if (ret) |
| 955 | return ret; |
| 956 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 957 | i915_gem_retire_requests_ring(ring); |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 958 | |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 959 | return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC; |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 960 | } |
| 961 | |
| 962 | static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, |
| 963 | int bytes) |
| 964 | { |
| 965 | struct intel_engine_cs *ring = ringbuf->ring; |
| 966 | struct drm_device *dev = ring->dev; |
| 967 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 968 | unsigned long end; |
| 969 | int ret; |
| 970 | |
| 971 | ret = logical_ring_wait_request(ringbuf, bytes); |
| 972 | if (ret != -ENOSPC) |
| 973 | return ret; |
| 974 | |
| 975 | /* Force the context submission in case we have been skipping it */ |
| 976 | intel_logical_ring_advance_and_submit(ringbuf); |
| 977 | |
| 978 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 979 | * leaving it early runs the risk of corrupting GEM state (due |
| 980 | * to running on almost untested codepaths). But on resume |
| 981 | * timers don't work yet, so prevent a complete hang in that |
| 982 | * case by choosing an insanely large timeout. */ |
| 983 | end = jiffies + 60 * HZ; |
| 984 | |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 985 | ret = 0; |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 986 | do { |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 987 | if (intel_ring_space(ringbuf) >= bytes) |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 988 | break; |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 989 | |
| 990 | msleep(1); |
| 991 | |
| 992 | if (dev_priv->mm.interruptible && signal_pending(current)) { |
| 993 | ret = -ERESTARTSYS; |
| 994 | break; |
| 995 | } |
| 996 | |
| 997 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 998 | dev_priv->mm.interruptible); |
| 999 | if (ret) |
| 1000 | break; |
| 1001 | |
| 1002 | if (time_after(jiffies, end)) { |
| 1003 | ret = -EBUSY; |
| 1004 | break; |
| 1005 | } |
| 1006 | } while (1); |
| 1007 | |
| 1008 | return ret; |
| 1009 | } |
| 1010 | |
| 1011 | static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf) |
| 1012 | { |
| 1013 | uint32_t __iomem *virt; |
| 1014 | int rem = ringbuf->size - ringbuf->tail; |
| 1015 | |
| 1016 | if (ringbuf->space < rem) { |
| 1017 | int ret = logical_ring_wait_for_space(ringbuf, rem); |
| 1018 | |
| 1019 | if (ret) |
| 1020 | return ret; |
| 1021 | } |
| 1022 | |
| 1023 | virt = ringbuf->virtual_start + ringbuf->tail; |
| 1024 | rem /= 4; |
| 1025 | while (rem--) |
| 1026 | iowrite32(MI_NOOP, virt++); |
| 1027 | |
| 1028 | ringbuf->tail = 0; |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 1029 | intel_ring_update_space(ringbuf); |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 1030 | |
| 1031 | return 0; |
| 1032 | } |
| 1033 | |
| 1034 | static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes) |
| 1035 | { |
| 1036 | int ret; |
| 1037 | |
| 1038 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
| 1039 | ret = logical_ring_wrap_buffer(ringbuf); |
| 1040 | if (unlikely(ret)) |
| 1041 | return ret; |
| 1042 | } |
| 1043 | |
| 1044 | if (unlikely(ringbuf->space < bytes)) { |
| 1045 | ret = logical_ring_wait_for_space(ringbuf, bytes); |
| 1046 | if (unlikely(ret)) |
| 1047 | return ret; |
| 1048 | } |
| 1049 | |
| 1050 | return 0; |
| 1051 | } |
| 1052 | |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 1053 | /** |
| 1054 | * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands |
| 1055 | * |
| 1056 | * @ringbuf: Logical ringbuffer. |
| 1057 | * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. |
| 1058 | * |
| 1059 | * The ringbuffer might not be ready to accept the commands right away (maybe it needs to |
| 1060 | * be wrapped, or wait a bit for the tail to be updated). This function takes care of that |
| 1061 | * and also preallocates a request (every workload submission is still mediated through |
| 1062 | * requests, same as it did with legacy ringbuffer submission). |
| 1063 | * |
| 1064 | * Return: non-zero if the ringbuffer is not ready to be written to. |
| 1065 | */ |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 1066 | int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords) |
| 1067 | { |
| 1068 | struct intel_engine_cs *ring = ringbuf->ring; |
| 1069 | struct drm_device *dev = ring->dev; |
| 1070 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1071 | int ret; |
| 1072 | |
| 1073 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 1074 | dev_priv->mm.interruptible); |
| 1075 | if (ret) |
| 1076 | return ret; |
| 1077 | |
| 1078 | ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t)); |
| 1079 | if (ret) |
| 1080 | return ret; |
| 1081 | |
| 1082 | /* Preallocate the olr before touching the ring */ |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1083 | ret = logical_ring_alloc_request(ring, ringbuf->FIXME_lrc_ctx); |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 1084 | if (ret) |
| 1085 | return ret; |
| 1086 | |
| 1087 | ringbuf->space -= num_dwords * sizeof(uint32_t); |
| 1088 | return 0; |
| 1089 | } |
| 1090 | |
Michel Thierry | 771b9a5 | 2014-11-11 16:47:33 +0000 | [diff] [blame] | 1091 | static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring, |
| 1092 | struct intel_context *ctx) |
| 1093 | { |
| 1094 | int ret, i; |
| 1095 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
| 1096 | struct drm_device *dev = ring->dev; |
| 1097 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1098 | struct i915_workarounds *w = &dev_priv->workarounds; |
| 1099 | |
| 1100 | if (WARN_ON(w->count == 0)) |
| 1101 | return 0; |
| 1102 | |
| 1103 | ring->gpu_caches_dirty = true; |
| 1104 | ret = logical_ring_flush_all_caches(ringbuf); |
| 1105 | if (ret) |
| 1106 | return ret; |
| 1107 | |
| 1108 | ret = intel_logical_ring_begin(ringbuf, w->count * 2 + 2); |
| 1109 | if (ret) |
| 1110 | return ret; |
| 1111 | |
| 1112 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); |
| 1113 | for (i = 0; i < w->count; i++) { |
| 1114 | intel_logical_ring_emit(ringbuf, w->reg[i].addr); |
| 1115 | intel_logical_ring_emit(ringbuf, w->reg[i].value); |
| 1116 | } |
| 1117 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
| 1118 | |
| 1119 | intel_logical_ring_advance(ringbuf); |
| 1120 | |
| 1121 | ring->gpu_caches_dirty = true; |
| 1122 | ret = logical_ring_flush_all_caches(ringbuf); |
| 1123 | if (ret) |
| 1124 | return ret; |
| 1125 | |
| 1126 | return 0; |
| 1127 | } |
| 1128 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 1129 | static int gen8_init_common_ring(struct intel_engine_cs *ring) |
| 1130 | { |
| 1131 | struct drm_device *dev = ring->dev; |
| 1132 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1133 | |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1134 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); |
| 1135 | I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); |
| 1136 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 1137 | I915_WRITE(RING_MODE_GEN7(ring), |
| 1138 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
| 1139 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); |
| 1140 | POSTING_READ(RING_MODE_GEN7(ring)); |
| 1141 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); |
| 1142 | |
| 1143 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
| 1144 | |
| 1145 | return 0; |
| 1146 | } |
| 1147 | |
| 1148 | static int gen8_init_render_ring(struct intel_engine_cs *ring) |
| 1149 | { |
| 1150 | struct drm_device *dev = ring->dev; |
| 1151 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1152 | int ret; |
| 1153 | |
| 1154 | ret = gen8_init_common_ring(ring); |
| 1155 | if (ret) |
| 1156 | return ret; |
| 1157 | |
| 1158 | /* We need to disable the AsyncFlip performance optimisations in order |
| 1159 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
| 1160 | * programmed to '1' on all products. |
| 1161 | * |
| 1162 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
| 1163 | */ |
| 1164 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 1165 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 1166 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
| 1167 | |
Michel Thierry | 771b9a5 | 2014-11-11 16:47:33 +0000 | [diff] [blame] | 1168 | return init_workarounds_ring(ring); |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 1169 | } |
| 1170 | |
Oscar Mateo | 1564858 | 2014-07-24 17:04:32 +0100 | [diff] [blame] | 1171 | static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, |
| 1172 | u64 offset, unsigned flags) |
| 1173 | { |
Oscar Mateo | 1564858 | 2014-07-24 17:04:32 +0100 | [diff] [blame] | 1174 | bool ppgtt = !(flags & I915_DISPATCH_SECURE); |
| 1175 | int ret; |
| 1176 | |
| 1177 | ret = intel_logical_ring_begin(ringbuf, 4); |
| 1178 | if (ret) |
| 1179 | return ret; |
| 1180 | |
| 1181 | /* FIXME(BDW): Address space and security selectors. */ |
| 1182 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
| 1183 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); |
| 1184 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); |
| 1185 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
| 1186 | intel_logical_ring_advance(ringbuf); |
| 1187 | |
| 1188 | return 0; |
| 1189 | } |
| 1190 | |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1191 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) |
| 1192 | { |
| 1193 | struct drm_device *dev = ring->dev; |
| 1194 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1195 | unsigned long flags; |
| 1196 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1197 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1198 | return false; |
| 1199 | |
| 1200 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1201 | if (ring->irq_refcount++ == 0) { |
| 1202 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); |
| 1203 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1204 | } |
| 1205 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1206 | |
| 1207 | return true; |
| 1208 | } |
| 1209 | |
| 1210 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) |
| 1211 | { |
| 1212 | struct drm_device *dev = ring->dev; |
| 1213 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1214 | unsigned long flags; |
| 1215 | |
| 1216 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1217 | if (--ring->irq_refcount == 0) { |
| 1218 | I915_WRITE_IMR(ring, ~ring->irq_keep_mask); |
| 1219 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1220 | } |
| 1221 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1222 | } |
| 1223 | |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 1224 | static int gen8_emit_flush(struct intel_ringbuffer *ringbuf, |
| 1225 | u32 invalidate_domains, |
| 1226 | u32 unused) |
| 1227 | { |
| 1228 | struct intel_engine_cs *ring = ringbuf->ring; |
| 1229 | struct drm_device *dev = ring->dev; |
| 1230 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1231 | uint32_t cmd; |
| 1232 | int ret; |
| 1233 | |
| 1234 | ret = intel_logical_ring_begin(ringbuf, 4); |
| 1235 | if (ret) |
| 1236 | return ret; |
| 1237 | |
| 1238 | cmd = MI_FLUSH_DW + 1; |
| 1239 | |
| 1240 | if (ring == &dev_priv->ring[VCS]) { |
| 1241 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
| 1242 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
| 1243 | MI_FLUSH_DW_STORE_INDEX | |
| 1244 | MI_FLUSH_DW_OP_STOREDW; |
| 1245 | } else { |
| 1246 | if (invalidate_domains & I915_GEM_DOMAIN_RENDER) |
| 1247 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
| 1248 | MI_FLUSH_DW_OP_STOREDW; |
| 1249 | } |
| 1250 | |
| 1251 | intel_logical_ring_emit(ringbuf, cmd); |
| 1252 | intel_logical_ring_emit(ringbuf, |
| 1253 | I915_GEM_HWS_SCRATCH_ADDR | |
| 1254 | MI_FLUSH_DW_USE_GTT); |
| 1255 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ |
| 1256 | intel_logical_ring_emit(ringbuf, 0); /* value */ |
| 1257 | intel_logical_ring_advance(ringbuf); |
| 1258 | |
| 1259 | return 0; |
| 1260 | } |
| 1261 | |
| 1262 | static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, |
| 1263 | u32 invalidate_domains, |
| 1264 | u32 flush_domains) |
| 1265 | { |
| 1266 | struct intel_engine_cs *ring = ringbuf->ring; |
| 1267 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
| 1268 | u32 flags = 0; |
| 1269 | int ret; |
| 1270 | |
| 1271 | flags |= PIPE_CONTROL_CS_STALL; |
| 1272 | |
| 1273 | if (flush_domains) { |
| 1274 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 1275 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 1276 | } |
| 1277 | |
| 1278 | if (invalidate_domains) { |
| 1279 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 1280 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 1281 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 1282 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 1283 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 1284 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 1285 | flags |= PIPE_CONTROL_QW_WRITE; |
| 1286 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
| 1287 | } |
| 1288 | |
| 1289 | ret = intel_logical_ring_begin(ringbuf, 6); |
| 1290 | if (ret) |
| 1291 | return ret; |
| 1292 | |
| 1293 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
| 1294 | intel_logical_ring_emit(ringbuf, flags); |
| 1295 | intel_logical_ring_emit(ringbuf, scratch_addr); |
| 1296 | intel_logical_ring_emit(ringbuf, 0); |
| 1297 | intel_logical_ring_emit(ringbuf, 0); |
| 1298 | intel_logical_ring_emit(ringbuf, 0); |
| 1299 | intel_logical_ring_advance(ringbuf); |
| 1300 | |
| 1301 | return 0; |
| 1302 | } |
| 1303 | |
Oscar Mateo | e94e37a | 2014-07-24 17:04:25 +0100 | [diff] [blame] | 1304 | static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
| 1305 | { |
| 1306 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 1307 | } |
| 1308 | |
| 1309 | static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
| 1310 | { |
| 1311 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); |
| 1312 | } |
| 1313 | |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 1314 | static int gen8_emit_request(struct intel_ringbuffer *ringbuf) |
| 1315 | { |
| 1316 | struct intel_engine_cs *ring = ringbuf->ring; |
| 1317 | u32 cmd; |
| 1318 | int ret; |
| 1319 | |
| 1320 | ret = intel_logical_ring_begin(ringbuf, 6); |
| 1321 | if (ret) |
| 1322 | return ret; |
| 1323 | |
Ville Syrjälä | 8edfbb8 | 2014-11-14 18:16:56 +0200 | [diff] [blame] | 1324 | cmd = MI_STORE_DWORD_IMM_GEN4; |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 1325 | cmd |= MI_GLOBAL_GTT; |
| 1326 | |
| 1327 | intel_logical_ring_emit(ringbuf, cmd); |
| 1328 | intel_logical_ring_emit(ringbuf, |
| 1329 | (ring->status_page.gfx_addr + |
| 1330 | (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); |
| 1331 | intel_logical_ring_emit(ringbuf, 0); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1332 | intel_logical_ring_emit(ringbuf, |
| 1333 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 1334 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
| 1335 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
| 1336 | intel_logical_ring_advance_and_submit(ringbuf); |
| 1337 | |
| 1338 | return 0; |
| 1339 | } |
| 1340 | |
Thomas Daniel | e7778be | 2014-12-02 12:50:48 +0000 | [diff] [blame] | 1341 | static int gen8_init_rcs_context(struct intel_engine_cs *ring, |
| 1342 | struct intel_context *ctx) |
| 1343 | { |
| 1344 | int ret; |
| 1345 | |
| 1346 | ret = intel_logical_ring_workarounds_emit(ring, ctx); |
| 1347 | if (ret) |
| 1348 | return ret; |
| 1349 | |
| 1350 | return intel_lr_context_render_state_init(ring, ctx); |
| 1351 | } |
| 1352 | |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 1353 | /** |
| 1354 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer |
| 1355 | * |
| 1356 | * @ring: Engine Command Streamer. |
| 1357 | * |
| 1358 | */ |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1359 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring) |
| 1360 | { |
John Harrison | 6402c33 | 2014-10-31 12:00:26 +0000 | [diff] [blame] | 1361 | struct drm_i915_private *dev_priv; |
Oscar Mateo | 9832b9d | 2014-07-24 17:04:30 +0100 | [diff] [blame] | 1362 | |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 1363 | if (!intel_ring_initialized(ring)) |
| 1364 | return; |
| 1365 | |
John Harrison | 6402c33 | 2014-10-31 12:00:26 +0000 | [diff] [blame] | 1366 | dev_priv = ring->dev->dev_private; |
| 1367 | |
Oscar Mateo | 9832b9d | 2014-07-24 17:04:30 +0100 | [diff] [blame] | 1368 | intel_logical_ring_stop(ring); |
| 1369 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1370 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 1371 | |
| 1372 | if (ring->cleanup) |
| 1373 | ring->cleanup(ring); |
| 1374 | |
| 1375 | i915_cmd_parser_fini_ring(ring); |
| 1376 | |
| 1377 | if (ring->status_page.obj) { |
| 1378 | kunmap(sg_page(ring->status_page.obj->pages->sgl)); |
| 1379 | ring->status_page.obj = NULL; |
| 1380 | } |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1381 | } |
| 1382 | |
| 1383 | static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) |
| 1384 | { |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 1385 | int ret; |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 1386 | |
| 1387 | /* Intentionally left blank. */ |
| 1388 | ring->buffer = NULL; |
| 1389 | |
| 1390 | ring->dev = dev; |
| 1391 | INIT_LIST_HEAD(&ring->active_list); |
| 1392 | INIT_LIST_HEAD(&ring->request_list); |
| 1393 | init_waitqueue_head(&ring->irq_queue); |
| 1394 | |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 1395 | INIT_LIST_HEAD(&ring->execlist_queue); |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 1396 | INIT_LIST_HEAD(&ring->execlist_retired_req_list); |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 1397 | spin_lock_init(&ring->execlist_lock); |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1398 | ring->next_context_status_buffer = 0; |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 1399 | |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 1400 | ret = i915_cmd_parser_init_ring(ring); |
| 1401 | if (ret) |
| 1402 | return ret; |
| 1403 | |
Oscar Mateo | 564ddb2 | 2014-08-21 11:40:54 +0100 | [diff] [blame] | 1404 | ret = intel_lr_context_deferred_create(ring->default_context, ring); |
| 1405 | |
| 1406 | return ret; |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1407 | } |
| 1408 | |
| 1409 | static int logical_render_ring_init(struct drm_device *dev) |
| 1410 | { |
| 1411 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1412 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
Daniel Vetter | 99be1df | 2014-11-20 00:33:06 +0100 | [diff] [blame] | 1413 | int ret; |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1414 | |
| 1415 | ring->name = "render ring"; |
| 1416 | ring->id = RCS; |
| 1417 | ring->mmio_base = RENDER_RING_BASE; |
| 1418 | ring->irq_enable_mask = |
| 1419 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1420 | ring->irq_keep_mask = |
| 1421 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; |
| 1422 | if (HAS_L3_DPF(dev)) |
| 1423 | ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1424 | |
Daniel Vetter | ecfe00d | 2014-11-20 00:33:04 +0100 | [diff] [blame] | 1425 | ring->init_hw = gen8_init_render_ring; |
Thomas Daniel | e7778be | 2014-12-02 12:50:48 +0000 | [diff] [blame] | 1426 | ring->init_context = gen8_init_rcs_context; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 1427 | ring->cleanup = intel_fini_pipe_control; |
Oscar Mateo | e94e37a | 2014-07-24 17:04:25 +0100 | [diff] [blame] | 1428 | ring->get_seqno = gen8_get_seqno; |
| 1429 | ring->set_seqno = gen8_set_seqno; |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 1430 | ring->emit_request = gen8_emit_request; |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 1431 | ring->emit_flush = gen8_emit_flush_render; |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1432 | ring->irq_get = gen8_logical_ring_get_irq; |
| 1433 | ring->irq_put = gen8_logical_ring_put_irq; |
Oscar Mateo | 1564858 | 2014-07-24 17:04:32 +0100 | [diff] [blame] | 1434 | ring->emit_bb_start = gen8_emit_bb_start; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 1435 | |
Daniel Vetter | 99be1df | 2014-11-20 00:33:06 +0100 | [diff] [blame] | 1436 | ring->dev = dev; |
| 1437 | ret = logical_ring_init(dev, ring); |
| 1438 | if (ret) |
| 1439 | return ret; |
| 1440 | |
| 1441 | return intel_init_pipe_control(ring); |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1442 | } |
| 1443 | |
| 1444 | static int logical_bsd_ring_init(struct drm_device *dev) |
| 1445 | { |
| 1446 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1447 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
| 1448 | |
| 1449 | ring->name = "bsd ring"; |
| 1450 | ring->id = VCS; |
| 1451 | ring->mmio_base = GEN6_BSD_RING_BASE; |
| 1452 | ring->irq_enable_mask = |
| 1453 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1454 | ring->irq_keep_mask = |
| 1455 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1456 | |
Daniel Vetter | ecfe00d | 2014-11-20 00:33:04 +0100 | [diff] [blame] | 1457 | ring->init_hw = gen8_init_common_ring; |
Oscar Mateo | e94e37a | 2014-07-24 17:04:25 +0100 | [diff] [blame] | 1458 | ring->get_seqno = gen8_get_seqno; |
| 1459 | ring->set_seqno = gen8_set_seqno; |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 1460 | ring->emit_request = gen8_emit_request; |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 1461 | ring->emit_flush = gen8_emit_flush; |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1462 | ring->irq_get = gen8_logical_ring_get_irq; |
| 1463 | ring->irq_put = gen8_logical_ring_put_irq; |
Oscar Mateo | 1564858 | 2014-07-24 17:04:32 +0100 | [diff] [blame] | 1464 | ring->emit_bb_start = gen8_emit_bb_start; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 1465 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1466 | return logical_ring_init(dev, ring); |
| 1467 | } |
| 1468 | |
| 1469 | static int logical_bsd2_ring_init(struct drm_device *dev) |
| 1470 | { |
| 1471 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1472 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
| 1473 | |
| 1474 | ring->name = "bds2 ring"; |
| 1475 | ring->id = VCS2; |
| 1476 | ring->mmio_base = GEN8_BSD2_RING_BASE; |
| 1477 | ring->irq_enable_mask = |
| 1478 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1479 | ring->irq_keep_mask = |
| 1480 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1481 | |
Daniel Vetter | ecfe00d | 2014-11-20 00:33:04 +0100 | [diff] [blame] | 1482 | ring->init_hw = gen8_init_common_ring; |
Oscar Mateo | e94e37a | 2014-07-24 17:04:25 +0100 | [diff] [blame] | 1483 | ring->get_seqno = gen8_get_seqno; |
| 1484 | ring->set_seqno = gen8_set_seqno; |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 1485 | ring->emit_request = gen8_emit_request; |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 1486 | ring->emit_flush = gen8_emit_flush; |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1487 | ring->irq_get = gen8_logical_ring_get_irq; |
| 1488 | ring->irq_put = gen8_logical_ring_put_irq; |
Oscar Mateo | 1564858 | 2014-07-24 17:04:32 +0100 | [diff] [blame] | 1489 | ring->emit_bb_start = gen8_emit_bb_start; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 1490 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1491 | return logical_ring_init(dev, ring); |
| 1492 | } |
| 1493 | |
| 1494 | static int logical_blt_ring_init(struct drm_device *dev) |
| 1495 | { |
| 1496 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1497 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
| 1498 | |
| 1499 | ring->name = "blitter ring"; |
| 1500 | ring->id = BCS; |
| 1501 | ring->mmio_base = BLT_RING_BASE; |
| 1502 | ring->irq_enable_mask = |
| 1503 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1504 | ring->irq_keep_mask = |
| 1505 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1506 | |
Daniel Vetter | ecfe00d | 2014-11-20 00:33:04 +0100 | [diff] [blame] | 1507 | ring->init_hw = gen8_init_common_ring; |
Oscar Mateo | e94e37a | 2014-07-24 17:04:25 +0100 | [diff] [blame] | 1508 | ring->get_seqno = gen8_get_seqno; |
| 1509 | ring->set_seqno = gen8_set_seqno; |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 1510 | ring->emit_request = gen8_emit_request; |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 1511 | ring->emit_flush = gen8_emit_flush; |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1512 | ring->irq_get = gen8_logical_ring_get_irq; |
| 1513 | ring->irq_put = gen8_logical_ring_put_irq; |
Oscar Mateo | 1564858 | 2014-07-24 17:04:32 +0100 | [diff] [blame] | 1514 | ring->emit_bb_start = gen8_emit_bb_start; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 1515 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1516 | return logical_ring_init(dev, ring); |
| 1517 | } |
| 1518 | |
| 1519 | static int logical_vebox_ring_init(struct drm_device *dev) |
| 1520 | { |
| 1521 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1522 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
| 1523 | |
| 1524 | ring->name = "video enhancement ring"; |
| 1525 | ring->id = VECS; |
| 1526 | ring->mmio_base = VEBOX_RING_BASE; |
| 1527 | ring->irq_enable_mask = |
| 1528 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1529 | ring->irq_keep_mask = |
| 1530 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1531 | |
Daniel Vetter | ecfe00d | 2014-11-20 00:33:04 +0100 | [diff] [blame] | 1532 | ring->init_hw = gen8_init_common_ring; |
Oscar Mateo | e94e37a | 2014-07-24 17:04:25 +0100 | [diff] [blame] | 1533 | ring->get_seqno = gen8_get_seqno; |
| 1534 | ring->set_seqno = gen8_set_seqno; |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 1535 | ring->emit_request = gen8_emit_request; |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 1536 | ring->emit_flush = gen8_emit_flush; |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1537 | ring->irq_get = gen8_logical_ring_get_irq; |
| 1538 | ring->irq_put = gen8_logical_ring_put_irq; |
Oscar Mateo | 1564858 | 2014-07-24 17:04:32 +0100 | [diff] [blame] | 1539 | ring->emit_bb_start = gen8_emit_bb_start; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 1540 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1541 | return logical_ring_init(dev, ring); |
| 1542 | } |
| 1543 | |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 1544 | /** |
| 1545 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers |
| 1546 | * @dev: DRM device. |
| 1547 | * |
| 1548 | * This function inits the engines for an Execlists submission style (the equivalent in the |
| 1549 | * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for |
| 1550 | * those engines that are present in the hardware. |
| 1551 | * |
| 1552 | * Return: non-zero if the initialization failed. |
| 1553 | */ |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 1554 | int intel_logical_rings_init(struct drm_device *dev) |
| 1555 | { |
| 1556 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1557 | int ret; |
| 1558 | |
| 1559 | ret = logical_render_ring_init(dev); |
| 1560 | if (ret) |
| 1561 | return ret; |
| 1562 | |
| 1563 | if (HAS_BSD(dev)) { |
| 1564 | ret = logical_bsd_ring_init(dev); |
| 1565 | if (ret) |
| 1566 | goto cleanup_render_ring; |
| 1567 | } |
| 1568 | |
| 1569 | if (HAS_BLT(dev)) { |
| 1570 | ret = logical_blt_ring_init(dev); |
| 1571 | if (ret) |
| 1572 | goto cleanup_bsd_ring; |
| 1573 | } |
| 1574 | |
| 1575 | if (HAS_VEBOX(dev)) { |
| 1576 | ret = logical_vebox_ring_init(dev); |
| 1577 | if (ret) |
| 1578 | goto cleanup_blt_ring; |
| 1579 | } |
| 1580 | |
| 1581 | if (HAS_BSD2(dev)) { |
| 1582 | ret = logical_bsd2_ring_init(dev); |
| 1583 | if (ret) |
| 1584 | goto cleanup_vebox_ring; |
| 1585 | } |
| 1586 | |
| 1587 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
| 1588 | if (ret) |
| 1589 | goto cleanup_bsd2_ring; |
| 1590 | |
| 1591 | return 0; |
| 1592 | |
| 1593 | cleanup_bsd2_ring: |
| 1594 | intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); |
| 1595 | cleanup_vebox_ring: |
| 1596 | intel_logical_ring_cleanup(&dev_priv->ring[VECS]); |
| 1597 | cleanup_blt_ring: |
| 1598 | intel_logical_ring_cleanup(&dev_priv->ring[BCS]); |
| 1599 | cleanup_bsd_ring: |
| 1600 | intel_logical_ring_cleanup(&dev_priv->ring[VCS]); |
| 1601 | cleanup_render_ring: |
| 1602 | intel_logical_ring_cleanup(&dev_priv->ring[RCS]); |
| 1603 | |
| 1604 | return ret; |
| 1605 | } |
| 1606 | |
Oscar Mateo | 564ddb2 | 2014-08-21 11:40:54 +0100 | [diff] [blame] | 1607 | int intel_lr_context_render_state_init(struct intel_engine_cs *ring, |
| 1608 | struct intel_context *ctx) |
| 1609 | { |
| 1610 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
| 1611 | struct render_state so; |
| 1612 | struct drm_i915_file_private *file_priv = ctx->file_priv; |
| 1613 | struct drm_file *file = file_priv ? file_priv->file : NULL; |
| 1614 | int ret; |
| 1615 | |
| 1616 | ret = i915_gem_render_state_prepare(ring, &so); |
| 1617 | if (ret) |
| 1618 | return ret; |
| 1619 | |
| 1620 | if (so.rodata == NULL) |
| 1621 | return 0; |
| 1622 | |
| 1623 | ret = ring->emit_bb_start(ringbuf, |
| 1624 | so.ggtt_offset, |
| 1625 | I915_DISPATCH_SECURE); |
| 1626 | if (ret) |
| 1627 | goto out; |
| 1628 | |
| 1629 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring); |
| 1630 | |
John Harrison | 9400ae5 | 2014-11-24 18:49:36 +0000 | [diff] [blame] | 1631 | ret = __i915_add_request(ring, file, so.obj); |
Oscar Mateo | 564ddb2 | 2014-08-21 11:40:54 +0100 | [diff] [blame] | 1632 | /* intel_logical_ring_add_request moves object to inactive if it |
| 1633 | * fails */ |
| 1634 | out: |
| 1635 | i915_gem_render_state_fini(&so); |
| 1636 | return ret; |
| 1637 | } |
| 1638 | |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 1639 | static int |
| 1640 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, |
| 1641 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) |
| 1642 | { |
Thomas Daniel | 2d96553 | 2014-08-19 10:13:36 +0100 | [diff] [blame] | 1643 | struct drm_device *dev = ring->dev; |
| 1644 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | ae6c480 | 2014-08-06 15:04:53 +0200 | [diff] [blame] | 1645 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 1646 | struct page *page; |
| 1647 | uint32_t *reg_state; |
| 1648 | int ret; |
| 1649 | |
Thomas Daniel | 2d96553 | 2014-08-19 10:13:36 +0100 | [diff] [blame] | 1650 | if (!ppgtt) |
| 1651 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 1652 | |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 1653 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
| 1654 | if (ret) { |
| 1655 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); |
| 1656 | return ret; |
| 1657 | } |
| 1658 | |
| 1659 | ret = i915_gem_object_get_pages(ctx_obj); |
| 1660 | if (ret) { |
| 1661 | DRM_DEBUG_DRIVER("Could not get object pages\n"); |
| 1662 | return ret; |
| 1663 | } |
| 1664 | |
| 1665 | i915_gem_object_pin_pages(ctx_obj); |
| 1666 | |
| 1667 | /* The second page of the context object contains some fields which must |
| 1668 | * be set up prior to the first execution. */ |
| 1669 | page = i915_gem_object_get_page(ctx_obj, 1); |
| 1670 | reg_state = kmap_atomic(page); |
| 1671 | |
| 1672 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM |
| 1673 | * commands followed by (reg, value) pairs. The values we are setting here are |
| 1674 | * only for the first context restore: on a subsequent save, the GPU will |
| 1675 | * recreate this batchbuffer with new values (including all the missing |
| 1676 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ |
| 1677 | if (ring->id == RCS) |
| 1678 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); |
| 1679 | else |
| 1680 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); |
| 1681 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; |
| 1682 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); |
| 1683 | reg_state[CTX_CONTEXT_CONTROL+1] = |
| 1684 | _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT); |
| 1685 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); |
| 1686 | reg_state[CTX_RING_HEAD+1] = 0; |
| 1687 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); |
| 1688 | reg_state[CTX_RING_TAIL+1] = 0; |
| 1689 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 1690 | /* Ring buffer start address is not known until the buffer is pinned. |
| 1691 | * It is written to the context image in execlists_update_context() |
| 1692 | */ |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 1693 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); |
| 1694 | reg_state[CTX_RING_BUFFER_CONTROL+1] = |
| 1695 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; |
| 1696 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; |
| 1697 | reg_state[CTX_BB_HEAD_U+1] = 0; |
| 1698 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; |
| 1699 | reg_state[CTX_BB_HEAD_L+1] = 0; |
| 1700 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; |
| 1701 | reg_state[CTX_BB_STATE+1] = (1<<5); |
| 1702 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; |
| 1703 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; |
| 1704 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; |
| 1705 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; |
| 1706 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; |
| 1707 | reg_state[CTX_SECOND_BB_STATE+1] = 0; |
| 1708 | if (ring->id == RCS) { |
| 1709 | /* TODO: according to BSpec, the register state context |
| 1710 | * for CHV does not have these. OTOH, these registers do |
| 1711 | * exist in CHV. I'm waiting for a clarification */ |
| 1712 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; |
| 1713 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; |
| 1714 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; |
| 1715 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; |
| 1716 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; |
| 1717 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; |
| 1718 | } |
| 1719 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); |
| 1720 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; |
| 1721 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; |
| 1722 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; |
| 1723 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); |
| 1724 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); |
| 1725 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); |
| 1726 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); |
| 1727 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); |
| 1728 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); |
| 1729 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); |
| 1730 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); |
| 1731 | reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]); |
| 1732 | reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]); |
| 1733 | reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]); |
| 1734 | reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]); |
| 1735 | reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]); |
| 1736 | reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]); |
| 1737 | reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]); |
| 1738 | reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]); |
| 1739 | if (ring->id == RCS) { |
| 1740 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
| 1741 | reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8; |
| 1742 | reg_state[CTX_R_PWR_CLK_STATE+1] = 0; |
| 1743 | } |
| 1744 | |
| 1745 | kunmap_atomic(reg_state); |
| 1746 | |
| 1747 | ctx_obj->dirty = 1; |
| 1748 | set_page_dirty(page); |
| 1749 | i915_gem_object_unpin_pages(ctx_obj); |
| 1750 | |
| 1751 | return 0; |
| 1752 | } |
| 1753 | |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 1754 | /** |
| 1755 | * intel_lr_context_free() - free the LRC specific bits of a context |
| 1756 | * @ctx: the LR context to free. |
| 1757 | * |
| 1758 | * The real context freeing is done in i915_gem_context_free: this only |
| 1759 | * takes care of the bits that are LRC related: the per-engine backing |
| 1760 | * objects and the logical ringbuffer. |
| 1761 | */ |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 1762 | void intel_lr_context_free(struct intel_context *ctx) |
| 1763 | { |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 1764 | int i; |
| 1765 | |
| 1766 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 1767 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1768 | |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 1769 | if (ctx_obj) { |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 1770 | struct intel_ringbuffer *ringbuf = |
| 1771 | ctx->engine[i].ringbuf; |
| 1772 | struct intel_engine_cs *ring = ringbuf->ring; |
| 1773 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 1774 | if (ctx == ring->default_context) { |
| 1775 | intel_unpin_ringbuffer_obj(ringbuf); |
| 1776 | i915_gem_object_ggtt_unpin(ctx_obj); |
| 1777 | } |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1778 | intel_destroy_ringbuffer_obj(ringbuf); |
| 1779 | kfree(ringbuf); |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 1780 | drm_gem_object_unreference(&ctx_obj->base); |
| 1781 | } |
| 1782 | } |
| 1783 | } |
| 1784 | |
| 1785 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) |
| 1786 | { |
| 1787 | int ret = 0; |
| 1788 | |
Michael H. Nguyen | 468c681 | 2014-11-13 17:51:49 +0000 | [diff] [blame] | 1789 | WARN_ON(INTEL_INFO(ring->dev)->gen < 8); |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 1790 | |
| 1791 | switch (ring->id) { |
| 1792 | case RCS: |
Michael H. Nguyen | 468c681 | 2014-11-13 17:51:49 +0000 | [diff] [blame] | 1793 | if (INTEL_INFO(ring->dev)->gen >= 9) |
| 1794 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; |
| 1795 | else |
| 1796 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 1797 | break; |
| 1798 | case VCS: |
| 1799 | case BCS: |
| 1800 | case VECS: |
| 1801 | case VCS2: |
| 1802 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; |
| 1803 | break; |
| 1804 | } |
| 1805 | |
| 1806 | return ret; |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 1807 | } |
| 1808 | |
Daniel Vetter | 70b0ea8 | 2014-11-18 09:09:32 +0100 | [diff] [blame] | 1809 | static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, |
Thomas Daniel | 1df06b7 | 2014-10-29 09:52:51 +0000 | [diff] [blame] | 1810 | struct drm_i915_gem_object *default_ctx_obj) |
| 1811 | { |
| 1812 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1813 | |
| 1814 | /* The status page is offset 0 from the default context object |
| 1815 | * in LRC mode. */ |
| 1816 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj); |
| 1817 | ring->status_page.page_addr = |
| 1818 | kmap(sg_page(default_ctx_obj->pages->sgl)); |
Thomas Daniel | 1df06b7 | 2014-10-29 09:52:51 +0000 | [diff] [blame] | 1819 | ring->status_page.obj = default_ctx_obj; |
| 1820 | |
| 1821 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), |
| 1822 | (u32)ring->status_page.gfx_addr); |
| 1823 | POSTING_READ(RING_HWS_PGA(ring->mmio_base)); |
Thomas Daniel | 1df06b7 | 2014-10-29 09:52:51 +0000 | [diff] [blame] | 1824 | } |
| 1825 | |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 1826 | /** |
| 1827 | * intel_lr_context_deferred_create() - create the LRC specific bits of a context |
| 1828 | * @ctx: LR context to create. |
| 1829 | * @ring: engine to be used with the context. |
| 1830 | * |
| 1831 | * This function can be called more than once, with different engines, if we plan |
| 1832 | * to use the context with them. The context backing objects and the ringbuffers |
| 1833 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why |
| 1834 | * the creation is a deferred call: it's better to make sure first that we need to use |
| 1835 | * a given ring with the context. |
| 1836 | * |
Masanari Iida | 32197aa | 2014-10-20 23:53:13 +0900 | [diff] [blame] | 1837 | * Return: non-zero on error. |
Oscar Mateo | 73e4d07 | 2014-07-24 17:04:48 +0100 | [diff] [blame] | 1838 | */ |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 1839 | int intel_lr_context_deferred_create(struct intel_context *ctx, |
| 1840 | struct intel_engine_cs *ring) |
| 1841 | { |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 1842 | const bool is_global_default_ctx = (ctx == ring->default_context); |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 1843 | struct drm_device *dev = ring->dev; |
| 1844 | struct drm_i915_gem_object *ctx_obj; |
| 1845 | uint32_t context_size; |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1846 | struct intel_ringbuffer *ringbuf; |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 1847 | int ret; |
| 1848 | |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 1849 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 1850 | WARN_ON(ctx->engine[ring->id].state); |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 1851 | |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 1852 | context_size = round_up(get_lr_context_size(ring), 4096); |
| 1853 | |
| 1854 | ctx_obj = i915_gem_alloc_context_obj(dev, context_size); |
| 1855 | if (IS_ERR(ctx_obj)) { |
| 1856 | ret = PTR_ERR(ctx_obj); |
| 1857 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret); |
| 1858 | return ret; |
| 1859 | } |
| 1860 | |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 1861 | if (is_global_default_ctx) { |
| 1862 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); |
| 1863 | if (ret) { |
| 1864 | DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", |
| 1865 | ret); |
| 1866 | drm_gem_object_unreference(&ctx_obj->base); |
| 1867 | return ret; |
| 1868 | } |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 1869 | } |
| 1870 | |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1871 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
| 1872 | if (!ringbuf) { |
| 1873 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", |
| 1874 | ring->name); |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1875 | ret = -ENOMEM; |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 1876 | goto error_unpin_ctx; |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1877 | } |
| 1878 | |
Daniel Vetter | 0c7dd53 | 2014-08-11 16:17:44 +0200 | [diff] [blame] | 1879 | ringbuf->ring = ring; |
Oscar Mateo | 582d67f | 2014-07-24 17:04:16 +0100 | [diff] [blame] | 1880 | ringbuf->FIXME_lrc_ctx = ctx; |
| 1881 | |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1882 | ringbuf->size = 32 * PAGE_SIZE; |
| 1883 | ringbuf->effective_size = ringbuf->size; |
| 1884 | ringbuf->head = 0; |
| 1885 | ringbuf->tail = 0; |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1886 | ringbuf->last_retired_head = -1; |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 1887 | intel_ring_update_space(ringbuf); |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1888 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 1889 | if (ringbuf->obj == NULL) { |
| 1890 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
| 1891 | if (ret) { |
| 1892 | DRM_DEBUG_DRIVER( |
| 1893 | "Failed to allocate ringbuffer obj %s: %d\n", |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1894 | ring->name, ret); |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 1895 | goto error_free_rbuf; |
| 1896 | } |
| 1897 | |
| 1898 | if (is_global_default_ctx) { |
| 1899 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); |
| 1900 | if (ret) { |
| 1901 | DRM_ERROR( |
| 1902 | "Failed to pin and map ringbuffer %s: %d\n", |
| 1903 | ring->name, ret); |
| 1904 | goto error_destroy_rbuf; |
| 1905 | } |
| 1906 | } |
| 1907 | |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 1908 | } |
| 1909 | |
| 1910 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); |
| 1911 | if (ret) { |
| 1912 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 1913 | goto error; |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1914 | } |
| 1915 | |
| 1916 | ctx->engine[ring->id].ringbuf = ringbuf; |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 1917 | ctx->engine[ring->id].state = ctx_obj; |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 1918 | |
Daniel Vetter | 70b0ea8 | 2014-11-18 09:09:32 +0100 | [diff] [blame] | 1919 | if (ctx == ring->default_context) |
| 1920 | lrc_setup_hardware_status_page(ring, ctx_obj); |
Thomas Daniel | e7778be | 2014-12-02 12:50:48 +0000 | [diff] [blame] | 1921 | else if (ring->id == RCS && !ctx->rcs_initialized) { |
Michel Thierry | 771b9a5 | 2014-11-11 16:47:33 +0000 | [diff] [blame] | 1922 | if (ring->init_context) { |
| 1923 | ret = ring->init_context(ring, ctx); |
Thomas Daniel | e7778be | 2014-12-02 12:50:48 +0000 | [diff] [blame] | 1924 | if (ret) { |
Michel Thierry | 771b9a5 | 2014-11-11 16:47:33 +0000 | [diff] [blame] | 1925 | DRM_ERROR("ring init context: %d\n", ret); |
Thomas Daniel | e7778be | 2014-12-02 12:50:48 +0000 | [diff] [blame] | 1926 | ctx->engine[ring->id].ringbuf = NULL; |
| 1927 | ctx->engine[ring->id].state = NULL; |
| 1928 | goto error; |
| 1929 | } |
Michel Thierry | 771b9a5 | 2014-11-11 16:47:33 +0000 | [diff] [blame] | 1930 | } |
| 1931 | |
Oscar Mateo | 564ddb2 | 2014-08-21 11:40:54 +0100 | [diff] [blame] | 1932 | ctx->rcs_initialized = true; |
| 1933 | } |
| 1934 | |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 1935 | return 0; |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 1936 | |
| 1937 | error: |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 1938 | if (is_global_default_ctx) |
| 1939 | intel_unpin_ringbuffer_obj(ringbuf); |
| 1940 | error_destroy_rbuf: |
| 1941 | intel_destroy_ringbuffer_obj(ringbuf); |
| 1942 | error_free_rbuf: |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 1943 | kfree(ringbuf); |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 1944 | error_unpin_ctx: |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 1945 | if (is_global_default_ctx) |
| 1946 | i915_gem_object_ggtt_unpin(ctx_obj); |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 1947 | drm_gem_object_unreference(&ctx_obj->base); |
| 1948 | return ret; |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 1949 | } |