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Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +00002/*
3 * Copyright 2012 Michael Ellerman, IBM Corporation.
4 * Copyright 2012 Benjamin Herrenschmidt, IBM Corporation
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +00005 */
6
7#ifndef _KVM_PPC_BOOK3S_XICS_H
8#define _KVM_PPC_BOOK3S_XICS_H
9
Benjamin Herrenschmidt5af50992017-04-05 17:54:56 +100010#ifdef CONFIG_KVM_XICS
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +000011/*
12 * We use a two-level tree to store interrupt source information.
13 * There are up to 1024 ICS nodes, each of which can represent
14 * 1024 sources.
15 */
16#define KVMPPC_XICS_MAX_ICS_ID 1023
17#define KVMPPC_XICS_ICS_SHIFT 10
18#define KVMPPC_XICS_IRQ_PER_ICS (1 << KVMPPC_XICS_ICS_SHIFT)
19#define KVMPPC_XICS_SRC_MASK (KVMPPC_XICS_IRQ_PER_ICS - 1)
20
21/*
22 * Interrupt source numbers below this are reserved, for example
23 * 0 is "no interrupt", and 2 is used for IPIs.
24 */
25#define KVMPPC_XICS_FIRST_IRQ 16
26#define KVMPPC_XICS_NR_IRQS ((KVMPPC_XICS_MAX_ICS_ID + 1) * \
27 KVMPPC_XICS_IRQ_PER_ICS)
28
29/* Priority value to use for disabling an interrupt */
30#define MASKED 0xff
31
Li Zhong17d48612016-11-11 12:57:35 +080032#define PQ_PRESENTED 1
33#define PQ_QUEUED 2
34
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +000035/* State for one irq source */
36struct ics_irq_state {
37 u32 number;
38 u32 server;
Li Zhong17d48612016-11-11 12:57:35 +080039 u32 pq_state;
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +000040 u8 priority;
Paul Mackerrasd19bd8622013-04-17 20:32:04 +000041 u8 saved_priority;
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +000042 u8 resend;
43 u8 masked_pending;
Paul Mackerrasb1a42862016-05-04 21:07:52 +100044 u8 lsi; /* level-sensitive interrupt */
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +000045 u8 exists;
Paul Mackerras5d375192016-08-19 15:35:56 +100046 int intr_cpu;
47 u32 host_irq;
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +000048};
49
50/* Atomic ICP state, updated with a single compare & swap */
51union kvmppc_icp_state {
52 unsigned long raw;
53 struct {
54 u8 out_ee:1;
55 u8 need_resend:1;
56 u8 cppr;
57 u8 mfrr;
58 u8 pending_pri;
59 u32 xisr;
60 };
61};
62
63/* One bit per ICS */
64#define ICP_RESEND_MAP_SIZE (KVMPPC_XICS_MAX_ICS_ID / BITS_PER_LONG + 1)
65
66struct kvmppc_icp {
67 struct kvm_vcpu *vcpu;
68 unsigned long server_num;
69 union kvmppc_icp_state state;
70 unsigned long resend_map[ICP_RESEND_MAP_SIZE];
Benjamin Herrenschmidte7d26f22013-04-17 20:31:15 +000071
72 /* Real mode might find something too hard, here's the action
73 * it might request from virtual mode
74 */
75#define XICS_RM_KICK_VCPU 0x1
76#define XICS_RM_CHECK_RESEND 0x2
Paul Mackerras25a2150b2014-06-30 20:51:14 +100077#define XICS_RM_NOTIFY_EOI 0x8
Benjamin Herrenschmidte7d26f22013-04-17 20:31:15 +000078 u32 rm_action;
79 struct kvm_vcpu *rm_kick_target;
Suresh E. Warrier5b88cda2014-11-03 15:51:59 +110080 struct kvmppc_icp *rm_resend_icp;
Benjamin Herrenschmidte7d26f22013-04-17 20:31:15 +000081 u32 rm_reject;
Paul Mackerras25a2150b2014-06-30 20:51:14 +100082 u32 rm_eoied_irq;
Benjamin Herrenschmidte7d26f22013-04-17 20:31:15 +000083
Suresh E. Warrier878610f2015-03-20 20:39:45 +110084 /* Counters for each reason we exited real mode */
85 unsigned long n_rm_kick_vcpu;
86 unsigned long n_rm_check_resend;
Suresh E. Warrier878610f2015-03-20 20:39:45 +110087 unsigned long n_rm_notify_eoi;
Suresh Warrier6e0365b2015-03-20 20:39:48 +110088 /* Counters for handling ICP processing in real mode */
89 unsigned long n_check_resend;
90 unsigned long n_reject;
Suresh E. Warrier878610f2015-03-20 20:39:45 +110091
Benjamin Herrenschmidte7d26f22013-04-17 20:31:15 +000092 /* Debug stuff for real mode */
93 union kvmppc_icp_state rm_dbgstate;
94 struct kvm_vcpu *rm_dbgtgt;
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +000095};
96
97struct kvmppc_ics {
Suresh Warrier34cb7952015-03-20 20:39:46 +110098 arch_spinlock_t lock;
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +000099 u16 icsid;
100 struct ics_irq_state irq_state[KVMPPC_XICS_IRQ_PER_ICS];
101};
102
103struct kvmppc_xics {
104 struct kvm *kvm;
Paul Mackerras5975a2e2013-04-27 00:28:37 +0000105 struct kvm_device *dev;
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +0000106 struct dentry *dentry;
107 u32 max_icsid;
Benjamin Herrenschmidte7d26f22013-04-17 20:31:15 +0000108 bool real_mode;
109 bool real_mode_dbg;
Suresh Warrier6e0365b2015-03-20 20:39:48 +1100110 u32 err_noics;
111 u32 err_noicp;
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +0000112 struct kvmppc_ics *ics[KVMPPC_XICS_MAX_ICS_ID + 1];
113};
114
115static inline struct kvmppc_icp *kvmppc_xics_find_server(struct kvm *kvm,
116 u32 nr)
117{
118 struct kvm_vcpu *vcpu = NULL;
119 int i;
120
121 kvm_for_each_vcpu(i, vcpu, kvm) {
122 if (vcpu->arch.icp && nr == vcpu->arch.icp->server_num)
123 return vcpu->arch.icp;
124 }
125 return NULL;
126}
127
128static inline struct kvmppc_ics *kvmppc_xics_find_ics(struct kvmppc_xics *xics,
129 u32 irq, u16 *source)
130{
131 u32 icsid = irq >> KVMPPC_XICS_ICS_SHIFT;
132 u16 src = irq & KVMPPC_XICS_SRC_MASK;
133 struct kvmppc_ics *ics;
134
135 if (source)
136 *source = src;
137 if (icsid > KVMPPC_XICS_MAX_ICS_ID)
138 return NULL;
139 ics = xics->ics[icsid];
140 if (!ics)
141 return NULL;
142 return ics;
143}
144
Benjamin Herrenschmidt5af50992017-04-05 17:54:56 +1000145extern unsigned long xics_rm_h_xirr(struct kvm_vcpu *vcpu);
146extern int xics_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
147 unsigned long mfrr);
148extern int xics_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr);
149extern int xics_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr);
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +0000150
Benjamin Herrenschmidt5af50992017-04-05 17:54:56 +1000151#endif /* CONFIG_KVM_XICS */
Benjamin Herrenschmidtbc5ad3f2013-04-17 20:30:26 +0000152#endif /* _KVM_PPC_BOOK3S_XICS_H */