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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 38b2df95c53be4bd5421d933ca0dabbcb82741d0 / . / drivers / media / dvb-frontends / drx39xyj / drxj.h
blob: ee7aa6aeac51d87ab620c82343518fe954666c03 [file] [log] [blame]
Devin Heitmueller38b2df92012-08-13 21:18:02 -0300[diff] [blame^]1/**
2* \file $Id: drxj.h,v 1.132 2009/12/22 12:13:48 danielg Exp $
3*
4* \brief DRXJ specific header file
5*
6* \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen
7*/
8
9/*
10* $(c) 2006-2009 Trident Microsystems, Inc. - All rights reserved.
11*
12* This software and related documentation (the 'Software') are intellectual
13* property owned by Trident and are copyright of Trident, unless specifically
14* noted otherwise.
15*
16* Any use of the Software is permitted only pursuant to the terms of the
17* license agreement, if any, which accompanies, is included with or applicable
18* to the Software ('License Agreement') or upon express written consent of
19* Trident. Any copying, reproduction or redistribution of the Software in
20* whole or in part by any means not in accordance with the License Agreement
21* or as agreed in writing by Trident is expressly prohibited.
22*
23* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
24* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
25* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND
26* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
27* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
28* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
29* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY
30* TO USE THE SOFTWARE.
31*
32* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
33* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
34* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
35* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
36* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE
37* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
38* TRIDENT'S NEGLIGENCE. $
39*
40*/
41#ifndef __DRXJ_H__
42#define __DRXJ_H__
43/*-------------------------------------------------------------------------
44INCLUDES
45-------------------------------------------------------------------------*/
46
47#include "drx_driver.h"
48#include "drx_dap_fasi.h"
49
50#ifdef __cplusplus
51extern "C" {
52#endif
53
54/* Check DRX-J specific dap condition */
55/* Multi master mode and short addr format only will not work.
56 RMW, CRC reset, broadcast and switching back to single master mode
57 cannot be done with short addr only in multi master mode. */
58#if ((DRXDAP_SINGLE_MASTER==0)&&(DRXDAPFASI_LONG_ADDR_ALLOWED==0))
59#error "Multi master mode and short addressing only is an illegal combination"
60*; /* Generate a fatal compiler error to make sure it stops here,
61 this is necesarry because not all compilers stop after a #error. */
62#endif
63
64/*-------------------------------------------------------------------------
65TYPEDEFS
66-------------------------------------------------------------------------*/
67/*============================================================================*/
68/*============================================================================*/
69/*== code support ============================================================*/
70/*============================================================================*/
71/*============================================================================*/
72
73/*============================================================================*/
74/*============================================================================*/
75/*== SCU cmd if =============================================================*/
76/*============================================================================*/
77/*============================================================================*/
78
79typedef struct {
80 u16_t command; /**< Command number */
81 u16_t parameterLen; /**< Data length in byte */
82 u16_t resultLen; /**< result length in byte */
83 u16_t *parameter; /**< General purpous param */
84 u16_t *result; /**< General purpous param */
85} DRXJSCUCmd_t, *pDRXJSCUCmd_t;
86
87
88/*============================================================================*/
89/*============================================================================*/
90/*== CTRL CFG related data structures ========================================*/
91/*============================================================================*/
92/*============================================================================*/
93
94/* extra intermediate lock state for VSB,QAM,NTSC */
95#define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1)
96
97/* OOB lock states */
98#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */
99#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */
100
101/* Intermediate powermodes for DRXJ */
102#define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8
103#define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9
104#define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10
105
106/* supstition for GPIO FNC mux */
107#define APP_O (0x0000)
108
109/*#define DRX_CTRL_BASE (0x0000)*/
110
111#define DRXJ_CTRL_CFG_BASE (0x1000)
112typedef enum {
113 DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE,
114 DRXJ_CFG_AGC_IF,
115 DRXJ_CFG_AGC_INTERNAL,
116 DRXJ_CFG_PRE_SAW,
117 DRXJ_CFG_AFE_GAIN,
118 DRXJ_CFG_SYMBOL_CLK_OFFSET,
119 DRXJ_CFG_ACCUM_CR_RS_CW_ERR,
120 DRXJ_CFG_FEC_MERS_SEQ_COUNT,
121 DRXJ_CFG_OOB_MISC,
122 DRXJ_CFG_SMART_ANT,
123 DRXJ_CFG_OOB_PRE_SAW,
124 DRXJ_CFG_VSB_MISC,
125 DRXJ_CFG_RESET_PACKET_ERR,
126
127 /* ATV (FM) */
128 DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */
129 DRXJ_CFG_ATV_MISC,
130 DRXJ_CFG_ATV_EQU_COEF,
131 DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */
132
133 DRXJ_CFG_MPEG_OUTPUT_MISC,
134 DRXJ_CFG_HW_CFG,
135 DRXJ_CFG_OOB_LO_POW,
136
137 DRXJ_CFG_MAX /* dummy, never to be used */
138
139} DRXJCfgType_t, *pDRXJCfgType_t;
140
141/**
142* /struct DRXJCfgSmartAntIO_t
143* smart antenna i/o.
144*/
145typedef enum DRXJCfgSmartAntIO_t {
146 DRXJ_SMT_ANT_OUTPUT = 0,
147 DRXJ_SMT_ANT_INPUT
148} DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t;
149
150/**
151* /struct DRXJCfgSmartAnt_t
152* Set smart antenna.
153*/
154typedef struct {
155 DRXJCfgSmartAntIO_t io;
156 u16_t ctrlData;
157} DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t;
158
159/**
160* /struct DRXJAGCSTATUS_t
161* AGC status information from the DRXJ-IQM-AF.
162*/
163typedef struct {
164 u16_t IFAGC;
165 u16_t RFAGC;
166 u16_t DigitalAGC;
167}DRXJAgcStatus_t, *pDRXJAgcStatus_t;
168
169/* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */
170
171/**
172* /struct DRXJAgcCtrlMode_t
173* Available AGCs modes in the DRXJ.
174*/
175typedef enum {
176 DRX_AGC_CTRL_AUTO = 0,
177 DRX_AGC_CTRL_USER,
178 DRX_AGC_CTRL_OFF
179} DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t;
180
181/**
182* /struct DRXJCfgAgc_t
183* Generic interface for all AGCs present on the DRXJ.
184*/
185typedef struct {
186 DRXStandard_t standard; /* standard for which these settings apply */
187 DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */
188 u16_t outputLevel; /* range dependent on AGC */
189 u16_t minOutputLevel; /* range dependent on AGC */
190 u16_t maxOutputLevel; /* range dependent on AGC */
191 u16_t speed; /* range dependent on AGC */
192 u16_t top; /* rf-agc take over point */
193 u16_t cutOffCurrent; /* rf-agc is accelerated if output current
194 is below cut-off current */
195}DRXJCfgAgc_t, *pDRXJCfgAgc_t;
196
197/* DRXJ_CFG_PRE_SAW */
198
199/**
200* /struct DRXJCfgPreSaw_t
201* Interface to configure pre SAW sense.
202*/
203typedef struct {
204 DRXStandard_t standard; /* standard to which these settings apply */
205 u16_t reference; /* pre SAW reference value, range 0 .. 31 */
206 Bool_t usePreSaw; /* TRUE algorithms must use pre SAW sense */
207} DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t;
208
209/* DRXJ_CFG_AFE_GAIN */
210
211/**
212* /struct DRXJCfgAfeGain_t
213* Interface to configure gain of AFE (LNA + PGA).
214*/
215typedef struct {
216 DRXStandard_t standard; /* standard to which these settings apply */
217 u16_t gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */
218} DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t;
219
220/**
221* /struct DRXJRSErrors_t
222* Available failure information in DRXJ_FEC_RS.
223*
224* Container for errors that are received in the most recently finished measurment period
225*
226*/
227typedef struct {
228 u16_t nrBitErrors; /**< no of pre RS bit errors */
229 u16_t nrSymbolErrors; /**< no of pre RS symbol errors */
230 u16_t nrPacketErrors; /**< no of pre RS packet errors */
231 u16_t nrFailures; /**< no of post RS failures to decode */
232 u16_t nrSncParFailCount; /**< no of post RS bit erros */
233} DRXJRSErrors_t, *pDRXJRSErrors_t;
234
235/**
236* /struct DRXJCfgVSBMisc_t
237* symbol error rate
238*/
239typedef struct{
240 u32_t symbError; /**< symbol error rate sps */
241}DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t;
242
243/**
244* /enum DRXJMpegOutputClockRate_t
245* Mpeg output clock rate.
246*
247*/
248typedef enum {
249 DRXJ_MPEG_START_WIDTH_1CLKCYC,
250 DRXJ_MPEG_START_WIDTH_8CLKCYC
251} DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t;
252
253/**
254* /enum DRXJMpegOutputClockRate_t
255* Mpeg output clock rate.
256*
257*/
258typedef enum {
259 DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO,
260 DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K,
261 DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K,
262 DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K,
263 DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K,
264 DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K,
265 DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K
266} DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t;
267
268/**
269* /struct DRXJCfgMisc_t
270* Change TEI bit of MPEG output
271* reverse MPEG output bit order
272* set MPEG output clock rate
273*/
274typedef struct{
275 Bool_t disableTEIHandling; /**< if TRUE pass (not change) TEI bit */
276 Bool_t bitReverseMpegOutout; /**< if TRUE, parallel: msb on MD0; serial: lsb out first */
277 DRXJMpegOutputClockRate_t mpegOutputClockRate; /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */
278 DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */
279}DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t;
280
281/**
282* /enum DRXJXtalFreq_t
283* Supported external crystal reference frequency.
284*/
285typedef enum{
286 DRXJ_XTAL_FREQ_RSVD,
287 DRXJ_XTAL_FREQ_27MHZ,
288 DRXJ_XTAL_FREQ_20P25MHZ,
289 DRXJ_XTAL_FREQ_4MHZ
290}DRXJXtalFreq_t, *pDRXJXtalFreq_t;
291
292/**
293* /enum DRXJXtalFreq_t
294* Supported external crystal reference frequency.
295*/
296typedef enum{
297 DRXJ_I2C_SPEED_400KBPS,
298 DRXJ_I2C_SPEED_100KBPS
299}DRXJI2CSpeed_t, *pDRXJI2CSpeed_t;
300
301/**
302* /struct DRXJCfgHwCfg_t
303* Get hw configuration, such as crystal reference frequency, I2C speed, etc...
304*/
305typedef struct{
306 DRXJXtalFreq_t xtalFreq; /**< crystal reference frequency */
307 DRXJI2CSpeed_t i2cSpeed; /**< 100 or 400 kbps */
308}DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t;
309
310/*
311 * DRXJ_CFG_ATV_MISC
312 */
313typedef struct{
314 s16_t peakFilter; /* -8 .. 15 */
315 u16_t noiseFilter; /* 0 .. 15 */
316}DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t;
317
318/*
319 * DRXJCfgOOBMisc_t
320 */
321#define DRXJ_OOB_STATE_RESET 0x0
322#define DRXJ_OOB_STATE_AGN_HUNT 0x1
323#define DRXJ_OOB_STATE_DGN_HUNT 0x2
324#define DRXJ_OOB_STATE_AGC_HUNT 0x3
325#define DRXJ_OOB_STATE_FRQ_HUNT 0x4
326#define DRXJ_OOB_STATE_PHA_HUNT 0x8
327#define DRXJ_OOB_STATE_TIM_HUNT 0x10
328#define DRXJ_OOB_STATE_EQU_HUNT 0x20
329#define DRXJ_OOB_STATE_EQT_HUNT 0x30
330#define DRXJ_OOB_STATE_SYNC 0x40
331
332typedef struct{
333 DRXJAgcStatus_t agc;
334 Bool_t eqLock;
335 Bool_t symTimingLock;
336 Bool_t phaseLock;
337 Bool_t freqLock;
338 Bool_t digGainLock;
339 Bool_t anaGainLock;
340 u8_t state;
341}DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t;
342
343/*
344 * Index of in array of coef
345 */
346typedef enum {
347 DRXJ_OOB_LO_POW_MINUS0DB = 0,
348 DRXJ_OOB_LO_POW_MINUS5DB,
349 DRXJ_OOB_LO_POW_MINUS10DB,
350 DRXJ_OOB_LO_POW_MINUS15DB,
351 DRXJ_OOB_LO_POW_MAX
352} DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t;
353
354/*
355 * DRXJ_CFG_ATV_EQU_COEF
356 */
357typedef struct {
358 s16_t coef0; /* -256 .. 255 */
359 s16_t coef1; /* -256 .. 255 */
360 s16_t coef2; /* -256 .. 255 */
361 s16_t coef3; /* -256 .. 255 */
362} DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t;
363
364/*
365 * Index of in array of coef
366 */
367typedef enum {
368 DRXJ_COEF_IDX_MN = 0,
369 DRXJ_COEF_IDX_FM ,
370 DRXJ_COEF_IDX_L ,
371 DRXJ_COEF_IDX_LP ,
372 DRXJ_COEF_IDX_BG ,
373 DRXJ_COEF_IDX_DK ,
374 DRXJ_COEF_IDX_I ,
375 DRXJ_COEF_IDX_MAX
376} DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t;
377
378/*
379 * DRXJ_CFG_ATV_OUTPUT
380 */
381
382/**
383* /enum DRXJAttenuation_t
384* Attenuation setting for SIF AGC.
385*
386*/
387typedef enum {
388 DRXJ_SIF_ATTENUATION_0DB,
389 DRXJ_SIF_ATTENUATION_3DB,
390 DRXJ_SIF_ATTENUATION_6DB,
391 DRXJ_SIF_ATTENUATION_9DB
392} DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t;
393
394/**
395* /struct DRXJCfgAtvOutput_t
396* SIF attenuation setting.
397*
398*/
399typedef struct {
400 Bool_t enableCVBSOutput; /* TRUE= enabled */
401 Bool_t enableSIFOutput; /* TRUE= enabled */
402 DRXJSIFAttenuation_t sifAttenuation;
403} DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t;
404
405/*
406 DRXJ_CFG_ATV_AGC_STATUS (get only)
407*/
408/* TODO : AFE interface not yet finished, subject to change */
409typedef struct {
410 u16_t rfAgcGain ; /* 0 .. 877 uA */
411 u16_t ifAgcGain ; /* 0 .. 877 uA */
412 s16_t videoAgcGain ; /* -75 .. 1972 in 0.1 dB steps */
413 s16_t audioAgcGain ; /* -4 .. 1020 in 0.1 dB steps */
414 u16_t rfAgcLoopGain ; /* 0 .. 7 */
415 u16_t ifAgcLoopGain ; /* 0 .. 7 */
416 u16_t videoAgcLoopGain; /* 0 .. 7 */
417} DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t;
418
419/*============================================================================*/
420/*============================================================================*/
421/*== CTRL related data structures ============================================*/
422/*============================================================================*/
423/*============================================================================*/
424
425/* NONE */
426
427/*============================================================================*/
428/*============================================================================*/
429
430/*========================================*/
431/**
432* /struct DRXJData_t
433* DRXJ specific attributes.
434*
435* Global data container for DRXJ specific data.
436*
437*/
438typedef struct {
439 /* device capabilties (determined during DRX_Open()) */
440 Bool_t hasLNA; /**< TRUE if LNA (aka PGA) present */
441 Bool_t hasOOB; /**< TRUE if OOB supported */
442 Bool_t hasNTSC; /**< TRUE if NTSC supported */
443 Bool_t hasBTSC; /**< TRUE if BTSC supported */
444 Bool_t hasSMATX; /**< TRUE if mat_tx is available */
445 Bool_t hasSMARX; /**< TRUE if mat_rx is available */
446 Bool_t hasGPIO; /**< TRUE if GPIO is available */
447 Bool_t hasIRQN; /**< TRUE if IRQN is available */
448 /* A1/A2/A... */
449 u8_t mfx; /**< metal fix */
450
451 /* tuner settings */
452 Bool_t mirrorFreqSpectOOB; /**< tuner inversion (TRUE = tuner mirrors the signal */
453
454 /* standard/channel settings */
455 DRXStandard_t standard; /**< current standard information */
456 DRXConstellation_t constellation; /**< current constellation */
457 DRXFrequency_t frequency; /**< center signal frequency in KHz */
458 DRXBandwidth_t currBandwidth; /**< current channel bandwidth */
459 DRXMirror_t mirror; /**< current channel mirror */
460
461 /* signal quality information */
462 u32_t fecBitsDesired; /**< BER accounting period */
463 u16_t fecVdPlen; /**< no of trellis symbols: VD SER measurement period */
464 u16_t qamVdPrescale; /**< Viterbi Measurement Prescale */
465 u16_t qamVdPeriod; /**< Viterbi Measurement period */
466 u16_t fecRsPlen; /**< defines RS BER measurement period */
467 u16_t fecRsPrescale; /**< ReedSolomon Measurement Prescale */
468 u16_t fecRsPeriod; /**< ReedSolomon Measurement period */
469 Bool_t resetPktErrAcc; /**< Set a flag to reset accumulated packet error */
470 u16_t pktErrAccStart; /**< Set a flag to reset accumulated packet error */
471
472 /* HI configuration */
473 u16_t HICfgTimingDiv; /**< HI Configure() parameter 2 */
474 u16_t HICfgBridgeDelay; /**< HI Configure() parameter 3 */
475 u16_t HICfgWakeUpKey; /**< HI Configure() parameter 4 */
476 u16_t HICfgCtrl; /**< HI Configure() parameter 5 */
477 u16_t HICfgTransmit; /**< HI Configure() parameter 6 */
478
479 /* UIO configuartion */
480 DRXUIOMode_t uioSmaRxMode; /**< current mode of SmaRx pin */
481 DRXUIOMode_t uioSmaTxMode; /**< current mode of SmaTx pin */
482 DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */
483 DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */
484
485 /* IQM fs frequecy shift and inversion */
486 u32_t iqmFsRateOfs; /**< frequency shifter setting after setchannel */
487 Bool_t posImage; /**< Ture: positive image */
488 /* IQM RC frequecy shift */
489 u32_t iqmRcRateOfs; /**< frequency shifter setting after setchannel */
490
491 /* ATV configuartion */
492 u32_t atvCfgChangedFlags; /**< flag: flags cfg changes */
493 s16_t atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */
494 s16_t atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */
495 s16_t atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */
496 s16_t atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */
497 Bool_t phaseCorrectionBypass; /**< flag: TRUE=bypass */
498 s16_t atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */
499 u16_t atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */
500 Bool_t enableCVBSOutput; /**< flag CVBS ouput enable */
501 Bool_t enableSIFOutput; /**< flag SIF ouput enable */
502 DRXJSIFAttenuation_t
503 sifAttenuation; /**< current SIF att setting */
504 /* Agc configuration for QAM and VSB */
505 DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */
506 DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */
507 DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */
508 DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */
509
510 /* PGA gain configuration for QAM and VSB */
511 u16_t qamPgaCfg; /**< qam PGA config */
512 u16_t vsbPgaCfg; /**< vsb PGA config */
513
514 /* Pre SAW configuration for QAM and VSB */
515 DRXJCfgPreSaw_t qamPreSawCfg; /**< qam pre SAW config */
516 DRXJCfgPreSaw_t vsbPreSawCfg; /**< qam pre SAW config */
517
518 /* Version information */
519 char vText[2][12]; /**< allocated text versions */
520 DRXVersion_t vVersion[2]; /**< allocated versions structs */
521 DRXVersionList_t vListElements[2]; /**< allocated version list */
522
523 /* smart antenna configuration */
524 Bool_t smartAntInverted;
525
526 /* Tracking filter setting for OOB */
527 u16_t oobTrkFilterCfg[8];
528 Bool_t oobPowerOn;
529
530 /* MPEG static bitrate setting */
531 u32_t mpegTsStaticBitrate; /**< bitrate static MPEG output */
532 Bool_t disableTEIhandling; /**< MPEG TS TEI handling */
533 Bool_t bitReverseMpegOutout; /**< MPEG output bit order */
534 DRXJMpegOutputClockRate_t
535 mpegOutputClockRate; /**< MPEG output clock rate */
536 DRXJMpegStartWidth_t
537 mpegStartWidth; /**< MPEG Start width */
538
539 /* Pre SAW & Agc configuration for ATV */
540 DRXJCfgPreSaw_t atvPreSawCfg; /**< atv pre SAW config */
541 DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */
542 DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */
543 u16_t atvPgaCfg; /**< atv pga config */
544
545 u32_t currSymbolRate;
546
547 /* pin-safe mode */
548 Bool_t pdrSafeMode; /**< PDR safe mode activated */
549 u16_t pdrSafeRestoreValGpio;
550 u16_t pdrSafeRestoreValVSync;
551 u16_t pdrSafeRestoreValSmaRx;
552 u16_t pdrSafeRestoreValSmaTx;
553
554 /* OOB pre-saw value */
555 u16_t oobPreSaw;
556 DRXJCfgOobLoPower_t oobLoPow;
557
558 DRXAudData_t audData; /**< audio storage */
559
560} DRXJData_t, *pDRXJData_t;
561
562/*-------------------------------------------------------------------------
563Access MACROS
564-------------------------------------------------------------------------*/
565/**
566* \brief Compilable references to attributes
567* \param d pointer to demod instance
568*
569* Used as main reference to an attribute field.
570* Can be used by both macro implementation and function implementation.
571* These macros are defined to avoid duplication of code in macro and function
572* definitions that handle access of demod common or extended attributes.
573*
574*/
575
576#define DRXJ_ATTR_BTSC_DETECT( d ) \
577 (((pDRXJData_t)(d)->myExtAttr)->audData.btscDetect)
578
579/**
580* \brief Actual access macros
581* \param d pointer to demod instance
582* \param x value to set or to get
583*
584* SET macros must be used to set the value of an attribute.
585* GET macros must be used to retrieve the value of an attribute.
586* Depending on the value of DRX_USE_ACCESS_FUNCTIONS the macro's will be
587* substituted by "direct-access-inline-code" or a function call.
588*
589*/
590#define DRXJ_GET_BTSC_DETECT( d, x ) \
591 do { \
592 (x) = DRXJ_ATTR_BTSC_DETECT(( d ); \
593 } while(0)
594
595#define DRXJ_SET_BTSC_DETECT( d, x ) \
596 do { \
597 DRXJ_ATTR_BTSC_DETECT( d ) = (x); \
598 } while(0)
599
600
601/*-------------------------------------------------------------------------
602DEFINES
603-------------------------------------------------------------------------*/
604
605/**
606* \def DRXJ_NTSC_CARRIER_FREQ_OFFSET
607* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
608*
609* For NTSC standard.
610* NTSC channels are listed by their picture carrier frequency (Fpc).
611* The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input.
612* In case the tuner module is not used the DRX-J requires that the tuner is
613* tuned to the centre frequency of the channel:
614*
615* Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET
616*
617*/
618#define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(1750))
619
620/**
621* \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET
622* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
623*
624* For PAL/SECAM - BG standard. This define is needed in case the tuner module
625* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc).
626* The DRX-J requires that the tuner is tuned to:
627* Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET
628*
629* In case the tuner module is used the drxdriver takes care of this.
630* In case the tuner module is NOT used the application programmer must take
631* care of this.
632*
633*/
634#define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(2375))
635
636/**
637* \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET
638* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
639*
640* For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module
641* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc).
642* The DRX-J requires that the tuner is tuned to:
643* Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET
644*
645* In case the tuner module is used the drxdriver takes care of this.
646* In case the tuner module is NOT used the application programmer must take
647* care of this.
648*
649*/
650#define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(2775))
651
652/**
653* \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET
654* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
655*
656* For PAL/SECAM - LP standard. This define is needed in case the tuner module
657* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc).
658* The DRX-J requires that the tuner is tuned to:
659* Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET
660*
661* In case the tuner module is used the drxdriver takes care of this.
662* In case the tuner module is NOT used the application programmer must take
663* care of this.
664*/
665#define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(-3255))
666
667/**
668* \def DRXJ_FM_CARRIER_FREQ_OFFSET
669* \brief Offset from sound carrier to centre frequency in kHz, in RF domain
670*
671* For FM standard.
672* FM channels are listed by their sound carrier frequency (Fsc).
673* The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as
674* input.
675* In case the tuner module is not used the DRX-J requires that the tuner is
676* tuned to the Ffm frequency of the channel.
677*
678* Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET
679*
680*/
681#define DRXJ_FM_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(-3000))
682
683/* Revision types -------------------------------------------------------*/
684
685#define DRXJ_TYPE_ID (0x3946000DUL)
686
687/* Macros ---------------------------------------------------------------*/
688
689/* Convert OOB lock status to string */
690#define DRXJ_STR_OOB_LOCKSTATUS(x) ( \
691 ( x == DRX_NEVER_LOCK ) ? "Never" : \
692 ( x == DRX_NOT_LOCKED ) ? "No" : \
693 ( x == DRX_LOCKED ) ? "Locked" : \
694 ( x == DRX_LOCK_STATE_1 ) ? "AGC lock" : \
695 ( x == DRX_LOCK_STATE_2 ) ? "sync lock" : \
696 "(Invalid)" )
697
698/*-------------------------------------------------------------------------
699ENUM
700-------------------------------------------------------------------------*/
701
702/*-------------------------------------------------------------------------
703STRUCTS
704-------------------------------------------------------------------------*/
705
706/*-------------------------------------------------------------------------
707Exported FUNCTIONS
708-------------------------------------------------------------------------*/
709
710extern DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod);
711extern DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod);
712extern DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod,
713 DRXCtrlIndex_t ctrl,
714 void *ctrlData);
715
716/*-------------------------------------------------------------------------
717Exported GLOBAL VARIABLES
718-------------------------------------------------------------------------*/
719extern DRXAccessFunc_t drxDapDRXJFunct_g;
720extern DRXDemodFunc_t DRXJFunctions_g;
721extern DRXJData_t DRXJData_g;
722extern I2CDeviceAddr_t DRXJDefaultAddr_g;
723extern DRXCommonAttr_t DRXJDefaultCommAttr_g;
724extern DRXDemodInstance_t DRXJDefaultDemod_g;
725
726/*-------------------------------------------------------------------------
727THE END
728-------------------------------------------------------------------------*/
729#ifdef __cplusplus
730}
731#endif
732#endif /* __DRXJ_H__ */