Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1 | /* |
| 2 | * SuperH Ethernet device driver |
| 3 | * |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 4 | * Copyright (C) 2006-2008 Nobuhiro Iwamatsu |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 5 | * Copyright (C) 2008-2009 Renesas Solutions Corp. |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms and conditions of the GNU General Public License, |
| 9 | * version 2, as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program; if not, write to the Free Software Foundation, Inc., |
| 17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | * |
| 19 | * The full GNU General Public License is included in this distribution in |
| 20 | * the file called "COPYING". |
| 21 | */ |
| 22 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 23 | #include <linux/init.h> |
| 24 | #include <linux/dma-mapping.h> |
| 25 | #include <linux/etherdevice.h> |
| 26 | #include <linux/delay.h> |
| 27 | #include <linux/platform_device.h> |
| 28 | #include <linux/mdio-bitbang.h> |
| 29 | #include <linux/netdevice.h> |
| 30 | #include <linux/phy.h> |
| 31 | #include <linux/cache.h> |
| 32 | #include <linux/io.h> |
| 33 | |
| 34 | #include "sh_eth.h" |
| 35 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 36 | /* There is CPU dependent code */ |
| 37 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 38 | #define SH_ETH_HAS_TSU 1 |
| 39 | static void sh_eth_chip_reset(struct net_device *ndev) |
| 40 | { |
| 41 | /* reset device */ |
| 42 | ctrl_outl(ARSTR_ARSTR, ARSTR); |
| 43 | mdelay(1); |
| 44 | } |
| 45 | |
| 46 | static void sh_eth_reset(struct net_device *ndev) |
| 47 | { |
| 48 | u32 ioaddr = ndev->base_addr; |
| 49 | int cnt = 100; |
| 50 | |
| 51 | ctrl_outl(EDSR_ENALL, ioaddr + EDSR); |
| 52 | ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR); |
| 53 | while (cnt > 0) { |
| 54 | if (!(ctrl_inl(ioaddr + EDMR) & 0x3)) |
| 55 | break; |
| 56 | mdelay(1); |
| 57 | cnt--; |
| 58 | } |
| 59 | if (cnt < 0) |
| 60 | printk(KERN_ERR "Device reset fail\n"); |
| 61 | |
| 62 | /* Table Init */ |
| 63 | ctrl_outl(0x0, ioaddr + TDLAR); |
| 64 | ctrl_outl(0x0, ioaddr + TDFAR); |
| 65 | ctrl_outl(0x0, ioaddr + TDFXR); |
| 66 | ctrl_outl(0x0, ioaddr + TDFFR); |
| 67 | ctrl_outl(0x0, ioaddr + RDLAR); |
| 68 | ctrl_outl(0x0, ioaddr + RDFAR); |
| 69 | ctrl_outl(0x0, ioaddr + RDFXR); |
| 70 | ctrl_outl(0x0, ioaddr + RDFFR); |
| 71 | } |
| 72 | |
| 73 | static void sh_eth_set_duplex(struct net_device *ndev) |
| 74 | { |
| 75 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 76 | u32 ioaddr = ndev->base_addr; |
| 77 | |
| 78 | if (mdp->duplex) /* Full */ |
| 79 | ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR); |
| 80 | else /* Half */ |
| 81 | ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR); |
| 82 | } |
| 83 | |
| 84 | static void sh_eth_set_rate(struct net_device *ndev) |
| 85 | { |
| 86 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 87 | u32 ioaddr = ndev->base_addr; |
| 88 | |
| 89 | switch (mdp->speed) { |
| 90 | case 10: /* 10BASE */ |
| 91 | ctrl_outl(GECMR_10, ioaddr + GECMR); |
| 92 | break; |
| 93 | case 100:/* 100BASE */ |
| 94 | ctrl_outl(GECMR_100, ioaddr + GECMR); |
| 95 | break; |
| 96 | case 1000: /* 1000BASE */ |
| 97 | ctrl_outl(GECMR_1000, ioaddr + GECMR); |
| 98 | break; |
| 99 | default: |
| 100 | break; |
| 101 | } |
| 102 | } |
| 103 | |
| 104 | /* sh7763 */ |
| 105 | static struct sh_eth_cpu_data sh_eth_my_cpu_data = { |
| 106 | .chip_reset = sh_eth_chip_reset, |
| 107 | .set_duplex = sh_eth_set_duplex, |
| 108 | .set_rate = sh_eth_set_rate, |
| 109 | |
| 110 | .ecsr_value = ECSR_ICD | ECSR_MPD, |
| 111 | .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, |
| 112 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
| 113 | |
| 114 | .tx_check = EESR_TC1 | EESR_FTC, |
| 115 | .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ |
| 116 | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ |
| 117 | EESR_ECI, |
| 118 | .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ |
| 119 | EESR_TFE, |
| 120 | |
| 121 | .apr = 1, |
| 122 | .mpr = 1, |
| 123 | .tpauser = 1, |
| 124 | .bculr = 1, |
| 125 | .hw_swap = 1, |
| 126 | .rpadir = 1, |
| 127 | .no_trimd = 1, |
| 128 | .no_ade = 1, |
| 129 | }; |
| 130 | |
| 131 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) |
| 132 | #define SH_ETH_RESET_DEFAULT 1 |
| 133 | static struct sh_eth_cpu_data sh_eth_my_cpu_data = { |
| 134 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
| 135 | |
| 136 | .apr = 1, |
| 137 | .mpr = 1, |
| 138 | .tpauser = 1, |
| 139 | .hw_swap = 1, |
| 140 | }; |
| 141 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
| 142 | #define SH_ETH_RESET_DEFAULT 1 |
| 143 | #define SH_ETH_HAS_TSU 1 |
| 144 | static struct sh_eth_cpu_data sh_eth_my_cpu_data = { |
| 145 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
| 146 | }; |
| 147 | #endif |
| 148 | |
| 149 | static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) |
| 150 | { |
| 151 | if (!cd->ecsr_value) |
| 152 | cd->ecsr_value = DEFAULT_ECSR_INIT; |
| 153 | |
| 154 | if (!cd->ecsipr_value) |
| 155 | cd->ecsipr_value = DEFAULT_ECSIPR_INIT; |
| 156 | |
| 157 | if (!cd->fcftr_value) |
| 158 | cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \ |
| 159 | DEFAULT_FIFO_F_D_RFD; |
| 160 | |
| 161 | if (!cd->fdr_value) |
| 162 | cd->fdr_value = DEFAULT_FDR_INIT; |
| 163 | |
| 164 | if (!cd->rmcr_value) |
| 165 | cd->rmcr_value = DEFAULT_RMCR_VALUE; |
| 166 | |
| 167 | if (!cd->tx_check) |
| 168 | cd->tx_check = DEFAULT_TX_CHECK; |
| 169 | |
| 170 | if (!cd->eesr_err_check) |
| 171 | cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; |
| 172 | |
| 173 | if (!cd->tx_error_check) |
| 174 | cd->tx_error_check = DEFAULT_TX_ERROR_CHECK; |
| 175 | } |
| 176 | |
| 177 | #if defined(SH_ETH_RESET_DEFAULT) |
| 178 | /* Chip Reset */ |
| 179 | static void sh_eth_reset(struct net_device *ndev) |
| 180 | { |
| 181 | u32 ioaddr = ndev->base_addr; |
| 182 | |
| 183 | ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR); |
| 184 | mdelay(3); |
| 185 | ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR); |
| 186 | } |
| 187 | #endif |
| 188 | |
| 189 | #if defined(CONFIG_CPU_SH4) |
| 190 | static void sh_eth_set_receive_align(struct sk_buff *skb) |
| 191 | { |
| 192 | int reserve; |
| 193 | |
| 194 | reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1)); |
| 195 | if (reserve) |
| 196 | skb_reserve(skb, reserve); |
| 197 | } |
| 198 | #else |
| 199 | static void sh_eth_set_receive_align(struct sk_buff *skb) |
| 200 | { |
| 201 | skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN); |
| 202 | } |
| 203 | #endif |
| 204 | |
| 205 | |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 206 | /* CPU <-> EDMAC endian convert */ |
| 207 | static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x) |
| 208 | { |
| 209 | switch (mdp->edmac_endian) { |
| 210 | case EDMAC_LITTLE_ENDIAN: |
| 211 | return cpu_to_le32(x); |
| 212 | case EDMAC_BIG_ENDIAN: |
| 213 | return cpu_to_be32(x); |
| 214 | } |
| 215 | return x; |
| 216 | } |
| 217 | |
| 218 | static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x) |
| 219 | { |
| 220 | switch (mdp->edmac_endian) { |
| 221 | case EDMAC_LITTLE_ENDIAN: |
| 222 | return le32_to_cpu(x); |
| 223 | case EDMAC_BIG_ENDIAN: |
| 224 | return be32_to_cpu(x); |
| 225 | } |
| 226 | return x; |
| 227 | } |
| 228 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 229 | /* |
| 230 | * Program the hardware MAC address from dev->dev_addr. |
| 231 | */ |
| 232 | static void update_mac_address(struct net_device *ndev) |
| 233 | { |
| 234 | u32 ioaddr = ndev->base_addr; |
| 235 | |
| 236 | ctrl_outl((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | |
| 237 | (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), |
| 238 | ioaddr + MAHR); |
| 239 | ctrl_outl((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), |
| 240 | ioaddr + MALR); |
| 241 | } |
| 242 | |
| 243 | /* |
| 244 | * Get MAC address from SuperH MAC address register |
| 245 | * |
| 246 | * SuperH's Ethernet device doesn't have 'ROM' to MAC address. |
| 247 | * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). |
| 248 | * When you want use this device, you must set MAC address in bootloader. |
| 249 | * |
| 250 | */ |
| 251 | static void read_mac_address(struct net_device *ndev) |
| 252 | { |
| 253 | u32 ioaddr = ndev->base_addr; |
| 254 | |
| 255 | ndev->dev_addr[0] = (ctrl_inl(ioaddr + MAHR) >> 24); |
| 256 | ndev->dev_addr[1] = (ctrl_inl(ioaddr + MAHR) >> 16) & 0xFF; |
| 257 | ndev->dev_addr[2] = (ctrl_inl(ioaddr + MAHR) >> 8) & 0xFF; |
| 258 | ndev->dev_addr[3] = (ctrl_inl(ioaddr + MAHR) & 0xFF); |
| 259 | ndev->dev_addr[4] = (ctrl_inl(ioaddr + MALR) >> 8) & 0xFF; |
| 260 | ndev->dev_addr[5] = (ctrl_inl(ioaddr + MALR) & 0xFF); |
| 261 | } |
| 262 | |
| 263 | struct bb_info { |
| 264 | struct mdiobb_ctrl ctrl; |
| 265 | u32 addr; |
| 266 | u32 mmd_msk;/* MMD */ |
| 267 | u32 mdo_msk; |
| 268 | u32 mdi_msk; |
| 269 | u32 mdc_msk; |
| 270 | }; |
| 271 | |
| 272 | /* PHY bit set */ |
| 273 | static void bb_set(u32 addr, u32 msk) |
| 274 | { |
| 275 | ctrl_outl(ctrl_inl(addr) | msk, addr); |
| 276 | } |
| 277 | |
| 278 | /* PHY bit clear */ |
| 279 | static void bb_clr(u32 addr, u32 msk) |
| 280 | { |
| 281 | ctrl_outl((ctrl_inl(addr) & ~msk), addr); |
| 282 | } |
| 283 | |
| 284 | /* PHY bit read */ |
| 285 | static int bb_read(u32 addr, u32 msk) |
| 286 | { |
| 287 | return (ctrl_inl(addr) & msk) != 0; |
| 288 | } |
| 289 | |
| 290 | /* Data I/O pin control */ |
| 291 | static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) |
| 292 | { |
| 293 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); |
| 294 | if (bit) |
| 295 | bb_set(bitbang->addr, bitbang->mmd_msk); |
| 296 | else |
| 297 | bb_clr(bitbang->addr, bitbang->mmd_msk); |
| 298 | } |
| 299 | |
| 300 | /* Set bit data*/ |
| 301 | static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) |
| 302 | { |
| 303 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); |
| 304 | |
| 305 | if (bit) |
| 306 | bb_set(bitbang->addr, bitbang->mdo_msk); |
| 307 | else |
| 308 | bb_clr(bitbang->addr, bitbang->mdo_msk); |
| 309 | } |
| 310 | |
| 311 | /* Get bit data*/ |
| 312 | static int sh_get_mdio(struct mdiobb_ctrl *ctrl) |
| 313 | { |
| 314 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); |
| 315 | return bb_read(bitbang->addr, bitbang->mdi_msk); |
| 316 | } |
| 317 | |
| 318 | /* MDC pin control */ |
| 319 | static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) |
| 320 | { |
| 321 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); |
| 322 | |
| 323 | if (bit) |
| 324 | bb_set(bitbang->addr, bitbang->mdc_msk); |
| 325 | else |
| 326 | bb_clr(bitbang->addr, bitbang->mdc_msk); |
| 327 | } |
| 328 | |
| 329 | /* mdio bus control struct */ |
| 330 | static struct mdiobb_ops bb_ops = { |
| 331 | .owner = THIS_MODULE, |
| 332 | .set_mdc = sh_mdc_ctrl, |
| 333 | .set_mdio_dir = sh_mmd_ctrl, |
| 334 | .set_mdio_data = sh_set_mdio, |
| 335 | .get_mdio_data = sh_get_mdio, |
| 336 | }; |
| 337 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 338 | /* free skb and descriptor buffer */ |
| 339 | static void sh_eth_ring_free(struct net_device *ndev) |
| 340 | { |
| 341 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 342 | int i; |
| 343 | |
| 344 | /* Free Rx skb ringbuffer */ |
| 345 | if (mdp->rx_skbuff) { |
| 346 | for (i = 0; i < RX_RING_SIZE; i++) { |
| 347 | if (mdp->rx_skbuff[i]) |
| 348 | dev_kfree_skb(mdp->rx_skbuff[i]); |
| 349 | } |
| 350 | } |
| 351 | kfree(mdp->rx_skbuff); |
| 352 | |
| 353 | /* Free Tx skb ringbuffer */ |
| 354 | if (mdp->tx_skbuff) { |
| 355 | for (i = 0; i < TX_RING_SIZE; i++) { |
| 356 | if (mdp->tx_skbuff[i]) |
| 357 | dev_kfree_skb(mdp->tx_skbuff[i]); |
| 358 | } |
| 359 | } |
| 360 | kfree(mdp->tx_skbuff); |
| 361 | } |
| 362 | |
| 363 | /* format skb and descriptor buffer */ |
| 364 | static void sh_eth_ring_format(struct net_device *ndev) |
| 365 | { |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 366 | u32 ioaddr = ndev->base_addr; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 367 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 368 | int i; |
| 369 | struct sk_buff *skb; |
| 370 | struct sh_eth_rxdesc *rxdesc = NULL; |
| 371 | struct sh_eth_txdesc *txdesc = NULL; |
| 372 | int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE; |
| 373 | int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE; |
| 374 | |
| 375 | mdp->cur_rx = mdp->cur_tx = 0; |
| 376 | mdp->dirty_rx = mdp->dirty_tx = 0; |
| 377 | |
| 378 | memset(mdp->rx_ring, 0, rx_ringsize); |
| 379 | |
| 380 | /* build Rx ring buffer */ |
| 381 | for (i = 0; i < RX_RING_SIZE; i++) { |
| 382 | /* skb */ |
| 383 | mdp->rx_skbuff[i] = NULL; |
| 384 | skb = dev_alloc_skb(mdp->rx_buf_sz); |
| 385 | mdp->rx_skbuff[i] = skb; |
| 386 | if (skb == NULL) |
| 387 | break; |
Yoshihiro Shimoda | e88aae7 | 2009-05-24 23:52:35 +0000 | [diff] [blame] | 388 | dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz, |
| 389 | DMA_FROM_DEVICE); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 390 | skb->dev = ndev; /* Mark as being used by this device. */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 391 | sh_eth_set_receive_align(skb); |
| 392 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 393 | /* RX descriptor */ |
| 394 | rxdesc = &mdp->rx_ring[i]; |
Yoshihiro Shimoda | 0029d64 | 2009-05-24 23:53:20 +0000 | [diff] [blame] | 395 | rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 396 | rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 397 | |
| 398 | /* The size of the buffer is 16 byte boundary. */ |
Yoshihiro Shimoda | 0029d64 | 2009-05-24 23:53:20 +0000 | [diff] [blame] | 399 | rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 400 | /* Rx descriptor address set */ |
| 401 | if (i == 0) { |
Yoshihiro Shimoda | 0029d64 | 2009-05-24 23:53:20 +0000 | [diff] [blame] | 402 | ctrl_outl(mdp->rx_desc_dma, ioaddr + RDLAR); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 403 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
Yoshihiro Shimoda | 0029d64 | 2009-05-24 23:53:20 +0000 | [diff] [blame] | 404 | ctrl_outl(mdp->rx_desc_dma, ioaddr + RDFAR); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 405 | #endif |
| 406 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 407 | } |
| 408 | |
| 409 | mdp->dirty_rx = (u32) (i - RX_RING_SIZE); |
| 410 | |
| 411 | /* Mark the last entry as wrapping the ring. */ |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 412 | rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 413 | |
| 414 | memset(mdp->tx_ring, 0, tx_ringsize); |
| 415 | |
| 416 | /* build Tx ring buffer */ |
| 417 | for (i = 0; i < TX_RING_SIZE; i++) { |
| 418 | mdp->tx_skbuff[i] = NULL; |
| 419 | txdesc = &mdp->tx_ring[i]; |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 420 | txdesc->status = cpu_to_edmac(mdp, TD_TFP); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 421 | txdesc->buffer_length = 0; |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 422 | if (i == 0) { |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 423 | /* Tx descriptor address set */ |
Yoshihiro Shimoda | 0029d64 | 2009-05-24 23:53:20 +0000 | [diff] [blame] | 424 | ctrl_outl(mdp->tx_desc_dma, ioaddr + TDLAR); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 425 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
Yoshihiro Shimoda | 0029d64 | 2009-05-24 23:53:20 +0000 | [diff] [blame] | 426 | ctrl_outl(mdp->tx_desc_dma, ioaddr + TDFAR); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 427 | #endif |
| 428 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 429 | } |
| 430 | |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 431 | txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | /* Get skb and descriptor buffer */ |
| 435 | static int sh_eth_ring_init(struct net_device *ndev) |
| 436 | { |
| 437 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 438 | int rx_ringsize, tx_ringsize, ret = 0; |
| 439 | |
| 440 | /* |
| 441 | * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the |
| 442 | * card needs room to do 8 byte alignment, +2 so we can reserve |
| 443 | * the first 2 bytes, and +16 gets room for the status word from the |
| 444 | * card. |
| 445 | */ |
| 446 | mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : |
| 447 | (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); |
| 448 | |
| 449 | /* Allocate RX and TX skb rings */ |
| 450 | mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE, |
| 451 | GFP_KERNEL); |
| 452 | if (!mdp->rx_skbuff) { |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 453 | dev_err(&ndev->dev, "Cannot allocate Rx skb\n"); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 454 | ret = -ENOMEM; |
| 455 | return ret; |
| 456 | } |
| 457 | |
| 458 | mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE, |
| 459 | GFP_KERNEL); |
| 460 | if (!mdp->tx_skbuff) { |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 461 | dev_err(&ndev->dev, "Cannot allocate Tx skb\n"); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 462 | ret = -ENOMEM; |
| 463 | goto skb_ring_free; |
| 464 | } |
| 465 | |
| 466 | /* Allocate all Rx descriptors. */ |
| 467 | rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE; |
| 468 | mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, |
| 469 | GFP_KERNEL); |
| 470 | |
| 471 | if (!mdp->rx_ring) { |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 472 | dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n", |
| 473 | rx_ringsize); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 474 | ret = -ENOMEM; |
| 475 | goto desc_ring_free; |
| 476 | } |
| 477 | |
| 478 | mdp->dirty_rx = 0; |
| 479 | |
| 480 | /* Allocate all Tx descriptors. */ |
| 481 | tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE; |
| 482 | mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, |
| 483 | GFP_KERNEL); |
| 484 | if (!mdp->tx_ring) { |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 485 | dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n", |
| 486 | tx_ringsize); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 487 | ret = -ENOMEM; |
| 488 | goto desc_ring_free; |
| 489 | } |
| 490 | return ret; |
| 491 | |
| 492 | desc_ring_free: |
| 493 | /* free DMA buffer */ |
| 494 | dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma); |
| 495 | |
| 496 | skb_ring_free: |
| 497 | /* Free Rx and Tx skb ring buffer */ |
| 498 | sh_eth_ring_free(ndev); |
| 499 | |
| 500 | return ret; |
| 501 | } |
| 502 | |
| 503 | static int sh_eth_dev_init(struct net_device *ndev) |
| 504 | { |
| 505 | int ret = 0; |
| 506 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 507 | u32 ioaddr = ndev->base_addr; |
| 508 | u_int32_t rx_int_var, tx_int_var; |
| 509 | u32 val; |
| 510 | |
| 511 | /* Soft Reset */ |
| 512 | sh_eth_reset(ndev); |
| 513 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 514 | /* Descriptor format */ |
| 515 | sh_eth_ring_format(ndev); |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 516 | if (mdp->cd->rpadir) |
| 517 | ctrl_outl(mdp->cd->rpadir_value, ioaddr + RPADIR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 518 | |
| 519 | /* all sh_eth int mask */ |
| 520 | ctrl_outl(0, ioaddr + EESIPR); |
| 521 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 522 | #if defined(__LITTLE_ENDIAN__) |
| 523 | if (mdp->cd->hw_swap) |
| 524 | ctrl_outl(EDMR_EL, ioaddr + EDMR); |
| 525 | else |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 526 | #endif |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 527 | ctrl_outl(0, ioaddr + EDMR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 528 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 529 | /* FIFO size set */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 530 | ctrl_outl(mdp->cd->fdr_value, ioaddr + FDR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 531 | ctrl_outl(0, ioaddr + TFTR); |
| 532 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 533 | /* Frame recv control */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 534 | ctrl_outl(mdp->cd->rmcr_value, ioaddr + RMCR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 535 | |
| 536 | rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5; |
| 537 | tx_int_var = mdp->tx_int_var = DESC_I_TINT2; |
| 538 | ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER); |
| 539 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 540 | if (mdp->cd->bculr) |
| 541 | ctrl_outl(0x800, ioaddr + BCULR); /* Burst sycle set */ |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 542 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 543 | ctrl_outl(mdp->cd->fcftr_value, ioaddr + FCFTR); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 544 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 545 | if (!mdp->cd->no_trimd) |
| 546 | ctrl_outl(0, ioaddr + TRIMD); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 547 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 548 | /* Recv frame limit set register */ |
| 549 | ctrl_outl(RFLR_VALUE, ioaddr + RFLR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 550 | |
| 551 | ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR); |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 552 | ctrl_outl(mdp->cd->eesipr_value, ioaddr + EESIPR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 553 | |
| 554 | /* PAUSE Prohibition */ |
| 555 | val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) | |
| 556 | ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; |
| 557 | |
| 558 | ctrl_outl(val, ioaddr + ECMR); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 559 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 560 | if (mdp->cd->set_rate) |
| 561 | mdp->cd->set_rate(ndev); |
| 562 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 563 | /* E-MAC Status Register clear */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 564 | ctrl_outl(mdp->cd->ecsr_value, ioaddr + ECSR); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 565 | |
| 566 | /* E-MAC Interrupt Enable register */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 567 | ctrl_outl(mdp->cd->ecsipr_value, ioaddr + ECSIPR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 568 | |
| 569 | /* Set MAC address */ |
| 570 | update_mac_address(ndev); |
| 571 | |
| 572 | /* mask reset */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 573 | if (mdp->cd->apr) |
| 574 | ctrl_outl(APR_AP, ioaddr + APR); |
| 575 | if (mdp->cd->mpr) |
| 576 | ctrl_outl(MPR_MP, ioaddr + MPR); |
| 577 | if (mdp->cd->tpauser) |
| 578 | ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 579 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 580 | /* Setting the Rx mode will start the Rx process. */ |
| 581 | ctrl_outl(EDRRR_R, ioaddr + EDRRR); |
| 582 | |
| 583 | netif_start_queue(ndev); |
| 584 | |
| 585 | return ret; |
| 586 | } |
| 587 | |
| 588 | /* free Tx skb function */ |
| 589 | static int sh_eth_txfree(struct net_device *ndev) |
| 590 | { |
| 591 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 592 | struct sh_eth_txdesc *txdesc; |
| 593 | int freeNum = 0; |
| 594 | int entry = 0; |
| 595 | |
| 596 | for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { |
| 597 | entry = mdp->dirty_tx % TX_RING_SIZE; |
| 598 | txdesc = &mdp->tx_ring[entry]; |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 599 | if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 600 | break; |
| 601 | /* Free the original skb. */ |
| 602 | if (mdp->tx_skbuff[entry]) { |
| 603 | dev_kfree_skb_irq(mdp->tx_skbuff[entry]); |
| 604 | mdp->tx_skbuff[entry] = NULL; |
| 605 | freeNum++; |
| 606 | } |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 607 | txdesc->status = cpu_to_edmac(mdp, TD_TFP); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 608 | if (entry >= TX_RING_SIZE - 1) |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 609 | txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 610 | |
| 611 | mdp->stats.tx_packets++; |
| 612 | mdp->stats.tx_bytes += txdesc->buffer_length; |
| 613 | } |
| 614 | return freeNum; |
| 615 | } |
| 616 | |
| 617 | /* Packet receive function */ |
| 618 | static int sh_eth_rx(struct net_device *ndev) |
| 619 | { |
| 620 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 621 | struct sh_eth_rxdesc *rxdesc; |
| 622 | |
| 623 | int entry = mdp->cur_rx % RX_RING_SIZE; |
| 624 | int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx; |
| 625 | struct sk_buff *skb; |
| 626 | u16 pkt_len = 0; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 627 | u32 desc_status; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 628 | |
| 629 | rxdesc = &mdp->rx_ring[entry]; |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 630 | while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { |
| 631 | desc_status = edmac_to_cpu(mdp, rxdesc->status); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 632 | pkt_len = rxdesc->frame_length; |
| 633 | |
| 634 | if (--boguscnt < 0) |
| 635 | break; |
| 636 | |
| 637 | if (!(desc_status & RDFEND)) |
| 638 | mdp->stats.rx_length_errors++; |
| 639 | |
| 640 | if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | |
| 641 | RD_RFS5 | RD_RFS6 | RD_RFS10)) { |
| 642 | mdp->stats.rx_errors++; |
| 643 | if (desc_status & RD_RFS1) |
| 644 | mdp->stats.rx_crc_errors++; |
| 645 | if (desc_status & RD_RFS2) |
| 646 | mdp->stats.rx_frame_errors++; |
| 647 | if (desc_status & RD_RFS3) |
| 648 | mdp->stats.rx_length_errors++; |
| 649 | if (desc_status & RD_RFS4) |
| 650 | mdp->stats.rx_length_errors++; |
| 651 | if (desc_status & RD_RFS6) |
| 652 | mdp->stats.rx_missed_errors++; |
| 653 | if (desc_status & RD_RFS10) |
| 654 | mdp->stats.rx_over_errors++; |
| 655 | } else { |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 656 | if (!mdp->cd->hw_swap) |
| 657 | sh_eth_soft_swap( |
| 658 | phys_to_virt(ALIGN(rxdesc->addr, 4)), |
| 659 | pkt_len + 2); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 660 | skb = mdp->rx_skbuff[entry]; |
| 661 | mdp->rx_skbuff[entry] = NULL; |
| 662 | skb_put(skb, pkt_len); |
| 663 | skb->protocol = eth_type_trans(skb, ndev); |
| 664 | netif_rx(skb); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 665 | mdp->stats.rx_packets++; |
| 666 | mdp->stats.rx_bytes += pkt_len; |
| 667 | } |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 668 | rxdesc->status |= cpu_to_edmac(mdp, RD_RACT); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 669 | entry = (++mdp->cur_rx) % RX_RING_SIZE; |
Yoshihiro Shimoda | 862df49 | 2009-05-24 23:53:40 +0000 | [diff] [blame] | 670 | rxdesc = &mdp->rx_ring[entry]; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 671 | } |
| 672 | |
| 673 | /* Refill the Rx ring buffers. */ |
| 674 | for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { |
| 675 | entry = mdp->dirty_rx % RX_RING_SIZE; |
| 676 | rxdesc = &mdp->rx_ring[entry]; |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 677 | /* The size of the buffer is 16 byte boundary. */ |
Yoshihiro Shimoda | 0029d64 | 2009-05-24 23:53:20 +0000 | [diff] [blame] | 678 | rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 679 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 680 | if (mdp->rx_skbuff[entry] == NULL) { |
| 681 | skb = dev_alloc_skb(mdp->rx_buf_sz); |
| 682 | mdp->rx_skbuff[entry] = skb; |
| 683 | if (skb == NULL) |
| 684 | break; /* Better luck next round. */ |
Yoshihiro Shimoda | e88aae7 | 2009-05-24 23:52:35 +0000 | [diff] [blame] | 685 | dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz, |
| 686 | DMA_FROM_DEVICE); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 687 | skb->dev = ndev; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 688 | sh_eth_set_receive_align(skb); |
| 689 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 690 | skb->ip_summed = CHECKSUM_NONE; |
Yoshihiro Shimoda | 0029d64 | 2009-05-24 23:53:20 +0000 | [diff] [blame] | 691 | rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 692 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 693 | if (entry >= RX_RING_SIZE - 1) |
| 694 | rxdesc->status |= |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 695 | cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 696 | else |
| 697 | rxdesc->status |= |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 698 | cpu_to_edmac(mdp, RD_RACT | RD_RFP); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 699 | } |
| 700 | |
| 701 | /* Restart Rx engine if stopped. */ |
| 702 | /* If we don't need to check status, don't. -KDU */ |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 703 | if (!(ctrl_inl(ndev->base_addr + EDRRR) & EDRRR_R)) |
| 704 | ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 705 | |
| 706 | return 0; |
| 707 | } |
| 708 | |
| 709 | /* error control function */ |
| 710 | static void sh_eth_error(struct net_device *ndev, int intr_status) |
| 711 | { |
| 712 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 713 | u32 ioaddr = ndev->base_addr; |
| 714 | u32 felic_stat; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 715 | u32 link_stat; |
| 716 | u32 mask; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 717 | |
| 718 | if (intr_status & EESR_ECI) { |
| 719 | felic_stat = ctrl_inl(ioaddr + ECSR); |
| 720 | ctrl_outl(felic_stat, ioaddr + ECSR); /* clear int */ |
| 721 | if (felic_stat & ECSR_ICD) |
| 722 | mdp->stats.tx_carrier_errors++; |
| 723 | if (felic_stat & ECSR_LCHNG) { |
| 724 | /* Link Changed */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 725 | if (mdp->cd->no_psr) { |
| 726 | if (mdp->link == PHY_DOWN) |
| 727 | link_stat = 0; |
| 728 | else |
| 729 | link_stat = PHY_ST_LINK; |
| 730 | } else { |
| 731 | link_stat = (ctrl_inl(ioaddr + PSR)); |
| 732 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 733 | if (!(link_stat & PHY_ST_LINK)) { |
| 734 | /* Link Down : disable tx and rx */ |
| 735 | ctrl_outl(ctrl_inl(ioaddr + ECMR) & |
| 736 | ~(ECMR_RE | ECMR_TE), ioaddr + ECMR); |
| 737 | } else { |
| 738 | /* Link Up */ |
| 739 | ctrl_outl(ctrl_inl(ioaddr + EESIPR) & |
| 740 | ~DMAC_M_ECI, ioaddr + EESIPR); |
| 741 | /*clear int */ |
| 742 | ctrl_outl(ctrl_inl(ioaddr + ECSR), |
| 743 | ioaddr + ECSR); |
| 744 | ctrl_outl(ctrl_inl(ioaddr + EESIPR) | |
| 745 | DMAC_M_ECI, ioaddr + EESIPR); |
| 746 | /* enable tx and rx */ |
| 747 | ctrl_outl(ctrl_inl(ioaddr + ECMR) | |
| 748 | (ECMR_RE | ECMR_TE), ioaddr + ECMR); |
| 749 | } |
| 750 | } |
| 751 | } |
| 752 | |
| 753 | if (intr_status & EESR_TWB) { |
| 754 | /* Write buck end. unused write back interrupt */ |
| 755 | if (intr_status & EESR_TABT) /* Transmit Abort int */ |
| 756 | mdp->stats.tx_aborted_errors++; |
| 757 | } |
| 758 | |
| 759 | if (intr_status & EESR_RABT) { |
| 760 | /* Receive Abort int */ |
| 761 | if (intr_status & EESR_RFRMER) { |
| 762 | /* Receive Frame Overflow int */ |
| 763 | mdp->stats.rx_frame_errors++; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 764 | dev_err(&ndev->dev, "Receive Frame Overflow\n"); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 765 | } |
| 766 | } |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 767 | |
| 768 | if (!mdp->cd->no_ade) { |
| 769 | if (intr_status & EESR_ADE && intr_status & EESR_TDE && |
| 770 | intr_status & EESR_TFE) |
| 771 | mdp->stats.tx_fifo_errors++; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | if (intr_status & EESR_RDE) { |
| 775 | /* Receive Descriptor Empty int */ |
| 776 | mdp->stats.rx_over_errors++; |
| 777 | |
| 778 | if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R) |
| 779 | ctrl_outl(EDRRR_R, ioaddr + EDRRR); |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 780 | dev_err(&ndev->dev, "Receive Descriptor Empty\n"); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 781 | } |
| 782 | if (intr_status & EESR_RFE) { |
| 783 | /* Receive FIFO Overflow int */ |
| 784 | mdp->stats.rx_fifo_errors++; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 785 | dev_err(&ndev->dev, "Receive FIFO Overflow\n"); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 786 | } |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 787 | |
| 788 | mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; |
| 789 | if (mdp->cd->no_ade) |
| 790 | mask &= ~EESR_ADE; |
| 791 | if (intr_status & mask) { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 792 | /* Tx error */ |
| 793 | u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR); |
| 794 | /* dmesg */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 795 | dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ", |
| 796 | intr_status, mdp->cur_tx); |
| 797 | dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 798 | mdp->dirty_tx, (u32) ndev->state, edtrr); |
| 799 | /* dirty buffer free */ |
| 800 | sh_eth_txfree(ndev); |
| 801 | |
| 802 | /* SH7712 BUG */ |
| 803 | if (edtrr ^ EDTRR_TRNS) { |
| 804 | /* tx dma start */ |
| 805 | ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR); |
| 806 | } |
| 807 | /* wakeup */ |
| 808 | netif_wake_queue(ndev); |
| 809 | } |
| 810 | } |
| 811 | |
| 812 | static irqreturn_t sh_eth_interrupt(int irq, void *netdev) |
| 813 | { |
| 814 | struct net_device *ndev = netdev; |
| 815 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 816 | struct sh_eth_cpu_data *cd = mdp->cd; |
Nobuhiro Iwamatsu | 0e0fde3 | 2009-03-16 19:50:57 +0000 | [diff] [blame] | 817 | irqreturn_t ret = IRQ_NONE; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 818 | u32 ioaddr, boguscnt = RX_RING_SIZE; |
| 819 | u32 intr_status = 0; |
| 820 | |
| 821 | ioaddr = ndev->base_addr; |
| 822 | spin_lock(&mdp->lock); |
| 823 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 824 | /* Get interrpt stat */ |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 825 | intr_status = ctrl_inl(ioaddr + EESR); |
| 826 | /* Clear interrupt */ |
Nobuhiro Iwamatsu | 0e0fde3 | 2009-03-16 19:50:57 +0000 | [diff] [blame] | 827 | if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF | |
| 828 | EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 829 | cd->tx_check | cd->eesr_err_check)) { |
Nobuhiro Iwamatsu | 0e0fde3 | 2009-03-16 19:50:57 +0000 | [diff] [blame] | 830 | ctrl_outl(intr_status, ioaddr + EESR); |
| 831 | ret = IRQ_HANDLED; |
| 832 | } else |
| 833 | goto other_irq; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 834 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 835 | if (intr_status & (EESR_FRC | /* Frame recv*/ |
| 836 | EESR_RMAF | /* Multi cast address recv*/ |
| 837 | EESR_RRF | /* Bit frame recv */ |
| 838 | EESR_RTLF | /* Long frame recv*/ |
| 839 | EESR_RTSF | /* short frame recv */ |
| 840 | EESR_PRE | /* PHY-LSI recv error */ |
| 841 | EESR_CERF)){ /* recv frame CRC error */ |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 842 | sh_eth_rx(ndev); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 843 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 844 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 845 | /* Tx Check */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 846 | if (intr_status & cd->tx_check) { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 847 | sh_eth_txfree(ndev); |
| 848 | netif_wake_queue(ndev); |
| 849 | } |
| 850 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 851 | if (intr_status & cd->eesr_err_check) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 852 | sh_eth_error(ndev, intr_status); |
| 853 | |
| 854 | if (--boguscnt < 0) { |
| 855 | printk(KERN_WARNING |
| 856 | "%s: Too much work at interrupt, status=0x%4.4x.\n", |
| 857 | ndev->name, intr_status); |
| 858 | } |
| 859 | |
Nobuhiro Iwamatsu | 0e0fde3 | 2009-03-16 19:50:57 +0000 | [diff] [blame] | 860 | other_irq: |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 861 | spin_unlock(&mdp->lock); |
| 862 | |
Nobuhiro Iwamatsu | 0e0fde3 | 2009-03-16 19:50:57 +0000 | [diff] [blame] | 863 | return ret; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 864 | } |
| 865 | |
| 866 | static void sh_eth_timer(unsigned long data) |
| 867 | { |
| 868 | struct net_device *ndev = (struct net_device *)data; |
| 869 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 870 | |
| 871 | mod_timer(&mdp->timer, jiffies + (10 * HZ)); |
| 872 | } |
| 873 | |
| 874 | /* PHY state control function */ |
| 875 | static void sh_eth_adjust_link(struct net_device *ndev) |
| 876 | { |
| 877 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 878 | struct phy_device *phydev = mdp->phydev; |
| 879 | u32 ioaddr = ndev->base_addr; |
| 880 | int new_state = 0; |
| 881 | |
| 882 | if (phydev->link != PHY_DOWN) { |
| 883 | if (phydev->duplex != mdp->duplex) { |
| 884 | new_state = 1; |
| 885 | mdp->duplex = phydev->duplex; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 886 | if (mdp->cd->set_duplex) |
| 887 | mdp->cd->set_duplex(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 888 | } |
| 889 | |
| 890 | if (phydev->speed != mdp->speed) { |
| 891 | new_state = 1; |
| 892 | mdp->speed = phydev->speed; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 893 | if (mdp->cd->set_rate) |
| 894 | mdp->cd->set_rate(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 895 | } |
| 896 | if (mdp->link == PHY_DOWN) { |
| 897 | ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF) |
| 898 | | ECMR_DM, ioaddr + ECMR); |
| 899 | new_state = 1; |
| 900 | mdp->link = phydev->link; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 901 | } |
| 902 | } else if (mdp->link) { |
| 903 | new_state = 1; |
| 904 | mdp->link = PHY_DOWN; |
| 905 | mdp->speed = 0; |
| 906 | mdp->duplex = -1; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 907 | } |
| 908 | |
| 909 | if (new_state) |
| 910 | phy_print_status(phydev); |
| 911 | } |
| 912 | |
| 913 | /* PHY init function */ |
| 914 | static int sh_eth_phy_init(struct net_device *ndev) |
| 915 | { |
| 916 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 917 | char phy_id[BUS_ID_SIZE]; |
| 918 | struct phy_device *phydev = NULL; |
| 919 | |
Kay Sievers | fb28ad3 | 2008-11-10 13:55:14 -0800 | [diff] [blame] | 920 | snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 921 | mdp->mii_bus->id , mdp->phy_id); |
| 922 | |
| 923 | mdp->link = PHY_DOWN; |
| 924 | mdp->speed = 0; |
| 925 | mdp->duplex = -1; |
| 926 | |
| 927 | /* Try connect to PHY */ |
| 928 | phydev = phy_connect(ndev, phy_id, &sh_eth_adjust_link, |
| 929 | 0, PHY_INTERFACE_MODE_MII); |
| 930 | if (IS_ERR(phydev)) { |
| 931 | dev_err(&ndev->dev, "phy_connect failed\n"); |
| 932 | return PTR_ERR(phydev); |
| 933 | } |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 934 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 935 | dev_info(&ndev->dev, "attached phy %i to driver %s\n", |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 936 | phydev->addr, phydev->drv->name); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 937 | |
| 938 | mdp->phydev = phydev; |
| 939 | |
| 940 | return 0; |
| 941 | } |
| 942 | |
| 943 | /* PHY control start function */ |
| 944 | static int sh_eth_phy_start(struct net_device *ndev) |
| 945 | { |
| 946 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 947 | int ret; |
| 948 | |
| 949 | ret = sh_eth_phy_init(ndev); |
| 950 | if (ret) |
| 951 | return ret; |
| 952 | |
| 953 | /* reset phy - this also wakes it from PDOWN */ |
| 954 | phy_write(mdp->phydev, MII_BMCR, BMCR_RESET); |
| 955 | phy_start(mdp->phydev); |
| 956 | |
| 957 | return 0; |
| 958 | } |
| 959 | |
| 960 | /* network device open function */ |
| 961 | static int sh_eth_open(struct net_device *ndev) |
| 962 | { |
| 963 | int ret = 0; |
| 964 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 965 | |
Nobuhiro Iwamatsu | 0e0fde3 | 2009-03-16 19:50:57 +0000 | [diff] [blame] | 966 | ret = request_irq(ndev->irq, &sh_eth_interrupt, |
| 967 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) || defined(CONFIG_CPU_SUBTYPE_SH7764) |
| 968 | IRQF_SHARED, |
| 969 | #else |
| 970 | 0, |
| 971 | #endif |
| 972 | ndev->name, ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 973 | if (ret) { |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 974 | dev_err(&ndev->dev, "Can not assign IRQ number\n"); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 975 | return ret; |
| 976 | } |
| 977 | |
| 978 | /* Descriptor set */ |
| 979 | ret = sh_eth_ring_init(ndev); |
| 980 | if (ret) |
| 981 | goto out_free_irq; |
| 982 | |
| 983 | /* device init */ |
| 984 | ret = sh_eth_dev_init(ndev); |
| 985 | if (ret) |
| 986 | goto out_free_irq; |
| 987 | |
| 988 | /* PHY control start*/ |
| 989 | ret = sh_eth_phy_start(ndev); |
| 990 | if (ret) |
| 991 | goto out_free_irq; |
| 992 | |
| 993 | /* Set the timer to check for link beat. */ |
| 994 | init_timer(&mdp->timer); |
| 995 | mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */ |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 996 | setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 997 | |
| 998 | return ret; |
| 999 | |
| 1000 | out_free_irq: |
| 1001 | free_irq(ndev->irq, ndev); |
| 1002 | return ret; |
| 1003 | } |
| 1004 | |
| 1005 | /* Timeout function */ |
| 1006 | static void sh_eth_tx_timeout(struct net_device *ndev) |
| 1007 | { |
| 1008 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 1009 | u32 ioaddr = ndev->base_addr; |
| 1010 | struct sh_eth_rxdesc *rxdesc; |
| 1011 | int i; |
| 1012 | |
| 1013 | netif_stop_queue(ndev); |
| 1014 | |
| 1015 | /* worning message out. */ |
| 1016 | printk(KERN_WARNING "%s: transmit timed out, status %8.8x," |
| 1017 | " resetting...\n", ndev->name, (int)ctrl_inl(ioaddr + EESR)); |
| 1018 | |
| 1019 | /* tx_errors count up */ |
| 1020 | mdp->stats.tx_errors++; |
| 1021 | |
| 1022 | /* timer off */ |
| 1023 | del_timer_sync(&mdp->timer); |
| 1024 | |
| 1025 | /* Free all the skbuffs in the Rx queue. */ |
| 1026 | for (i = 0; i < RX_RING_SIZE; i++) { |
| 1027 | rxdesc = &mdp->rx_ring[i]; |
| 1028 | rxdesc->status = 0; |
| 1029 | rxdesc->addr = 0xBADF00D0; |
| 1030 | if (mdp->rx_skbuff[i]) |
| 1031 | dev_kfree_skb(mdp->rx_skbuff[i]); |
| 1032 | mdp->rx_skbuff[i] = NULL; |
| 1033 | } |
| 1034 | for (i = 0; i < TX_RING_SIZE; i++) { |
| 1035 | if (mdp->tx_skbuff[i]) |
| 1036 | dev_kfree_skb(mdp->tx_skbuff[i]); |
| 1037 | mdp->tx_skbuff[i] = NULL; |
| 1038 | } |
| 1039 | |
| 1040 | /* device init */ |
| 1041 | sh_eth_dev_init(ndev); |
| 1042 | |
| 1043 | /* timer on */ |
| 1044 | mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */ |
| 1045 | add_timer(&mdp->timer); |
| 1046 | } |
| 1047 | |
| 1048 | /* Packet transmit function */ |
| 1049 | static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
| 1050 | { |
| 1051 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 1052 | struct sh_eth_txdesc *txdesc; |
| 1053 | u32 entry; |
Nobuhiro Iwamatsu | fb5e2f9 | 2008-11-17 20:29:58 +0000 | [diff] [blame] | 1054 | unsigned long flags; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1055 | |
| 1056 | spin_lock_irqsave(&mdp->lock, flags); |
| 1057 | if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) { |
| 1058 | if (!sh_eth_txfree(ndev)) { |
| 1059 | netif_stop_queue(ndev); |
| 1060 | spin_unlock_irqrestore(&mdp->lock, flags); |
| 1061 | return 1; |
| 1062 | } |
| 1063 | } |
| 1064 | spin_unlock_irqrestore(&mdp->lock, flags); |
| 1065 | |
| 1066 | entry = mdp->cur_tx % TX_RING_SIZE; |
| 1067 | mdp->tx_skbuff[entry] = skb; |
| 1068 | txdesc = &mdp->tx_ring[entry]; |
Yoshihiro Shimoda | 0029d64 | 2009-05-24 23:53:20 +0000 | [diff] [blame] | 1069 | txdesc->addr = virt_to_phys(skb->data); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1070 | /* soft swap. */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 1071 | if (!mdp->cd->hw_swap) |
| 1072 | sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)), |
| 1073 | skb->len + 2); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1074 | /* write back */ |
| 1075 | __flush_purge_region(skb->data, skb->len); |
| 1076 | if (skb->len < ETHERSMALL) |
| 1077 | txdesc->buffer_length = ETHERSMALL; |
| 1078 | else |
| 1079 | txdesc->buffer_length = skb->len; |
| 1080 | |
| 1081 | if (entry >= TX_RING_SIZE - 1) |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 1082 | txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1083 | else |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 1084 | txdesc->status |= cpu_to_edmac(mdp, TD_TACT); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1085 | |
| 1086 | mdp->cur_tx++; |
| 1087 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1088 | if (!(ctrl_inl(ndev->base_addr + EDTRR) & EDTRR_TRNS)) |
| 1089 | ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR); |
| 1090 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1091 | ndev->trans_start = jiffies; |
| 1092 | |
| 1093 | return 0; |
| 1094 | } |
| 1095 | |
| 1096 | /* device close function */ |
| 1097 | static int sh_eth_close(struct net_device *ndev) |
| 1098 | { |
| 1099 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 1100 | u32 ioaddr = ndev->base_addr; |
| 1101 | int ringsize; |
| 1102 | |
| 1103 | netif_stop_queue(ndev); |
| 1104 | |
| 1105 | /* Disable interrupts by clearing the interrupt mask. */ |
| 1106 | ctrl_outl(0x0000, ioaddr + EESIPR); |
| 1107 | |
| 1108 | /* Stop the chip's Tx and Rx processes. */ |
| 1109 | ctrl_outl(0, ioaddr + EDTRR); |
| 1110 | ctrl_outl(0, ioaddr + EDRRR); |
| 1111 | |
| 1112 | /* PHY Disconnect */ |
| 1113 | if (mdp->phydev) { |
| 1114 | phy_stop(mdp->phydev); |
| 1115 | phy_disconnect(mdp->phydev); |
| 1116 | } |
| 1117 | |
| 1118 | free_irq(ndev->irq, ndev); |
| 1119 | |
| 1120 | del_timer_sync(&mdp->timer); |
| 1121 | |
| 1122 | /* Free all the skbuffs in the Rx queue. */ |
| 1123 | sh_eth_ring_free(ndev); |
| 1124 | |
| 1125 | /* free DMA buffer */ |
| 1126 | ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE; |
| 1127 | dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma); |
| 1128 | |
| 1129 | /* free DMA buffer */ |
| 1130 | ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE; |
| 1131 | dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma); |
| 1132 | |
| 1133 | return 0; |
| 1134 | } |
| 1135 | |
| 1136 | static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) |
| 1137 | { |
| 1138 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 1139 | u32 ioaddr = ndev->base_addr; |
| 1140 | |
| 1141 | mdp->stats.tx_dropped += ctrl_inl(ioaddr + TROCR); |
| 1142 | ctrl_outl(0, ioaddr + TROCR); /* (write clear) */ |
| 1143 | mdp->stats.collisions += ctrl_inl(ioaddr + CDCR); |
| 1144 | ctrl_outl(0, ioaddr + CDCR); /* (write clear) */ |
| 1145 | mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR); |
| 1146 | ctrl_outl(0, ioaddr + LCCR); /* (write clear) */ |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1147 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 1148 | mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CERCR);/* CERCR */ |
| 1149 | ctrl_outl(0, ioaddr + CERCR); /* (write clear) */ |
| 1150 | mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CEECR);/* CEECR */ |
| 1151 | ctrl_outl(0, ioaddr + CEECR); /* (write clear) */ |
| 1152 | #else |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1153 | mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR); |
| 1154 | ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */ |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1155 | #endif |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1156 | return &mdp->stats; |
| 1157 | } |
| 1158 | |
| 1159 | /* ioctl to device funciotn*/ |
| 1160 | static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, |
| 1161 | int cmd) |
| 1162 | { |
| 1163 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 1164 | struct phy_device *phydev = mdp->phydev; |
| 1165 | |
| 1166 | if (!netif_running(ndev)) |
| 1167 | return -EINVAL; |
| 1168 | |
| 1169 | if (!phydev) |
| 1170 | return -ENODEV; |
| 1171 | |
| 1172 | return phy_mii_ioctl(phydev, if_mii(rq), cmd); |
| 1173 | } |
| 1174 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 1175 | #if defined(SH_ETH_HAS_TSU) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1176 | /* Multicast reception directions set */ |
| 1177 | static void sh_eth_set_multicast_list(struct net_device *ndev) |
| 1178 | { |
| 1179 | u32 ioaddr = ndev->base_addr; |
| 1180 | |
| 1181 | if (ndev->flags & IFF_PROMISC) { |
| 1182 | /* Set promiscuous. */ |
| 1183 | ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM, |
| 1184 | ioaddr + ECMR); |
| 1185 | } else { |
| 1186 | /* Normal, unicast/broadcast-only mode. */ |
| 1187 | ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT, |
| 1188 | ioaddr + ECMR); |
| 1189 | } |
| 1190 | } |
| 1191 | |
| 1192 | /* SuperH's TSU register init function */ |
| 1193 | static void sh_eth_tsu_init(u32 ioaddr) |
| 1194 | { |
| 1195 | ctrl_outl(0, ioaddr + TSU_FWEN0); /* Disable forward(0->1) */ |
| 1196 | ctrl_outl(0, ioaddr + TSU_FWEN1); /* Disable forward(1->0) */ |
| 1197 | ctrl_outl(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */ |
| 1198 | ctrl_outl(0xc, ioaddr + TSU_BSYSL0); |
| 1199 | ctrl_outl(0xc, ioaddr + TSU_BSYSL1); |
| 1200 | ctrl_outl(0, ioaddr + TSU_PRISL0); |
| 1201 | ctrl_outl(0, ioaddr + TSU_PRISL1); |
| 1202 | ctrl_outl(0, ioaddr + TSU_FWSL0); |
| 1203 | ctrl_outl(0, ioaddr + TSU_FWSL1); |
| 1204 | ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1205 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 1206 | ctrl_outl(0, ioaddr + TSU_QTAG0); /* Disable QTAG(0->1) */ |
| 1207 | ctrl_outl(0, ioaddr + TSU_QTAG1); /* Disable QTAG(1->0) */ |
| 1208 | #else |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1209 | ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */ |
| 1210 | ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */ |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1211 | #endif |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1212 | ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */ |
| 1213 | ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */ |
| 1214 | ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */ |
| 1215 | ctrl_outl(0, ioaddr + TSU_POST1); /* Disable CAM entry [ 0- 7] */ |
| 1216 | ctrl_outl(0, ioaddr + TSU_POST2); /* Disable CAM entry [ 8-15] */ |
| 1217 | ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */ |
| 1218 | ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */ |
| 1219 | } |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 1220 | #endif /* SH_ETH_HAS_TSU */ |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1221 | |
| 1222 | /* MDIO bus release function */ |
| 1223 | static int sh_mdio_release(struct net_device *ndev) |
| 1224 | { |
| 1225 | struct mii_bus *bus = dev_get_drvdata(&ndev->dev); |
| 1226 | |
| 1227 | /* unregister mdio bus */ |
| 1228 | mdiobus_unregister(bus); |
| 1229 | |
| 1230 | /* remove mdio bus info from net_device */ |
| 1231 | dev_set_drvdata(&ndev->dev, NULL); |
| 1232 | |
| 1233 | /* free bitbang info */ |
| 1234 | free_mdio_bitbang(bus); |
| 1235 | |
| 1236 | return 0; |
| 1237 | } |
| 1238 | |
| 1239 | /* MDIO bus init function */ |
| 1240 | static int sh_mdio_init(struct net_device *ndev, int id) |
| 1241 | { |
| 1242 | int ret, i; |
| 1243 | struct bb_info *bitbang; |
| 1244 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 1245 | |
| 1246 | /* create bit control struct for PHY */ |
| 1247 | bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL); |
| 1248 | if (!bitbang) { |
| 1249 | ret = -ENOMEM; |
| 1250 | goto out; |
| 1251 | } |
| 1252 | |
| 1253 | /* bitbang init */ |
| 1254 | bitbang->addr = ndev->base_addr + PIR; |
| 1255 | bitbang->mdi_msk = 0x08; |
| 1256 | bitbang->mdo_msk = 0x04; |
| 1257 | bitbang->mmd_msk = 0x02;/* MMD */ |
| 1258 | bitbang->mdc_msk = 0x01; |
| 1259 | bitbang->ctrl.ops = &bb_ops; |
| 1260 | |
| 1261 | /* MII contorller setting */ |
| 1262 | mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); |
| 1263 | if (!mdp->mii_bus) { |
| 1264 | ret = -ENOMEM; |
| 1265 | goto out_free_bitbang; |
| 1266 | } |
| 1267 | |
| 1268 | /* Hook up MII support for ethtool */ |
| 1269 | mdp->mii_bus->name = "sh_mii"; |
Lennert Buytenhek | 18ee49d | 2008-10-01 15:41:33 +0000 | [diff] [blame] | 1270 | mdp->mii_bus->parent = &ndev->dev; |
Nobuhiro Iwamatsu | fb5e2f9 | 2008-11-17 20:29:58 +0000 | [diff] [blame] | 1271 | snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1272 | |
| 1273 | /* PHY IRQ */ |
| 1274 | mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
| 1275 | if (!mdp->mii_bus->irq) { |
| 1276 | ret = -ENOMEM; |
| 1277 | goto out_free_bus; |
| 1278 | } |
| 1279 | |
| 1280 | for (i = 0; i < PHY_MAX_ADDR; i++) |
| 1281 | mdp->mii_bus->irq[i] = PHY_POLL; |
| 1282 | |
| 1283 | /* regist mdio bus */ |
| 1284 | ret = mdiobus_register(mdp->mii_bus); |
| 1285 | if (ret) |
| 1286 | goto out_free_irq; |
| 1287 | |
| 1288 | dev_set_drvdata(&ndev->dev, mdp->mii_bus); |
| 1289 | |
| 1290 | return 0; |
| 1291 | |
| 1292 | out_free_irq: |
| 1293 | kfree(mdp->mii_bus->irq); |
| 1294 | |
| 1295 | out_free_bus: |
Lennert Buytenhek | 298cf9b | 2008-10-08 16:29:57 -0700 | [diff] [blame] | 1296 | free_mdio_bitbang(mdp->mii_bus); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1297 | |
| 1298 | out_free_bitbang: |
| 1299 | kfree(bitbang); |
| 1300 | |
| 1301 | out: |
| 1302 | return ret; |
| 1303 | } |
| 1304 | |
Alexander Beregalov | ebf84ea | 2009-04-11 07:40:49 +0000 | [diff] [blame] | 1305 | static const struct net_device_ops sh_eth_netdev_ops = { |
| 1306 | .ndo_open = sh_eth_open, |
| 1307 | .ndo_stop = sh_eth_close, |
| 1308 | .ndo_start_xmit = sh_eth_start_xmit, |
| 1309 | .ndo_get_stats = sh_eth_get_stats, |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 1310 | #if defined(SH_ETH_HAS_TSU) |
Alexander Beregalov | ebf84ea | 2009-04-11 07:40:49 +0000 | [diff] [blame] | 1311 | .ndo_set_multicast_list = sh_eth_set_multicast_list, |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 1312 | #endif |
Alexander Beregalov | ebf84ea | 2009-04-11 07:40:49 +0000 | [diff] [blame] | 1313 | .ndo_tx_timeout = sh_eth_tx_timeout, |
| 1314 | .ndo_do_ioctl = sh_eth_do_ioctl, |
| 1315 | .ndo_validate_addr = eth_validate_addr, |
| 1316 | .ndo_set_mac_address = eth_mac_addr, |
| 1317 | .ndo_change_mtu = eth_change_mtu, |
| 1318 | }; |
| 1319 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1320 | static int sh_eth_drv_probe(struct platform_device *pdev) |
| 1321 | { |
| 1322 | int ret, i, devno = 0; |
| 1323 | struct resource *res; |
| 1324 | struct net_device *ndev = NULL; |
| 1325 | struct sh_eth_private *mdp; |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 1326 | struct sh_eth_plat_data *pd; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1327 | |
| 1328 | /* get base addr */ |
| 1329 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1330 | if (unlikely(res == NULL)) { |
| 1331 | dev_err(&pdev->dev, "invalid resource\n"); |
| 1332 | ret = -EINVAL; |
| 1333 | goto out; |
| 1334 | } |
| 1335 | |
| 1336 | ndev = alloc_etherdev(sizeof(struct sh_eth_private)); |
| 1337 | if (!ndev) { |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 1338 | dev_err(&pdev->dev, "Could not allocate device.\n"); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1339 | ret = -ENOMEM; |
| 1340 | goto out; |
| 1341 | } |
| 1342 | |
| 1343 | /* The sh Ether-specific entries in the device structure. */ |
| 1344 | ndev->base_addr = res->start; |
| 1345 | devno = pdev->id; |
| 1346 | if (devno < 0) |
| 1347 | devno = 0; |
| 1348 | |
| 1349 | ndev->dma = -1; |
roel kluin | cc3c080 | 2008-09-10 19:22:44 +0200 | [diff] [blame] | 1350 | ret = platform_get_irq(pdev, 0); |
| 1351 | if (ret < 0) { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1352 | ret = -ENODEV; |
| 1353 | goto out_release; |
| 1354 | } |
roel kluin | cc3c080 | 2008-09-10 19:22:44 +0200 | [diff] [blame] | 1355 | ndev->irq = ret; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1356 | |
| 1357 | SET_NETDEV_DEV(ndev, &pdev->dev); |
| 1358 | |
| 1359 | /* Fill in the fields of the device structure with ethernet values. */ |
| 1360 | ether_setup(ndev); |
| 1361 | |
| 1362 | mdp = netdev_priv(ndev); |
| 1363 | spin_lock_init(&mdp->lock); |
| 1364 | |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 1365 | pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1366 | /* get PHY ID */ |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 1367 | mdp->phy_id = pd->phy; |
| 1368 | /* EDMAC endian */ |
| 1369 | mdp->edmac_endian = pd->edmac_endian; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1370 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 1371 | /* set cpu data */ |
| 1372 | mdp->cd = &sh_eth_my_cpu_data; |
| 1373 | sh_eth_set_default_cpu_data(mdp->cd); |
| 1374 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1375 | /* set function */ |
Alexander Beregalov | ebf84ea | 2009-04-11 07:40:49 +0000 | [diff] [blame] | 1376 | ndev->netdev_ops = &sh_eth_netdev_ops; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1377 | ndev->watchdog_timeo = TX_TIMEOUT; |
| 1378 | |
| 1379 | mdp->post_rx = POST_RX >> (devno << 1); |
| 1380 | mdp->post_fw = POST_FW >> (devno << 1); |
| 1381 | |
| 1382 | /* read and set MAC address */ |
| 1383 | read_mac_address(ndev); |
| 1384 | |
| 1385 | /* First device only init */ |
| 1386 | if (!devno) { |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 1387 | if (mdp->cd->chip_reset) |
| 1388 | mdp->cd->chip_reset(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1389 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 1390 | #if defined(SH_ETH_HAS_TSU) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1391 | /* TSU init (Init only)*/ |
| 1392 | sh_eth_tsu_init(SH_TSU_ADDR); |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 1393 | #endif |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1394 | } |
| 1395 | |
| 1396 | /* network device register */ |
| 1397 | ret = register_netdev(ndev); |
| 1398 | if (ret) |
| 1399 | goto out_release; |
| 1400 | |
| 1401 | /* mdio bus init */ |
| 1402 | ret = sh_mdio_init(ndev, pdev->id); |
| 1403 | if (ret) |
| 1404 | goto out_unregister; |
| 1405 | |
| 1406 | /* pritnt device infomation */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame^] | 1407 | pr_info("Base address at 0x%x, ", |
| 1408 | (u32)ndev->base_addr); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1409 | |
| 1410 | for (i = 0; i < 5; i++) |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 1411 | printk("%02X:", ndev->dev_addr[i]); |
| 1412 | printk("%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1413 | |
| 1414 | platform_set_drvdata(pdev, ndev); |
| 1415 | |
| 1416 | return ret; |
| 1417 | |
| 1418 | out_unregister: |
| 1419 | unregister_netdev(ndev); |
| 1420 | |
| 1421 | out_release: |
| 1422 | /* net_dev free */ |
| 1423 | if (ndev) |
| 1424 | free_netdev(ndev); |
| 1425 | |
| 1426 | out: |
| 1427 | return ret; |
| 1428 | } |
| 1429 | |
| 1430 | static int sh_eth_drv_remove(struct platform_device *pdev) |
| 1431 | { |
| 1432 | struct net_device *ndev = platform_get_drvdata(pdev); |
| 1433 | |
| 1434 | sh_mdio_release(ndev); |
| 1435 | unregister_netdev(ndev); |
| 1436 | flush_scheduled_work(); |
| 1437 | |
| 1438 | free_netdev(ndev); |
| 1439 | platform_set_drvdata(pdev, NULL); |
| 1440 | |
| 1441 | return 0; |
| 1442 | } |
| 1443 | |
| 1444 | static struct platform_driver sh_eth_driver = { |
| 1445 | .probe = sh_eth_drv_probe, |
| 1446 | .remove = sh_eth_drv_remove, |
| 1447 | .driver = { |
| 1448 | .name = CARDNAME, |
| 1449 | }, |
| 1450 | }; |
| 1451 | |
| 1452 | static int __init sh_eth_init(void) |
| 1453 | { |
| 1454 | return platform_driver_register(&sh_eth_driver); |
| 1455 | } |
| 1456 | |
| 1457 | static void __exit sh_eth_cleanup(void) |
| 1458 | { |
| 1459 | platform_driver_unregister(&sh_eth_driver); |
| 1460 | } |
| 1461 | |
| 1462 | module_init(sh_eth_init); |
| 1463 | module_exit(sh_eth_cleanup); |
| 1464 | |
| 1465 | MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); |
| 1466 | MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); |
| 1467 | MODULE_LICENSE("GPL v2"); |