Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 ARM Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | #ifndef __ASM_ELF_H |
| 17 | #define __ASM_ELF_H |
| 18 | |
| 19 | #include <asm/hwcap.h> |
| 20 | |
| 21 | /* |
| 22 | * ELF register definitions.. |
| 23 | */ |
| 24 | #include <asm/ptrace.h> |
| 25 | #include <asm/user.h> |
| 26 | |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 27 | /* |
| 28 | * AArch64 static relocation types. |
| 29 | */ |
| 30 | |
| 31 | /* Miscellaneous. */ |
| 32 | #define R_ARM_NONE 0 |
| 33 | #define R_AARCH64_NONE 256 |
| 34 | |
| 35 | /* Data. */ |
| 36 | #define R_AARCH64_ABS64 257 |
| 37 | #define R_AARCH64_ABS32 258 |
| 38 | #define R_AARCH64_ABS16 259 |
| 39 | #define R_AARCH64_PREL64 260 |
| 40 | #define R_AARCH64_PREL32 261 |
| 41 | #define R_AARCH64_PREL16 262 |
| 42 | |
| 43 | /* Instructions. */ |
| 44 | #define R_AARCH64_MOVW_UABS_G0 263 |
| 45 | #define R_AARCH64_MOVW_UABS_G0_NC 264 |
| 46 | #define R_AARCH64_MOVW_UABS_G1 265 |
| 47 | #define R_AARCH64_MOVW_UABS_G1_NC 266 |
| 48 | #define R_AARCH64_MOVW_UABS_G2 267 |
| 49 | #define R_AARCH64_MOVW_UABS_G2_NC 268 |
| 50 | #define R_AARCH64_MOVW_UABS_G3 269 |
| 51 | |
| 52 | #define R_AARCH64_MOVW_SABS_G0 270 |
| 53 | #define R_AARCH64_MOVW_SABS_G1 271 |
| 54 | #define R_AARCH64_MOVW_SABS_G2 272 |
| 55 | |
| 56 | #define R_AARCH64_LD_PREL_LO19 273 |
| 57 | #define R_AARCH64_ADR_PREL_LO21 274 |
| 58 | #define R_AARCH64_ADR_PREL_PG_HI21 275 |
| 59 | #define R_AARCH64_ADR_PREL_PG_HI21_NC 276 |
| 60 | #define R_AARCH64_ADD_ABS_LO12_NC 277 |
| 61 | #define R_AARCH64_LDST8_ABS_LO12_NC 278 |
| 62 | |
| 63 | #define R_AARCH64_TSTBR14 279 |
| 64 | #define R_AARCH64_CONDBR19 280 |
| 65 | #define R_AARCH64_JUMP26 282 |
| 66 | #define R_AARCH64_CALL26 283 |
| 67 | #define R_AARCH64_LDST16_ABS_LO12_NC 284 |
| 68 | #define R_AARCH64_LDST32_ABS_LO12_NC 285 |
| 69 | #define R_AARCH64_LDST64_ABS_LO12_NC 286 |
| 70 | #define R_AARCH64_LDST128_ABS_LO12_NC 299 |
| 71 | |
| 72 | #define R_AARCH64_MOVW_PREL_G0 287 |
| 73 | #define R_AARCH64_MOVW_PREL_G0_NC 288 |
| 74 | #define R_AARCH64_MOVW_PREL_G1 289 |
| 75 | #define R_AARCH64_MOVW_PREL_G1_NC 290 |
| 76 | #define R_AARCH64_MOVW_PREL_G2 291 |
| 77 | #define R_AARCH64_MOVW_PREL_G2_NC 292 |
| 78 | #define R_AARCH64_MOVW_PREL_G3 293 |
| 79 | |
Ard Biesheuvel | 1e48ef7 | 2016-01-26 09:13:44 +0100 | [diff] [blame] | 80 | #define R_AARCH64_RELATIVE 1027 |
| 81 | |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 82 | /* |
| 83 | * These are used to set parameters in the core dumps. |
| 84 | */ |
| 85 | #define ELF_CLASS ELFCLASS64 |
Will Deacon | 5436b5c | 2013-10-11 14:52:10 +0100 | [diff] [blame] | 86 | #ifdef __AARCH64EB__ |
| 87 | #define ELF_DATA ELFDATA2MSB |
| 88 | #else |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 89 | #define ELF_DATA ELFDATA2LSB |
Will Deacon | 5436b5c | 2013-10-11 14:52:10 +0100 | [diff] [blame] | 90 | #endif |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 91 | #define ELF_ARCH EM_AARCH64 |
| 92 | |
Will Deacon | 5436b5c | 2013-10-11 14:52:10 +0100 | [diff] [blame] | 93 | /* |
| 94 | * This yields a string that ld.so will use to load implementation |
| 95 | * specific libraries for optimization. This is more specific in |
| 96 | * intent than poking at uname or /proc/cpuinfo. |
| 97 | */ |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 98 | #define ELF_PLATFORM_SIZE 16 |
Will Deacon | 5436b5c | 2013-10-11 14:52:10 +0100 | [diff] [blame] | 99 | #ifdef __AARCH64EB__ |
| 100 | #define ELF_PLATFORM ("aarch64_be") |
| 101 | #else |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 102 | #define ELF_PLATFORM ("aarch64") |
Will Deacon | 5436b5c | 2013-10-11 14:52:10 +0100 | [diff] [blame] | 103 | #endif |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 104 | |
| 105 | /* |
| 106 | * This is used to ensure we don't load something for the wrong architecture. |
| 107 | */ |
| 108 | #define elf_check_arch(x) ((x)->e_machine == EM_AARCH64) |
| 109 | |
| 110 | #define elf_read_implies_exec(ex,stk) (stk != EXSTACK_DISABLE_X) |
| 111 | |
| 112 | #define CORE_DUMP_USE_REGSET |
| 113 | #define ELF_EXEC_PAGESIZE PAGE_SIZE |
| 114 | |
| 115 | /* |
Kees Cook | 0244599 | 2017-07-10 15:52:44 -0700 | [diff] [blame] | 116 | * This is the base location for PIE (ET_DYN with INTERP) loads. On |
Kees Cook | c715b72 | 2017-08-18 15:16:31 -0700 | [diff] [blame] | 117 | * 64-bit, this is above 4GB to leave the entire 32-bit address |
Kees Cook | 0244599 | 2017-07-10 15:52:44 -0700 | [diff] [blame] | 118 | * space open for things that want to use the area for 32-bit pointers. |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 119 | */ |
Kees Cook | c715b72 | 2017-08-18 15:16:31 -0700 | [diff] [blame] | 120 | #define ELF_ET_DYN_BASE (2 * TASK_SIZE_64 / 3) |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 121 | |
Ard Biesheuvel | 4a2e034 | 2016-01-11 17:08:26 +0100 | [diff] [blame] | 122 | #ifndef __ASSEMBLY__ |
| 123 | |
| 124 | typedef unsigned long elf_greg_t; |
| 125 | |
| 126 | #define ELF_NGREG (sizeof(struct user_pt_regs) / sizeof(elf_greg_t)) |
| 127 | #define ELF_CORE_COPY_REGS(dest, regs) \ |
| 128 | *(struct user_pt_regs *)&(dest) = (regs)->user_regs; |
| 129 | |
| 130 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; |
| 131 | typedef struct user_fpsimd_state elf_fpregset_t; |
| 132 | |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 133 | /* |
| 134 | * When the program starts, a1 contains a pointer to a function to be |
| 135 | * registered with atexit, as per the SVR4 ABI. A value of 0 means we have no |
| 136 | * such handler. |
| 137 | */ |
| 138 | #define ELF_PLAT_INIT(_r, load_addr) (_r)->regs[0] = 0 |
| 139 | |
Pratyush Anand | 06beb72 | 2016-11-02 14:40:45 +0530 | [diff] [blame] | 140 | #define SET_PERSONALITY(ex) \ |
| 141 | ({ \ |
Pratyush Anand | 06beb72 | 2016-11-02 14:40:45 +0530 | [diff] [blame] | 142 | clear_thread_flag(TIF_32BIT); \ |
Dong Bo | 48f99c8 | 2017-04-25 14:11:29 +0800 | [diff] [blame] | 143 | current->personality &= ~READ_IMPLIES_EXEC; \ |
Pratyush Anand | 06beb72 | 2016-11-02 14:40:45 +0530 | [diff] [blame] | 144 | }) |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 145 | |
James Hogan | 3146bc6 | 2016-07-25 16:59:52 +0100 | [diff] [blame] | 146 | /* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */ |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 147 | #define ARCH_DLINFO \ |
| 148 | do { \ |
| 149 | NEW_AUX_ENT(AT_SYSINFO_EHDR, \ |
| 150 | (elf_addr_t)current->mm->context.vdso); \ |
| 151 | } while (0) |
| 152 | |
| 153 | #define ARCH_HAS_SETUP_ADDITIONAL_PAGES |
| 154 | struct linux_binprm; |
| 155 | extern int arch_setup_additional_pages(struct linux_binprm *bprm, |
| 156 | int uses_interp); |
| 157 | |
| 158 | /* 1GB of VA */ |
| 159 | #ifdef CONFIG_COMPAT |
| 160 | #define STACK_RND_MASK (test_thread_flag(TIF_32BIT) ? \ |
| 161 | 0x7ff >> (PAGE_SHIFT - 12) : \ |
| 162 | 0x3ffff >> (PAGE_SHIFT - 12)) |
| 163 | #else |
| 164 | #define STACK_RND_MASK (0x3ffff >> (PAGE_SHIFT - 12)) |
| 165 | #endif |
| 166 | |
Will Deacon | a795a38 | 2013-10-11 14:52:12 +0100 | [diff] [blame] | 167 | #ifdef __AARCH64EB__ |
| 168 | #define COMPAT_ELF_PLATFORM ("v8b") |
| 169 | #else |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 170 | #define COMPAT_ELF_PLATFORM ("v8l") |
Will Deacon | a795a38 | 2013-10-11 14:52:12 +0100 | [diff] [blame] | 171 | #endif |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 172 | |
Catalin Marinas | e47b020 | 2016-05-31 15:55:03 +0100 | [diff] [blame] | 173 | #ifdef CONFIG_COMPAT |
| 174 | |
Kees Cook | 0244599 | 2017-07-10 15:52:44 -0700 | [diff] [blame] | 175 | /* PIE load location for compat arm. Must match ARM ELF_ET_DYN_BASE. */ |
| 176 | #define COMPAT_ELF_ET_DYN_BASE 0x000400000UL |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 177 | |
| 178 | /* AArch32 registers. */ |
| 179 | #define COMPAT_ELF_NGREG 18 |
| 180 | typedef unsigned int compat_elf_greg_t; |
| 181 | typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG]; |
| 182 | |
| 183 | /* AArch32 EABI. */ |
| 184 | #define EF_ARM_EABI_MASK 0xff000000 |
Suzuki K Poulose | 643d703 | 2016-04-18 10:28:37 +0100 | [diff] [blame] | 185 | #define compat_elf_check_arch(x) (system_supports_32bit_el0() && \ |
| 186 | ((x)->e_machine == EM_ARM) && \ |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 187 | ((x)->e_flags & EF_ARM_EABI_MASK)) |
| 188 | |
| 189 | #define compat_start_thread compat_start_thread |
Dong Bo | 48f99c8 | 2017-04-25 14:11:29 +0800 | [diff] [blame] | 190 | /* |
Ben Hutchings | 0c3039f | 2017-10-06 03:00:01 +0100 | [diff] [blame] | 191 | * Unlike the native SET_PERSONALITY macro, the compat version maintains |
| 192 | * READ_IMPLIES_EXEC across an execve() since this is the behaviour on |
Dong Bo | 48f99c8 | 2017-04-25 14:11:29 +0800 | [diff] [blame] | 193 | * arch/arm/. |
| 194 | */ |
Pratyush Anand | 06beb72 | 2016-11-02 14:40:45 +0530 | [diff] [blame] | 195 | #define COMPAT_SET_PERSONALITY(ex) \ |
| 196 | ({ \ |
Pratyush Anand | 06beb72 | 2016-11-02 14:40:45 +0530 | [diff] [blame] | 197 | set_thread_flag(TIF_32BIT); \ |
| 198 | }) |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 199 | #define COMPAT_ARCH_DLINFO |
| 200 | extern int aarch32_setup_vectors_page(struct linux_binprm *bprm, |
| 201 | int uses_interp); |
| 202 | #define compat_arch_setup_additional_pages \ |
| 203 | aarch32_setup_vectors_page |
| 204 | |
| 205 | #endif /* CONFIG_COMPAT */ |
| 206 | |
Ard Biesheuvel | 4a2e034 | 2016-01-11 17:08:26 +0100 | [diff] [blame] | 207 | #endif /* !__ASSEMBLY__ */ |
| 208 | |
Catalin Marinas | f668cd1 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 209 | #endif |