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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 2bbc078f812d45b8decb55935dab21199bd21489 / . / arch / arm / boot / dts / imx25-karo-tx25.dts
blob: 0950eb66d3d91540192c1fccc935daf1de4108f5 [file] [log] [blame]
Thomas Gleixnerfcaf2032019-05-27 08:55:08 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]2/*
3 * Copyright 2012 Sascha Hauer, Pengutronix
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]4 */
5
6/dts-v1/;
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]7#include "imx25.dtsi"
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]8
9/ {
10 model = "Ka-Ro TX25";
11 compatible = "karo,imx25-tx25", "fsl,imx25";
12
Sascha Hauer48f51962014-05-07 15:19:00 +0200[diff] [blame]13 chosen {
14 stdout-path = &uart1;
15 };
16
Sascha Hauer974e5872014-05-09 19:59:55 +0800[diff] [blame]17 regulators {
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 reg_fec_phy: regulator@0 {
23 compatible = "regulator-fixed";
24 reg = <0>;
25 regulator-name = "fec-phy";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
28 gpio = <&gpio4 9 0>;
29 enable-active-high;
30 };
31 };
32
Marco Franchiad00e082018-01-24 11:22:14 -0200[diff] [blame]33 memory@80000000 {
Fabio Estevam59d8bb32018-11-26 10:40:54 -0200[diff] [blame]34 device_type = "memory";
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]35 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
36 };
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]37};
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]38
Sascha Hauer8d690432014-05-09 08:11:17 +0200[diff] [blame]39&iomuxc {
40 pinctrl_uart1: uart1grp {
41 fsl,pins = <
42 MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
43 MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
44 MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
45 MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
46 >;
47 };
48
49 pinctrl_fec: fecgrp {
50 fsl,pins = <
51 MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */
52 MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */
53 MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
54 MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000
55 MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
56 MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
57 MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
58 MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
59 MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
60 MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
61 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
62 >;
63 };
64
65 pinctrl_nfc: nfcgrp {
66 fsl,pins = <
67 MX25_PAD_NF_CE0__NF_CE0 0x80000000
68 MX25_PAD_NFWE_B__NFWE_B 0x80000000
69 MX25_PAD_NFRE_B__NFRE_B 0x80000000
70 MX25_PAD_NFALE__NFALE 0x80000000
71 MX25_PAD_NFCLE__NFCLE 0x80000000
72 MX25_PAD_NFWP_B__NFWP_B 0x80000000
73 MX25_PAD_NFRB__NFRB 0x80000000
74 MX25_PAD_D7__D7 0x80000000
75 MX25_PAD_D6__D6 0x80000000
76 MX25_PAD_D5__D5 0x80000000
77 MX25_PAD_D4__D4 0x80000000
78 MX25_PAD_D3__D3 0x80000000
79 MX25_PAD_D2__D2 0x80000000
80 MX25_PAD_D1__D1 0x80000000
81 MX25_PAD_D0__D0 0x80000000
82 >;
83 };
84};
85
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]86&uart1 {
Sascha Hauer8d690432014-05-09 08:11:17 +0200[diff] [blame]87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]89 status = "okay";
90};
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]91
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]92&fec {
Sascha Hauer8d690432014-05-09 08:11:17 +0200[diff] [blame]93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_fec>;
Fabio Estevam12de44f2017-06-04 14:31:15 -0300[diff] [blame]95 phy-reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]96 phy-mode = "rmii";
Sascha Hauer974e5872014-05-09 19:59:55 +0800[diff] [blame]97 phy-supply = <&reg_fec_phy>;
Fabio Estevam152fab62013-01-04 10:29:09 -0200[diff] [blame]98 status = "okay";
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]99};
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]100
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]101&nfc {
Sascha Hauer8d690432014-05-09 08:11:17 +0200[diff] [blame]102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_nfc>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]104 nand-on-flash-bbt;
Sascha Hauer1885e5d2014-05-09 08:11:19 +0200[diff] [blame]105 nand-ecc-mode = "hw";
106 nand-bus-width = <8>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]107 status = "okay";
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]108};