| Zhou Wang | dfed009 | 2019-08-02 15:57:51 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* Copyright (c) 2019 HiSilicon Limited. */ |
| 3 | #ifndef HISI_ACC_SGL_H |
| 4 | #define HISI_ACC_SGL_H |
| 5 | |
| 6 | struct hisi_acc_sgl_pool { |
| 7 | struct hisi_acc_hw_sgl *sgl; |
| 8 | dma_addr_t sgl_dma; |
| 9 | size_t size; |
| 10 | u32 count; |
| 11 | size_t sgl_size; |
| 12 | }; |
| 13 | |
| 14 | struct hisi_acc_hw_sgl * |
| 15 | hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev, |
| 16 | struct scatterlist *sgl, |
| 17 | struct hisi_acc_sgl_pool *pool, |
| 18 | u32 index, dma_addr_t *hw_sgl_dma); |
| 19 | void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl, |
| 20 | struct hisi_acc_hw_sgl *hw_sgl); |
| 21 | int hisi_acc_create_sgl_pool(struct device *dev, struct hisi_acc_sgl_pool *pool, |
| 22 | u32 count); |
| 23 | void hisi_acc_free_sgl_pool(struct device *dev, struct hisi_acc_sgl_pool *pool); |
| 24 | #endif |