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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 2a0d35962ff114cc92f29d01d4a10f06fcdaeaec / . / arch / arm / boot / dts / sam9x60.dtsi
blob: ec45ced3cde68eb3492e619d31d261eaaf27248f [file] [log] [blame]
Sandeep Sheriker Mallikarjun1e5f5322020-01-15 12:59:47 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
4 *
5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
6 *
7 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
8 */
9
10#include <dt-bindings/dma/at91.h>
11#include <dt-bindings/pinctrl/at91.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/clock/at91.h>
15#include <dt-bindings/mfd/atmel-flexcom.h>
16
17/ {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 model = "Microchip SAM9X60 SoC";
21 compatible = "microchip,sam9x60";
22 interrupt-parent = <&aic>;
23
24 aliases {
25 serial0 = &dbgu;
26 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 gpio3 = &pioD;
30 tcb0 = &tcb0;
31 tcb1 = &tcb1;
32 };
33
34 cpus {
Alexandre Belloni58f98492020-08-31 19:11:23 +0200[diff] [blame]35 #address-cells = <1>;
Sandeep Sheriker Mallikarjun1e5f5322020-01-15 12:59:47 +0200[diff] [blame]36 #size-cells = <0>;
37
Alexandre Belloni58f98492020-08-31 19:11:23 +0200[diff] [blame]38 cpu@0 {
Sandeep Sheriker Mallikarjun1e5f5322020-01-15 12:59:47 +0200[diff] [blame]39 compatible = "arm,arm926ej-s";
40 device_type = "cpu";
Alexandre Belloni58f98492020-08-31 19:11:23 +0200[diff] [blame]41 reg = <0>;
Sandeep Sheriker Mallikarjun1e5f5322020-01-15 12:59:47 +0200[diff] [blame]42 };
43 };
44
Alexandre Belloni996710a2020-08-31 19:11:28 +0200[diff] [blame]45 memory@20000000 {
Sandeep Sheriker Mallikarjun1e5f5322020-01-15 12:59:47 +0200[diff] [blame]46 device_type = "memory";
47 reg = <0x20000000 0x10000000>;
48 };
49
50 clocks {
51 slow_xtal: slow_xtal {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 };
55
56 main_xtal: main_xtal {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 };
60 };
61
62 sram: sram@300000 {
63 compatible = "mmio-sram";
64 reg = <0x00300000 0x100000>;
Alexandre Bellonicd6228b2020-08-31 19:11:25 +0200[diff] [blame]65 #address-cells = <1>;
66 #size-cells = <1>;
67 ranges = <0 0x00300000 0x100000>;
Sandeep Sheriker Mallikarjun1e5f5322020-01-15 12:59:47 +0200[diff] [blame]68 };
69
70 ahb {
71 compatible = "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges;
75
Cristian Birsan84b522e2020-07-23 21:49:02 +0300[diff] [blame]76 usb0: gadget@500000 {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 compatible = "microchip,sam9x60-udc";
80 reg = <0x00500000 0x100000
81 0xf803c000 0x400>;
82 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
83 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
84 clock-names = "pclk", "hclk";
85 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
86 assigned-clock-rates = <480000000>;
87 status = "disabled";
88 };
89
Sandeep Sheriker Mallikarjun1e5f5322020-01-15 12:59:47 +0200[diff] [blame]90 usb1: ohci@600000 {
91 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
92 reg = <0x00600000 0x100000>;
93 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
94 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
95 clock-names = "ohci_clk", "hclk", "uhpck";
96 status = "disabled";
97 };
98
99 usb2: ehci@700000 {
100 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
101 reg = <0x00700000 0x100000>;
102 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
103 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
104 clock-names = "usb_clk", "ehci_clk";
105 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
106 assigned-clock-rates = <480000000>;
107 status = "disabled";
108 };
109
110 ebi: ebi@10000000 {
111 compatible = "microchip,sam9x60-ebi";
112 #address-cells = <2>;
113 #size-cells = <1>;
114 atmel,smc = <&smc>;
115 microchip,sfr = <&sfr>;
116 reg = <0x10000000 0x60000000>;
117 ranges = <0x0 0x0 0x10000000 0x10000000
118 0x1 0x0 0x20000000 0x10000000
119 0x2 0x0 0x30000000 0x10000000
120 0x3 0x0 0x40000000 0x10000000
121 0x4 0x0 0x50000000 0x10000000
122 0x5 0x0 0x60000000 0x10000000>;
123 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
124 status = "disabled";
125
126 nand_controller: nand-controller {
127 compatible = "microchip,sam9x60-nand-controller";
128 ecc-engine = <&pmecc>;
129 #address-cells = <2>;
130 #size-cells = <1>;
131 ranges;
132 status = "disabled";
133 };
134 };
135
136 sdmmc0: sdio-host@80000000 {
137 compatible = "microchip,sam9x60-sdhci";
138 reg = <0x80000000 0x300>;
139 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
140 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
141 clock-names = "hclock", "multclk";
142 assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
143 assigned-clock-rates = <100000000>;
144 status = "disabled";
145 };
146
147 sdmmc1: sdio-host@90000000 {
148 compatible = "microchip,sam9x60-sdhci";
149 reg = <0x90000000 0x300>;
150 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
151 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
152 clock-names = "hclock", "multclk";
153 assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
154 assigned-clock-rates = <100000000>;
155 status = "disabled";
156 };
157
158 apb {
159 compatible = "simple-bus";
160 #address-cells = <1>;
161 #size-cells = <1>;
162 ranges;
163
164 flx4: flexcom@f0000000 {
165 compatible = "atmel,sama5d2-flexcom";
166 reg = <0xf0000000 0x200>;
167 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
168 #address-cells = <1>;
169 #size-cells = <1>;
170 ranges = <0x0 0xf0000000 0x800>;
171 status = "disabled";
172 };
173
174 flx5: flexcom@f0004000 {
175 compatible = "atmel,sama5d2-flexcom";
176 reg = <0xf0004000 0x200>;
177 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
178 #address-cells = <1>;
179 #size-cells = <1>;
180 ranges = <0x0 0xf0004000 0x800>;
181 status = "disabled";
182 };
183
184 dma0: dma-controller@f0008000 {
185 compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
186 reg = <0xf0008000 0x1000>;
187 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
188 #dma-cells = <1>;
189 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
190 clock-names = "dma_clk";
191 };
192
193 ssc: ssc@f0010000 {
194 compatible = "atmel,at91sam9g45-ssc";
195 reg = <0xf0010000 0x4000>;
196 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
197 dmas = <&dma0
198 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
199 AT91_XDMAC_DT_PERID(38))>,
200 <&dma0
201 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
202 AT91_XDMAC_DT_PERID(39))>;
203 dma-names = "tx", "rx";
204 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
205 clock-names = "pclk";
206 status = "disabled";
207 };
208
209 qspi: spi@f0014000 {
210 compatible = "microchip,sam9x60-qspi";
211 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
212 reg-names = "qspi_base", "qspi_mmap";
213 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
214 dmas = <&dma0
215 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
216 AT91_XDMAC_DT_PERID(26))>,
217 <&dma0
218 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
219 AT91_XDMAC_DT_PERID(27))>;
220 dma-names = "tx", "rx";
221 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
222 clock-names = "pclk", "qspick";
223 atmel,pmc = <&pmc>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 status = "disabled";
227 };
228
229 i2s: i2s@f001c000 {
230 compatible = "microchip,sam9x60-i2smcc";
231 reg = <0xf001c000 0x100>;
232 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
233 dmas = <&dma0
234 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
235 AT91_XDMAC_DT_PERID(36))>,
236 <&dma0
237 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
238 AT91_XDMAC_DT_PERID(37))>;
239 dma-names = "tx", "rx";
240 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
241 clock-names = "pclk", "gclk";
242 status = "disabled";
243 };
244
245 flx11: flexcom@f0020000 {
246 compatible = "atmel,sama5d2-flexcom";
247 reg = <0xf0020000 0x200>;
248 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
249 #address-cells = <1>;
250 #size-cells = <1>;
251 ranges = <0x0 0xf0020000 0x800>;
252 status = "disabled";
253 };
254
255 flx12: flexcom@f0024000 {
256 compatible = "atmel,sama5d2-flexcom";
257 reg = <0xf0024000 0x200>;
258 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
259 #address-cells = <1>;
260 #size-cells = <1>;
261 ranges = <0x0 0xf0024000 0x800>;
262 status = "disabled";
263 };
264
265 pit64b: timer@f0028000 {
266 compatible = "microchip,sam9x60-pit64b";
267 reg = <0xf0028000 0x100>;
268 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
269 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
270 clock-names = "pclk", "gclk";
271 };
272
273 sha: sha@f002c000 {
274 compatible = "atmel,at91sam9g46-sha";
275 reg = <0xf002c000 0x100>;
276 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
277 dmas = <&dma0
278 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
279 AT91_XDMAC_DT_PERID(34))>;
280 dma-names = "tx";
281 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
282 clock-names = "sha_clk";
283 status = "okay";
284 };
285
286 trng: trng@f0030000 {
287 compatible = "microchip,sam9x60-trng";
288 reg = <0xf0030000 0x100>;
289 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
290 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
291 status = "okay";
292 };
293
294 aes: aes@f0034000 {
295 compatible = "atmel,at91sam9g46-aes";
296 reg = <0xf0034000 0x100>;
297 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
298 dmas = <&dma0
299 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
300 AT91_XDMAC_DT_PERID(32))>,
301 <&dma0
302 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
303 AT91_XDMAC_DT_PERID(33))>;
304 dma-names = "tx", "rx";
305 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
306 clock-names = "aes_clk";
307 status = "okay";
308 };
309
310 tdes: tdes@f0038000 {
311 compatible = "atmel,at91sam9g46-tdes";
312 reg = <0xf0038000 0x100>;
313 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
314 dmas = <&dma0
315 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
316 AT91_XDMAC_DT_PERID(31))>,
317 <&dma0
318 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
319 AT91_XDMAC_DT_PERID(30))>;
320 dma-names = "tx", "rx";
321 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
322 clock-names = "tdes_clk";
323 status = "okay";
324 };
325
326 classd: classd@f003c000 {
327 compatible = "atmel,sama5d2-classd";
328 reg = <0xf003c000 0x100>;
329 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
330 dmas = <&dma0
331 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
332 AT91_XDMAC_DT_PERID(35))>;
333 dma-names = "tx";
334 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
335 clock-names = "pclk", "gclk";
336 status = "disabled";
337 };
338
339 can0: can@f8000000 {
340 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
341 reg = <0xf8000000 0x300>;
342 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
343 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
344 clock-names = "can_clk";
345 status = "disabled";
346 };
347
348 can1: can@f8004000 {
349 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
350 reg = <0xf8004000 0x300>;
351 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
352 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
353 clock-names = "can_clk";
354 status = "disabled";
355 };
356
357 tcb0: timer@f8008000 {
358 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
359 #address-cells = <1>;
360 #size-cells = <0>;
361 reg = <0xf8008000 0x100>;
362 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
363 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
364 clock-names = "t0_clk", "slow_clk";
365 };
366
367 tcb1: timer@f800c000 {
368 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
369 #address-cells = <1>;
370 #size-cells = <0>;
371 reg = <0xf800c000 0x100>;
372 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
373 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
374 clock-names = "t0_clk", "slow_clk";
375 };
376
377 flx6: flexcom@f8010000 {
378 compatible = "atmel,sama5d2-flexcom";
379 reg = <0xf8010000 0x200>;
380 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
381 #address-cells = <1>;
382 #size-cells = <1>;
383 ranges = <0x0 0xf8010000 0x800>;
384 status = "disabled";
385 };
386
387 flx7: flexcom@f8014000 {
388 compatible = "atmel,sama5d2-flexcom";
389 reg = <0xf8014000 0x200>;
390 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
391 #address-cells = <1>;
392 #size-cells = <1>;
393 ranges = <0x0 0xf8014000 0x800>;
394 status = "disabled";
395 };
396
397 flx8: flexcom@f8018000 {
398 compatible = "atmel,sama5d2-flexcom";
399 reg = <0xf8018000 0x200>;
400 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
401 #address-cells = <1>;
402 #size-cells = <1>;
403 ranges = <0x0 0xf8018000 0x800>;
404 status = "disabled";
405 };
406
407 flx0: flexcom@f801c000 {
408 compatible = "atmel,sama5d2-flexcom";
409 reg = <0xf801c000 0x200>;
410 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
411 #address-cells = <1>;
412 #size-cells = <1>;
413 ranges = <0x0 0xf801c000 0x800>;
414 status = "disabled";
415 };
416
417 flx1: flexcom@f8020000 {
418 compatible = "atmel,sama5d2-flexcom";
419 reg = <0xf8020000 0x200>;
420 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
421 #address-cells = <1>;
422 #size-cells = <1>;
423 ranges = <0x0 0xf8020000 0x800>;
424 status = "disabled";
425 };
426
427 flx2: flexcom@f8024000 {
428 compatible = "atmel,sama5d2-flexcom";
429 reg = <0xf8024000 0x200>;
430 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
431 #address-cells = <1>;
432 #size-cells = <1>;
433 ranges = <0x0 0xf8024000 0x800>;
434 status = "disabled";
435 };
436
437 flx3: flexcom@f8028000 {
438 compatible = "atmel,sama5d2-flexcom";
439 reg = <0xf8028000 0x200>;
440 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
441 #address-cells = <1>;
442 #size-cells = <1>;
443 ranges = <0x0 0xf8028000 0x800>;
444 status = "disabled";
445 };
446
447 macb0: ethernet@f802c000 {
448 compatible = "cdns,sam9x60-macb", "cdns,macb";
449 reg = <0xf802c000 0x1000>;
450 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
451 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
452 clock-names = "hclk", "pclk";
453 status = "disabled";
454 };
455
456 macb1: ethernet@f8030000 {
457 compatible = "cdns,sam9x60-macb", "cdns,macb";
458 reg = <0xf8030000 0x1000>;
459 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
460 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
461 clock-names = "hclk", "pclk";
462 status = "disabled";
463 };
464
465 pwm0: pwm@f8034000 {
466 compatible = "microchip,sam9x60-pwm";
467 reg = <0xf8034000 0x300>;
468 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
469 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
470 #pwm-cells = <3>;
471 status="disabled";
472 };
473
474 hlcdc: hlcdc@f8038000 {
475 compatible = "microchip,sam9x60-hlcdc";
476 reg = <0xf8038000 0x4000>;
477 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
478 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
479 clock-names = "periph_clk","sys_clk", "slow_clk";
480 assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
481 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
482 status = "disabled";
483
484 hlcdc-display-controller {
485 compatible = "atmel,hlcdc-display-controller";
486 #address-cells = <1>;
487 #size-cells = <0>;
488
489 port@0 {
490 #address-cells = <1>;
491 #size-cells = <0>;
492 reg = <0>;
493 };
494 };
495
496 hlcdc_pwm: hlcdc-pwm {
497 compatible = "atmel,hlcdc-pwm";
498 #pwm-cells = <3>;
499 };
500 };
501
502 flx9: flexcom@f8040000 {
503 compatible = "atmel,sama5d2-flexcom";
504 reg = <0xf8040000 0x200>;
505 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
506 #address-cells = <1>;
507 #size-cells = <1>;
508 ranges = <0x0 0xf8040000 0x800>;
509 status = "disabled";
510 };
511
512 flx10: flexcom@f8044000 {
513 compatible = "atmel,sama5d2-flexcom";
514 reg = <0xf8044000 0x200>;
515 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
516 #address-cells = <1>;
517 #size-cells = <1>;
518 ranges = <0x0 0xf8044000 0x800>;
519 status = "disabled";
520 };
521
522 isi: isi@f8048000 {
523 compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
524 reg = <0xf8048000 0x100>;
525 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
526 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
527 clock-names = "isi_clk";
528 status = "disabled";
529 port {
530 #address-cells = <1>;
531 #size-cells = <0>;
532 };
533 };
534
535 adc: adc@f804c000 {
536 compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
537 reg = <0xf804c000 0x100>;
538 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
539 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
540 clock-names = "adc_clk";
541 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
542 dma-names = "rx";
543 atmel,min-sample-rate-hz = <200000>;
544 atmel,max-sample-rate-hz = <20000000>;
545 atmel,startup-time-ms = <4>;
546 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
547 #io-channel-cells = <1>;
548 status = "disabled";
549 };
550
551 sfr: sfr@f8050000 {
552 compatible = "microchip,sam9x60-sfr", "syscon";
553 reg = <0xf8050000 0x100>;
554 };
555
556 matrix: matrix@ffffde00 {
557 compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
558 reg = <0xffffde00 0x200>;
559 };
560
561 pmecc: ecc-engine@ffffe000 {
562 compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
563 reg = <0xffffe000 0x300>,
564 <0xffffe600 0x100>;
565 };
566
567 mpddrc: mpddrc@ffffe800 {
568 compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
569 reg = <0xffffe800 0x200>;
570 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
571 clock-names = "ddrck", "mpddr";
572 };
573
574 smc: smc@ffffea00 {
575 compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
576 reg = <0xffffea00 0x100>;
577 };
578
579 aic: interrupt-controller@fffff100 {
580 compatible = "microchip,sam9x60-aic";
581 #interrupt-cells = <3>;
582 interrupt-controller;
583 reg = <0xfffff100 0x100>;
584 atmel,external-irqs = <31>;
585 };
586
587 dbgu: serial@fffff200 {
588 compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
589 reg = <0xfffff200 0x200>;
590 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
591 dmas = <&dma0
592 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
593 AT91_XDMAC_DT_PERID(28))>,
594 <&dma0
595 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
596 AT91_XDMAC_DT_PERID(29))>;
597 dma-names = "tx", "rx";
598 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
599 clock-names = "usart";
600 status = "disabled";
601 };
602
603 pinctrl: pinctrl@fffff400 {
604 #address-cells = <1>;
605 #size-cells = <1>;
606 compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
607 ranges = <0xfffff400 0xfffff400 0x800>;
608
Nicolas Ferre2a0d3592021-03-10 16:20:06 +0100[diff] [blame^]609 /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
610 atmel,mux-mask = <
611 /* A B C */
612 0xffffffff 0xffe03fff 0xef00019d /* pioA */
613 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
614 0xffffffff 0xffffffff 0xf83fffff /* pioC */
615 0x003fffff 0x003f8000 0x00000000 /* pioD */
616 >;
617
Sandeep Sheriker Mallikarjun1e5f5322020-01-15 12:59:47 +0200[diff] [blame]618 pioA: gpio@fffff400 {
619 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
620 reg = <0xfffff400 0x200>;
621 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
622 #gpio-cells = <2>;
623 gpio-controller;
624 interrupt-controller;
625 #interrupt-cells = <2>;
626 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
627 };
628
629 pioB: gpio@fffff600 {
630 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
631 reg = <0xfffff600 0x200>;
632 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
633 #gpio-cells = <2>;
634 gpio-controller;
635 #gpio-lines = <26>;
636 interrupt-controller;
637 #interrupt-cells = <2>;
638 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
639 };
640
641 pioC: gpio@fffff800 {
642 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
643 reg = <0xfffff800 0x200>;
644 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
645 #gpio-cells = <2>;
646 gpio-controller;
647 interrupt-controller;
648 #interrupt-cells = <2>;
649 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
650 };
651
652 pioD: gpio@fffffa00 {
653 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
654 reg = <0xfffffa00 0x200>;
655 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
656 #gpio-cells = <2>;
657 gpio-controller;
658 #gpio-lines = <22>;
659 interrupt-controller;
660 #interrupt-cells = <2>;
661 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
662 };
663 };
664
665 pmc: pmc@fffffc00 {
666 compatible = "microchip,sam9x60-pmc", "syscon";
667 reg = <0xfffffc00 0x200>;
668 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
669 #clock-cells = <2>;
670 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
671 clock-names = "td_slck", "md_slck", "main_xtal";
672 };
673
674 reset_controller: rstc@fffffe00 {
675 compatible = "microchip,sam9x60-rstc";
676 reg = <0xfffffe00 0x10>;
677 clocks = <&clk32k 0>;
678 };
679
680 shutdown_controller: shdwc@fffffe10 {
681 compatible = "microchip,sam9x60-shdwc";
682 reg = <0xfffffe10 0x10>;
683 clocks = <&clk32k 0>;
684 #address-cells = <1>;
685 #size-cells = <0>;
686 atmel,wakeup-rtc-timer;
687 atmel,wakeup-rtt-timer;
688 status = "disabled";
689 };
690
Claudiu Beznea5f6b33f2020-06-10 12:05:36 +0300[diff] [blame]691 rtt: rtt@fffffe20 {
692 compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
693 reg = <0xfffffe20 0x20>;
694 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
695 clocks = <&clk32k 0>;
696 };
697
Sandeep Sheriker Mallikarjun1e5f5322020-01-15 12:59:47 +0200[diff] [blame]698 pit: timer@fffffe40 {
699 compatible = "atmel,at91sam9260-pit";
700 reg = <0xfffffe40 0x10>;
701 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
702 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
703 };
704
705 clk32k: sckc@fffffe50 {
706 compatible = "microchip,sam9x60-sckc";
707 reg = <0xfffffe50 0x4>;
708 clocks = <&slow_xtal>;
709 #clock-cells = <1>;
710 };
711
712 gpbr: syscon@fffffe60 {
713 compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
714 reg = <0xfffffe60 0x10>;
715 };
716
717 rtc: rtc@fffffea8 {
718 compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
719 reg = <0xfffffea8 0x100>;
720 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
721 clocks = <&clk32k 0>;
722 };
Eugen Hristev278af802020-02-11 08:07:14 +0000[diff] [blame]723
724 watchdog: watchdog@ffffff80 {
725 compatible = "microchip,sam9x60-wdt";
726 reg = <0xffffff80 0x24>;
727 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
728 clocks = <&clk32k 0>;
729 status = "disabled";
730 };
Sandeep Sheriker Mallikarjun1e5f5322020-01-15 12:59:47 +0200[diff] [blame]731 };
732 };
733};