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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 22cc1b6b35ce560ebf9252027397d5f1b92bfa9b / . / drivers / spi / spi-cavium.h
blob: d41dba5968fd9dcaf294a44ba5ccd91dd0f46086 [file] [log] [blame]
Jan Glauber22cc1b62016-07-23 12:42:53 +0200[diff] [blame^]1/* MPI register descriptions */
David Daney95d585f2012-05-11 14:34:45 -0700[diff] [blame]2
3#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
4#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
5#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
6#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
7
8union cvmx_mpi_cfg {
9 uint64_t u64;
10 struct cvmx_mpi_cfg_s {
11#ifdef __BIG_ENDIAN_BITFIELD
12 uint64_t reserved_29_63:35;
13 uint64_t clkdiv:13;
14 uint64_t csena3:1;
15 uint64_t csena2:1;
16 uint64_t csena1:1;
17 uint64_t csena0:1;
18 uint64_t cslate:1;
19 uint64_t tritx:1;
20 uint64_t idleclks:2;
21 uint64_t cshi:1;
22 uint64_t csena:1;
23 uint64_t int_ena:1;
24 uint64_t lsbfirst:1;
25 uint64_t wireor:1;
26 uint64_t clk_cont:1;
27 uint64_t idlelo:1;
28 uint64_t enable:1;
29#else
30 uint64_t enable:1;
31 uint64_t idlelo:1;
32 uint64_t clk_cont:1;
33 uint64_t wireor:1;
34 uint64_t lsbfirst:1;
35 uint64_t int_ena:1;
36 uint64_t csena:1;
37 uint64_t cshi:1;
38 uint64_t idleclks:2;
39 uint64_t tritx:1;
40 uint64_t cslate:1;
41 uint64_t csena0:1;
42 uint64_t csena1:1;
43 uint64_t csena2:1;
44 uint64_t csena3:1;
45 uint64_t clkdiv:13;
46 uint64_t reserved_29_63:35;
47#endif
48 } s;
49 struct cvmx_mpi_cfg_cn30xx {
50#ifdef __BIG_ENDIAN_BITFIELD
51 uint64_t reserved_29_63:35;
52 uint64_t clkdiv:13;
53 uint64_t reserved_12_15:4;
54 uint64_t cslate:1;
55 uint64_t tritx:1;
56 uint64_t idleclks:2;
57 uint64_t cshi:1;
58 uint64_t csena:1;
59 uint64_t int_ena:1;
60 uint64_t lsbfirst:1;
61 uint64_t wireor:1;
62 uint64_t clk_cont:1;
63 uint64_t idlelo:1;
64 uint64_t enable:1;
65#else
66 uint64_t enable:1;
67 uint64_t idlelo:1;
68 uint64_t clk_cont:1;
69 uint64_t wireor:1;
70 uint64_t lsbfirst:1;
71 uint64_t int_ena:1;
72 uint64_t csena:1;
73 uint64_t cshi:1;
74 uint64_t idleclks:2;
75 uint64_t tritx:1;
76 uint64_t cslate:1;
77 uint64_t reserved_12_15:4;
78 uint64_t clkdiv:13;
79 uint64_t reserved_29_63:35;
80#endif
81 } cn30xx;
82 struct cvmx_mpi_cfg_cn31xx {
83#ifdef __BIG_ENDIAN_BITFIELD
84 uint64_t reserved_29_63:35;
85 uint64_t clkdiv:13;
86 uint64_t reserved_11_15:5;
87 uint64_t tritx:1;
88 uint64_t idleclks:2;
89 uint64_t cshi:1;
90 uint64_t csena:1;
91 uint64_t int_ena:1;
92 uint64_t lsbfirst:1;
93 uint64_t wireor:1;
94 uint64_t clk_cont:1;
95 uint64_t idlelo:1;
96 uint64_t enable:1;
97#else
98 uint64_t enable:1;
99 uint64_t idlelo:1;
100 uint64_t clk_cont:1;
101 uint64_t wireor:1;
102 uint64_t lsbfirst:1;
103 uint64_t int_ena:1;
104 uint64_t csena:1;
105 uint64_t cshi:1;
106 uint64_t idleclks:2;
107 uint64_t tritx:1;
108 uint64_t reserved_11_15:5;
109 uint64_t clkdiv:13;
110 uint64_t reserved_29_63:35;
111#endif
112 } cn31xx;
113 struct cvmx_mpi_cfg_cn30xx cn50xx;
114 struct cvmx_mpi_cfg_cn61xx {
115#ifdef __BIG_ENDIAN_BITFIELD
116 uint64_t reserved_29_63:35;
117 uint64_t clkdiv:13;
118 uint64_t reserved_14_15:2;
119 uint64_t csena1:1;
120 uint64_t csena0:1;
121 uint64_t cslate:1;
122 uint64_t tritx:1;
123 uint64_t idleclks:2;
124 uint64_t cshi:1;
125 uint64_t reserved_6_6:1;
126 uint64_t int_ena:1;
127 uint64_t lsbfirst:1;
128 uint64_t wireor:1;
129 uint64_t clk_cont:1;
130 uint64_t idlelo:1;
131 uint64_t enable:1;
132#else
133 uint64_t enable:1;
134 uint64_t idlelo:1;
135 uint64_t clk_cont:1;
136 uint64_t wireor:1;
137 uint64_t lsbfirst:1;
138 uint64_t int_ena:1;
139 uint64_t reserved_6_6:1;
140 uint64_t cshi:1;
141 uint64_t idleclks:2;
142 uint64_t tritx:1;
143 uint64_t cslate:1;
144 uint64_t csena0:1;
145 uint64_t csena1:1;
146 uint64_t reserved_14_15:2;
147 uint64_t clkdiv:13;
148 uint64_t reserved_29_63:35;
149#endif
150 } cn61xx;
151 struct cvmx_mpi_cfg_cn66xx {
152#ifdef __BIG_ENDIAN_BITFIELD
153 uint64_t reserved_29_63:35;
154 uint64_t clkdiv:13;
155 uint64_t csena3:1;
156 uint64_t csena2:1;
157 uint64_t reserved_12_13:2;
158 uint64_t cslate:1;
159 uint64_t tritx:1;
160 uint64_t idleclks:2;
161 uint64_t cshi:1;
162 uint64_t reserved_6_6:1;
163 uint64_t int_ena:1;
164 uint64_t lsbfirst:1;
165 uint64_t wireor:1;
166 uint64_t clk_cont:1;
167 uint64_t idlelo:1;
168 uint64_t enable:1;
169#else
170 uint64_t enable:1;
171 uint64_t idlelo:1;
172 uint64_t clk_cont:1;
173 uint64_t wireor:1;
174 uint64_t lsbfirst:1;
175 uint64_t int_ena:1;
176 uint64_t reserved_6_6:1;
177 uint64_t cshi:1;
178 uint64_t idleclks:2;
179 uint64_t tritx:1;
180 uint64_t cslate:1;
181 uint64_t reserved_12_13:2;
182 uint64_t csena2:1;
183 uint64_t csena3:1;
184 uint64_t clkdiv:13;
185 uint64_t reserved_29_63:35;
186#endif
187 } cn66xx;
188 struct cvmx_mpi_cfg_cn61xx cnf71xx;
189};
190
191union cvmx_mpi_datx {
192 uint64_t u64;
193 struct cvmx_mpi_datx_s {
194#ifdef __BIG_ENDIAN_BITFIELD
195 uint64_t reserved_8_63:56;
196 uint64_t data:8;
197#else
198 uint64_t data:8;
199 uint64_t reserved_8_63:56;
200#endif
201 } s;
202 struct cvmx_mpi_datx_s cn30xx;
203 struct cvmx_mpi_datx_s cn31xx;
204 struct cvmx_mpi_datx_s cn50xx;
205 struct cvmx_mpi_datx_s cn61xx;
206 struct cvmx_mpi_datx_s cn66xx;
207 struct cvmx_mpi_datx_s cnf71xx;
208};
209
210union cvmx_mpi_sts {
211 uint64_t u64;
212 struct cvmx_mpi_sts_s {
213#ifdef __BIG_ENDIAN_BITFIELD
214 uint64_t reserved_13_63:51;
215 uint64_t rxnum:5;
216 uint64_t reserved_1_7:7;
217 uint64_t busy:1;
218#else
219 uint64_t busy:1;
220 uint64_t reserved_1_7:7;
221 uint64_t rxnum:5;
222 uint64_t reserved_13_63:51;
223#endif
224 } s;
225 struct cvmx_mpi_sts_s cn30xx;
226 struct cvmx_mpi_sts_s cn31xx;
227 struct cvmx_mpi_sts_s cn50xx;
228 struct cvmx_mpi_sts_s cn61xx;
229 struct cvmx_mpi_sts_s cn66xx;
230 struct cvmx_mpi_sts_s cnf71xx;
231};
232
233union cvmx_mpi_tx {
234 uint64_t u64;
235 struct cvmx_mpi_tx_s {
236#ifdef __BIG_ENDIAN_BITFIELD
237 uint64_t reserved_22_63:42;
238 uint64_t csid:2;
239 uint64_t reserved_17_19:3;
240 uint64_t leavecs:1;
241 uint64_t reserved_13_15:3;
242 uint64_t txnum:5;
243 uint64_t reserved_5_7:3;
244 uint64_t totnum:5;
245#else
246 uint64_t totnum:5;
247 uint64_t reserved_5_7:3;
248 uint64_t txnum:5;
249 uint64_t reserved_13_15:3;
250 uint64_t leavecs:1;
251 uint64_t reserved_17_19:3;
252 uint64_t csid:2;
253 uint64_t reserved_22_63:42;
254#endif
255 } s;
256 struct cvmx_mpi_tx_cn30xx {
257#ifdef __BIG_ENDIAN_BITFIELD
258 uint64_t reserved_17_63:47;
259 uint64_t leavecs:1;
260 uint64_t reserved_13_15:3;
261 uint64_t txnum:5;
262 uint64_t reserved_5_7:3;
263 uint64_t totnum:5;
264#else
265 uint64_t totnum:5;
266 uint64_t reserved_5_7:3;
267 uint64_t txnum:5;
268 uint64_t reserved_13_15:3;
269 uint64_t leavecs:1;
270 uint64_t reserved_17_63:47;
271#endif
272 } cn30xx;
273 struct cvmx_mpi_tx_cn30xx cn31xx;
274 struct cvmx_mpi_tx_cn30xx cn50xx;
275 struct cvmx_mpi_tx_cn61xx {
276#ifdef __BIG_ENDIAN_BITFIELD
277 uint64_t reserved_21_63:43;
278 uint64_t csid:1;
279 uint64_t reserved_17_19:3;
280 uint64_t leavecs:1;
281 uint64_t reserved_13_15:3;
282 uint64_t txnum:5;
283 uint64_t reserved_5_7:3;
284 uint64_t totnum:5;
285#else
286 uint64_t totnum:5;
287 uint64_t reserved_5_7:3;
288 uint64_t txnum:5;
289 uint64_t reserved_13_15:3;
290 uint64_t leavecs:1;
291 uint64_t reserved_17_19:3;
292 uint64_t csid:1;
293 uint64_t reserved_21_63:43;
294#endif
295 } cn61xx;
296 struct cvmx_mpi_tx_s cn66xx;
297 struct cvmx_mpi_tx_cn61xx cnf71xx;
298};