blob: 4ef1764aa8a55942a4222344cd6dc6fe09228f43 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Chris Wilsone9b73c62012-12-03 21:03:14 +000033#include <uapi/drm/i915_drm.h>
Tvrtko Ursulin93b81f52015-02-10 17:16:05 +000034#include <uapi/drm/drm_fourcc.h>
Chris Wilsone9b73c62012-12-03 21:03:14 +000035
Jesse Barnes585fb112008-07-29 11:54:06 -070036#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080037#include "intel_bios.h"
Zou Nan hai8187a2b2010-05-21 09:08:55 +080038#include "intel_ringbuffer.h"
Oscar Mateob20385f2014-07-24 17:04:10 +010039#include "intel_lrc.h"
Ben Widawsky0260c422014-03-22 22:47:21 -070040#include "i915_gem_gtt.h"
Oscar Mateo564ddb22014-08-21 11:40:54 +010041#include "i915_gem_render_state.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070042#include <linux/io-mapping.h>
Chris Wilsonf899fc62010-07-20 15:44:45 -070043#include <linux/i2c.h>
Daniel Vetterc167a6f2012-02-28 00:43:09 +010044#include <linux/i2c-algo-bit.h>
Daniel Vetter0ade6382010-08-24 22:18:41 +020045#include <drm/intel-gtt.h>
Daniel Vetterba8286f2014-09-11 07:43:25 +020046#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
Daniel Vetterd9fc9412014-09-23 15:46:53 +020047#include <drm/drm_gem.h>
Matthew Garrettaaa6fd22011-08-12 12:11:33 +020048#include <linux/backlight.h>
Chris Wilson5cc9ed42014-05-16 14:22:37 +010049#include <linux/hashtable.h>
Ben Widawsky2911a352012-04-05 14:47:36 -070050#include <linux/intel-iommu.h>
Daniel Vetter742cbee2012-04-27 15:17:39 +020051#include <linux/kref.h>
Daniel Vetter9ee32fea2012-12-01 13:53:48 +010052#include <linux/pm_qos.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070053
Linus Torvalds1da177e2005-04-16 15:20:36 -070054/* General customization:
55 */
56
Linus Torvalds1da177e2005-04-16 15:20:36 -070057#define DRIVER_NAME "i915"
58#define DRIVER_DESC "Intel Graphics"
Daniel Vettera3d1d002015-07-03 15:53:23 +020059#define DRIVER_DATE "20150703"
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
Mika Kuoppalac883ef12014-10-28 17:32:30 +020061#undef WARN_ON
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010062/* Many gcc seem to no see through this and fall over :( */
63#if 0
64#define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
69#else
70#define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
71#endif
72
Jani Nikulacd9bfac2015-03-12 13:01:12 +020073#undef WARN_ON_ONCE
74#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
75
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010076#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
Mika Kuoppalac883ef12014-10-28 17:32:30 +020078
Rob Clarke2c719b2014-12-15 13:56:32 -050079/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
84 * spam.
85 */
86#define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
Jani Nikula2f3408c2015-01-12 15:45:31 +020090 WARN(1, format); \
Rob Clarke2c719b2014-12-15 13:56:32 -050091 else \
92 DRM_ERROR(format); \
93 } \
94 unlikely(__ret_warn_on); \
95})
96
97#define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
Jani Nikula2f3408c2015-01-12 15:45:31 +0200101 WARN(1, "WARN_ON(" #condition ")\n"); \
Rob Clarke2c719b2014-12-15 13:56:32 -0500102 else \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
104 } \
105 unlikely(__ret_warn_on); \
106})
Jesse Barnes317c35d2008-08-25 15:11:06 -0700107
108enum pipe {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800109 INVALID_PIPE = -1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200110 PIPE_A = 0,
111 PIPE_B,
Jesse Barnes317c35d2008-08-25 15:11:06 -0700112 PIPE_C,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800113 _PIPE_EDP,
Jesse Barnes317c35d2008-08-25 15:11:06 -0700114 I915_MAX_PIPES = _PIPE_EDP
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200115};
116#define pipe_name(p) ((p) + 'A')
117
118enum transcoder {
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200119 TRANSCODER_A = 0,
120 TRANSCODER_B,
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200121 TRANSCODER_C,
122 TRANSCODER_EDP,
123 I915_MAX_TRANSCODERS
Damien Lespiau84139d12014-03-28 00:18:32 +0530124};
125#define transcoder_name(t) ((t) + 'A')
126
127/*
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
130 *
131 * This value doesn't count the cursor plane.
Jesse Barnes80824002009-09-10 15:28:06 -0700132 */
Damien Lespiau8232edb2015-03-17 11:39:35 +0200133#define I915_MAX_PLANES 4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134
Jesse Barnes80824002009-09-10 15:28:06 -0700135enum plane {
136 PLANE_A = 0,
137 PLANE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800138 PLANE_C,
Jesse Barnes80824002009-09-10 15:28:06 -0700139};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800140#define plane_name(p) ((p) + 'A')
Keith Packard52440212008-11-18 09:30:25 -0800141
Damien Lespiaud615a162014-03-03 17:31:48 +0000142#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
Ville Syrjälä06da8da2013-04-17 17:48:51 +0300143
Eugeni Dodonov2b139522012-03-29 12:32:22 -0300144enum port {
145 PORT_A = 0,
146 PORT_B,
147 PORT_C,
148 PORT_D,
149 PORT_E,
150 I915_MAX_PORTS
151};
152#define port_name(p) ((p) + 'A')
153
Chon Ming Leea09cadd2014-04-09 13:28:14 +0300154#define I915_NUM_PHYS_VLV 2
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800155
156enum dpio_channel {
157 DPIO_CH0,
158 DPIO_CH1
159};
160
161enum dpio_phy {
162 DPIO_PHY0,
163 DPIO_PHY1
164};
165
Paulo Zanonib97186f2013-05-03 12:15:36 -0300166enum intel_display_power_domain {
167 POWER_DOMAIN_PIPE_A,
168 POWER_DOMAIN_PIPE_B,
169 POWER_DOMAIN_PIPE_C,
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
173 POWER_DOMAIN_TRANSCODER_A,
174 POWER_DOMAIN_TRANSCODER_B,
175 POWER_DOMAIN_TRANSCODER_C,
Imre Deakf52e3532013-10-16 17:25:48 +0300176 POWER_DOMAIN_TRANSCODER_EDP,
Imre Deak319be8a2014-03-04 19:22:57 +0200177 POWER_DOMAIN_PORT_DDI_A_2_LANES,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES,
185 POWER_DOMAIN_PORT_DSI,
186 POWER_DOMAIN_PORT_CRT,
187 POWER_DOMAIN_PORT_OTHER,
Ville Syrjäläcdf8dd72013-09-16 17:38:30 +0300188 POWER_DOMAIN_VGA,
Imre Deakfbeeaa22013-11-25 17:15:28 +0200189 POWER_DOMAIN_AUDIO,
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -0300190 POWER_DOMAIN_PLLS,
Satheeshakrishna M14071212015-01-16 15:57:51 +0000191 POWER_DOMAIN_AUX_A,
192 POWER_DOMAIN_AUX_B,
193 POWER_DOMAIN_AUX_C,
194 POWER_DOMAIN_AUX_D,
Imre Deakbaa70702013-10-25 17:36:48 +0300195 POWER_DOMAIN_INIT,
Imre Deakbddc7642013-10-16 17:25:49 +0300196
197 POWER_DOMAIN_NUM,
Paulo Zanonib97186f2013-05-03 12:15:36 -0300198};
199
200#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
201#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
202 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
Imre Deakf52e3532013-10-16 17:25:48 +0300203#define POWER_DOMAIN_TRANSCODER(tran) \
204 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
205 (tran) + POWER_DOMAIN_TRANSCODER_A)
Paulo Zanonib97186f2013-05-03 12:15:36 -0300206
Egbert Eich1d843f92013-02-25 12:06:49 -0500207enum hpd_pin {
208 HPD_NONE = 0,
209 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
211 HPD_CRT,
212 HPD_SDVO_B,
213 HPD_SDVO_C,
214 HPD_PORT_B,
215 HPD_PORT_C,
216 HPD_PORT_D,
217 HPD_NUM_PINS
218};
219
Jani Nikulac91711f2015-05-28 15:43:48 +0300220#define for_each_hpd_pin(__pin) \
221 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
222
Jani Nikula5fcece82015-05-27 15:03:42 +0300223struct i915_hotplug {
224 struct work_struct hotplug_work;
225
226 struct {
227 unsigned long last_jiffies;
228 int count;
229 enum {
230 HPD_ENABLED = 0,
231 HPD_DISABLED = 1,
232 HPD_MARK_DISABLED = 2
233 } state;
234 } stats[HPD_NUM_PINS];
235 u32 event_bits;
236 struct delayed_work reenable_work;
237
238 struct intel_digital_port *irq_port[I915_MAX_PORTS];
239 u32 long_port_mask;
240 u32 short_port_mask;
241 struct work_struct dig_port_work;
242
243 /*
244 * if we get a HPD irq from DP and a HPD irq from non-DP
245 * the non-DP HPD could block the workqueue on a mode config
246 * mutex getting, that userspace may have taken. However
247 * userspace is waiting on the DP workqueue to run which is
248 * blocked behind the non-DP one.
249 */
250 struct workqueue_struct *dp_wq;
251};
252
Chris Wilson2a2d5482012-12-03 11:49:06 +0000253#define I915_GEM_GPU_DOMAINS \
254 (I915_GEM_DOMAIN_RENDER | \
255 I915_GEM_DOMAIN_SAMPLER | \
256 I915_GEM_DOMAIN_COMMAND | \
257 I915_GEM_DOMAIN_INSTRUCTION | \
258 I915_GEM_DOMAIN_VERTEX)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700259
Damien Lespiau055e3932014-08-18 13:49:10 +0100260#define for_each_pipe(__dev_priv, __p) \
261 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
Damien Lespiaudd740782015-02-28 14:54:08 +0000262#define for_each_plane(__dev_priv, __pipe, __p) \
263 for ((__p) = 0; \
264 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
265 (__p)++)
Damien Lespiau3bdcfc02015-02-28 14:54:09 +0000266#define for_each_sprite(__dev_priv, __p, __s) \
267 for ((__s) = 0; \
268 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
269 (__s)++)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800270
Damien Lespiaud79b8142014-05-13 23:32:23 +0100271#define for_each_crtc(dev, crtc) \
272 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
273
Maarten Lankhorst27321ae2015-04-21 17:12:52 +0300274#define for_each_intel_plane(dev, intel_plane) \
275 list_for_each_entry(intel_plane, \
276 &dev->mode_config.plane_list, \
277 base.head)
278
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300279#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
280 list_for_each_entry(intel_plane, \
281 &(dev)->mode_config.plane_list, \
282 base.head) \
283 if ((intel_plane)->pipe == (intel_crtc)->pipe)
284
Damien Lespiaud063ae42014-05-13 23:32:21 +0100285#define for_each_intel_crtc(dev, intel_crtc) \
286 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
287
Damien Lespiaub2784e12014-08-05 11:29:37 +0100288#define for_each_intel_encoder(dev, intel_encoder) \
289 list_for_each_entry(intel_encoder, \
290 &(dev)->mode_config.encoder_list, \
291 base.head)
292
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +0200293#define for_each_intel_connector(dev, intel_connector) \
294 list_for_each_entry(intel_connector, \
295 &dev->mode_config.connector_list, \
296 base.head)
297
Daniel Vetter6c2b7c12012-07-05 09:50:24 +0200298#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
299 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
300 if ((intel_encoder)->base.crtc == (__crtc))
301
Jesse Barnes53f5e3c2014-02-07 12:48:15 -0800302#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
303 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
304 if ((intel_connector)->base.encoder == (__encoder))
305
Borun Fub04c5bd2014-07-12 10:02:27 +0530306#define for_each_power_domain(domain, mask) \
307 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
308 if ((1 << (domain)) & (mask))
309
Daniel Vettere7b903d2013-06-05 13:34:14 +0200310struct drm_i915_private;
Chris Wilsonad46cb52014-08-07 14:20:40 +0100311struct i915_mm_struct;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100312struct i915_mmu_object;
Daniel Vettere7b903d2013-06-05 13:34:14 +0200313
Chris Wilsona6f766f2015-04-27 13:41:20 +0100314struct drm_i915_file_private {
315 struct drm_i915_private *dev_priv;
316 struct drm_file *file;
317
318 struct {
319 spinlock_t lock;
320 struct list_head request_list;
Chris Wilsond0bc54f2015-05-21 21:01:48 +0100321/* 20ms is a fairly arbitrary limit (greater than the average frame time)
322 * chosen to prevent the CPU getting more than a frame ahead of the GPU
323 * (when using lax throttling for the frontbuffer). We also use it to
324 * offer free GPU waitboosts for severely congested workloads.
325 */
326#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
Chris Wilsona6f766f2015-04-27 13:41:20 +0100327 } mm;
328 struct idr context_idr;
329
Chris Wilson2e1b8732015-04-27 13:41:22 +0100330 struct intel_rps_client {
331 struct list_head link;
332 unsigned boosts;
333 } rps;
Chris Wilsona6f766f2015-04-27 13:41:20 +0100334
Chris Wilson2e1b8732015-04-27 13:41:22 +0100335 struct intel_engine_cs *bsd_ring;
Chris Wilsona6f766f2015-04-27 13:41:20 +0100336};
337
Daniel Vettere2b78262013-06-07 23:10:03 +0200338enum intel_dpll_id {
339 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
340 /* real shared dpll ids must be >= 0 */
Daniel Vetter9cd86932014-06-25 22:01:57 +0300341 DPLL_ID_PCH_PLL_A = 0,
342 DPLL_ID_PCH_PLL_B = 1,
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000343 /* hsw/bdw */
Daniel Vetter9cd86932014-06-25 22:01:57 +0300344 DPLL_ID_WRPLL1 = 0,
345 DPLL_ID_WRPLL2 = 1,
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000346 /* skl */
347 DPLL_ID_SKL_DPLL1 = 0,
348 DPLL_ID_SKL_DPLL2 = 1,
349 DPLL_ID_SKL_DPLL3 = 2,
Daniel Vettere2b78262013-06-07 23:10:03 +0200350};
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000351#define I915_NUM_PLLS 3
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100352
Daniel Vetter53589012013-06-05 13:34:16 +0200353struct intel_dpll_hw_state {
Damien Lespiaudcfc3552014-07-29 18:06:16 +0100354 /* i9xx, pch plls */
Daniel Vetter66e985c2013-06-05 13:34:20 +0200355 uint32_t dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +0200356 uint32_t dpll_md;
Daniel Vetter66e985c2013-06-05 13:34:20 +0200357 uint32_t fp0;
358 uint32_t fp1;
Damien Lespiaudcfc3552014-07-29 18:06:16 +0100359
360 /* hsw, bdw */
Daniel Vetterd452c5b2014-07-04 11:27:39 -0300361 uint32_t wrpll;
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +0000362
363 /* skl */
364 /*
365 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
Damien Lespiau71cd8422015-04-30 16:39:17 +0100366 * lower part of ctrl1 and they get shifted into position when writing
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +0000367 * the register. This allows us to easily compare the state to share
368 * the DPLL.
369 */
370 uint32_t ctrl1;
371 /* HDMI only, 0 when used for DP */
372 uint32_t cfgcr1, cfgcr2;
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +0530373
374 /* bxt */
Imre Deak05712c12015-06-18 17:25:54 +0300375 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
376 pcsdw12;
Daniel Vetter53589012013-06-05 13:34:16 +0200377};
378
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +0200379struct intel_shared_dpll_config {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +0200380 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +0200381 struct intel_dpll_hw_state hw_state;
382};
383
384struct intel_shared_dpll {
385 struct intel_shared_dpll_config config;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +0200386
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387 int active; /* count of number of active CRTCs (i.e. DPMS on) */
388 bool on; /* is the PLL actually active? Disabled during modeset */
Daniel Vetter46edb022013-06-05 13:34:12 +0200389 const char *name;
390 /* should match the index in the dev_priv->shared_dplls array */
391 enum intel_dpll_id id;
Daniel Vetter96f61282014-06-25 22:01:58 +0300392 /* The mode_set hook is optional and should be used together with the
393 * intel_prepare_shared_dpll function. */
Daniel Vetter15bdd4c2013-06-05 13:34:23 +0200394 void (*mode_set)(struct drm_i915_private *dev_priv,
395 struct intel_shared_dpll *pll);
Daniel Vettere7b903d2013-06-05 13:34:14 +0200396 void (*enable)(struct drm_i915_private *dev_priv,
397 struct intel_shared_dpll *pll);
398 void (*disable)(struct drm_i915_private *dev_priv,
399 struct intel_shared_dpll *pll);
Daniel Vetter53589012013-06-05 13:34:16 +0200400 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
401 struct intel_shared_dpll *pll,
402 struct intel_dpll_hw_state *hw_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000405#define SKL_DPLL0 0
406#define SKL_DPLL1 1
407#define SKL_DPLL2 2
408#define SKL_DPLL3 3
409
Daniel Vettere69d0bc2012-11-29 15:59:36 +0100410/* Used by dp and fdi links */
411struct intel_link_m_n {
412 uint32_t tu;
413 uint32_t gmch_m;
414 uint32_t gmch_n;
415 uint32_t link_m;
416 uint32_t link_n;
417};
418
419void intel_link_compute_m_n(int bpp, int nlanes,
420 int pixel_clock, int link_clock,
421 struct intel_link_m_n *m_n);
422
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423/* Interface history:
424 *
425 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +1100426 * 1.2: Add Power Management
427 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +1100428 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +1000429 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000430 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
431 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432 */
433#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000434#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435#define DRIVER_PATCHLEVEL 0
436
Chris Wilson23bc5982010-09-29 16:10:57 +0100437#define WATCH_LISTS 0
Eric Anholt673a3942008-07-30 12:06:12 -0700438
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700439struct opregion_header;
440struct opregion_acpi;
441struct opregion_swsci;
442struct opregion_asle;
443
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100444struct intel_opregion {
Ben Widawsky5bc44182012-04-16 14:07:42 -0700445 struct opregion_header __iomem *header;
446 struct opregion_acpi __iomem *acpi;
447 struct opregion_swsci __iomem *swsci;
Jani Nikulaebde53c2013-09-02 10:38:59 +0300448 u32 swsci_gbda_sub_functions;
449 u32 swsci_sbcb_sub_functions;
Ben Widawsky5bc44182012-04-16 14:07:42 -0700450 struct opregion_asle __iomem *asle;
451 void __iomem *vbt;
Chris Wilson01fe9db2011-01-16 19:37:30 +0000452 u32 __iomem *lid_state;
Jani Nikula91a60f22013-10-31 18:55:48 +0200453 struct work_struct asle_work;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100454};
Chris Wilson44834a62010-08-19 16:09:23 +0100455#define OPREGION_SIZE (8*1024)
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100456
Chris Wilson6ef3d422010-08-04 20:26:07 +0100457struct intel_overlay;
458struct intel_overlay_error_state;
459
Jesse Barnesde151cf2008-11-12 10:03:55 -0800460#define I915_FENCE_REG_NONE -1
Ville Syrjälä42b5aea2013-04-09 13:02:47 +0300461#define I915_MAX_NUM_FENCES 32
462/* 32 fences + sign bit for FENCE_REG_NONE */
463#define I915_MAX_NUM_FENCE_BITS 6
Jesse Barnesde151cf2008-11-12 10:03:55 -0800464
465struct drm_i915_fence_reg {
Daniel Vetter007cc8a2010-04-28 11:02:31 +0200466 struct list_head lru_list;
Chris Wilsoncaea7472010-11-12 13:53:37 +0000467 struct drm_i915_gem_object *obj;
Chris Wilson1690e1e2011-12-14 13:57:08 +0100468 int pin_count;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800469};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000470
yakui_zhao9b9d1722009-05-31 17:17:17 +0800471struct sdvo_device_mapping {
Chris Wilsone957d772010-09-24 12:52:03 +0100472 u8 initialized;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800473 u8 dvo_port;
474 u8 slave_addr;
475 u8 dvo_wiring;
Chris Wilsone957d772010-09-24 12:52:03 +0100476 u8 i2c_pin;
Adam Jacksonb1083332010-04-23 16:07:40 -0400477 u8 ddc_pin;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800478};
479
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000480struct intel_display_error_state;
481
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700482struct drm_i915_error_state {
Daniel Vetter742cbee2012-04-27 15:17:39 +0200483 struct kref ref;
Ben Widawsky585b0282014-01-30 00:19:37 -0800484 struct timeval time;
485
Mika Kuoppalacb383002014-02-25 17:11:25 +0200486 char error_msg[128];
Mika Kuoppala48b031e2014-02-25 17:11:27 +0200487 u32 reset_count;
Mika Kuoppala62d5d692014-02-25 17:11:28 +0200488 u32 suspend_count;
Mika Kuoppalacb383002014-02-25 17:11:25 +0200489
Ben Widawsky585b0282014-01-30 00:19:37 -0800490 /* Generic register state */
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700491 u32 eir;
492 u32 pgtbl_er;
Ben Widawskybe998e22012-04-26 16:03:00 -0700493 u32 ier;
Rodrigo Vivi885ea5a2014-08-05 10:07:13 -0700494 u32 gtier[4];
Ben Widawskyb9a39062012-06-04 14:42:52 -0700495 u32 ccid;
Chris Wilson0f3b6842013-01-15 12:05:55 +0000496 u32 derrmr;
497 u32 forcewake;
Ben Widawsky585b0282014-01-30 00:19:37 -0800498 u32 error; /* gen6+ */
499 u32 err_int; /* gen7 */
Mika Kuoppala6c826f32015-03-24 14:54:19 +0200500 u32 fault_data0; /* gen8, gen9 */
501 u32 fault_data1; /* gen8, gen9 */
Ben Widawsky585b0282014-01-30 00:19:37 -0800502 u32 done_reg;
Ben Widawsky91ec5d12014-01-30 00:19:39 -0800503 u32 gac_eco;
504 u32 gam_ecochk;
505 u32 gab_ctl;
506 u32 gfx_mode;
Ben Widawsky585b0282014-01-30 00:19:37 -0800507 u32 extra_instdone[I915_NUM_INSTDONE_REG];
Ben Widawsky585b0282014-01-30 00:19:37 -0800508 u64 fence[I915_MAX_NUM_FENCES];
509 struct intel_overlay_error_state *overlay;
510 struct intel_display_error_state *display;
Ben Widawsky0ca36d72014-06-30 09:53:41 -0700511 struct drm_i915_error_object *semaphore_obj;
Ben Widawsky585b0282014-01-30 00:19:37 -0800512
Chris Wilson52d39a22012-02-15 11:25:37 +0000513 struct drm_i915_error_ring {
Chris Wilson372fbb82014-01-27 13:52:34 +0000514 bool valid;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800515 /* Software tracked state */
516 bool waiting;
517 int hangcheck_score;
518 enum intel_ring_hangcheck_action hangcheck_action;
519 int num_requests;
520
521 /* our own tracking of ring head and tail */
522 u32 cpu_ring_head;
523 u32 cpu_ring_tail;
524
525 u32 semaphore_seqno[I915_NUM_RINGS - 1];
526
527 /* Register state */
Chris Wilson94f8cf12015-04-07 16:20:47 +0100528 u32 start;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800529 u32 tail;
530 u32 head;
531 u32 ctl;
532 u32 hws;
533 u32 ipeir;
534 u32 ipehr;
535 u32 instdone;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800536 u32 bbstate;
537 u32 instpm;
538 u32 instps;
539 u32 seqno;
540 u64 bbaddr;
Chris Wilson50877442014-03-21 12:41:53 +0000541 u64 acthd;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800542 u32 fault_reg;
Ben Widawsky13ffadd2014-04-01 16:31:07 -0700543 u64 faddr;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800544 u32 rc_psmi; /* sleep state */
545 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
546
Chris Wilson52d39a22012-02-15 11:25:37 +0000547 struct drm_i915_error_object {
548 int page_count;
549 u32 gtt_offset;
550 u32 *pages[0];
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200551 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800552
Chris Wilson52d39a22012-02-15 11:25:37 +0000553 struct drm_i915_error_request {
554 long jiffies;
555 u32 seqno;
Chris Wilsonee4f42b2012-02-15 11:25:38 +0000556 u32 tail;
Chris Wilson52d39a22012-02-15 11:25:37 +0000557 } *requests;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800558
559 struct {
560 u32 gfx_mode;
561 union {
562 u64 pdp[4];
563 u32 pp_dir_base;
564 };
565 } vm_info;
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200566
567 pid_t pid;
568 char comm[TASK_COMM_LEN];
Chris Wilson52d39a22012-02-15 11:25:37 +0000569 } ring[I915_NUM_RINGS];
Chris Wilson3a448732014-08-12 20:05:47 +0100570
Chris Wilson9df30792010-02-18 10:24:56 +0000571 struct drm_i915_error_buffer {
Chris Wilsona779e5a2011-01-09 21:07:49 +0000572 u32 size;
Chris Wilson9df30792010-02-18 10:24:56 +0000573 u32 name;
Chris Wilsonb4716182015-04-27 13:41:17 +0100574 u32 rseqno[I915_NUM_RINGS], wseqno;
Chris Wilson9df30792010-02-18 10:24:56 +0000575 u32 gtt_offset;
576 u32 read_domains;
577 u32 write_domain;
Daniel Vetter4b9de732011-10-09 21:52:02 +0200578 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
Chris Wilson9df30792010-02-18 10:24:56 +0000579 s32 pinned:2;
580 u32 tiling:2;
581 u32 dirty:1;
582 u32 purgeable:1;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100583 u32 userptr:1;
Daniel Vetter5d1333f2012-02-16 11:03:29 +0100584 s32 ring:4;
Chris Wilsonf56383c2013-09-25 10:23:19 +0100585 u32 cache_level:3;
Ben Widawsky95f53012013-07-31 17:00:15 -0700586 } **active_bo, **pinned_bo;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800587
Ben Widawsky95f53012013-07-31 17:00:15 -0700588 u32 *active_bo_count, *pinned_bo_count;
Chris Wilson3a448732014-08-12 20:05:47 +0100589 u32 vm_count;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700590};
591
Jani Nikula7bd688c2013-11-08 16:48:56 +0200592struct intel_connector;
Jani Nikula820d2d72014-10-27 16:26:47 +0200593struct intel_encoder;
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200594struct intel_crtc_state;
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000595struct intel_initial_plane_config;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100596struct intel_crtc;
Daniel Vetteree9300b2013-06-03 22:40:22 +0200597struct intel_limit;
598struct dpll;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100599
Jesse Barnese70236a2009-09-21 10:42:27 -0700600struct drm_i915_display_funcs {
Jesse Barnese70236a2009-09-21 10:42:27 -0700601 int (*get_display_clock_speed)(struct drm_device *dev);
602 int (*get_fifo_size)(struct drm_device *dev, int plane);
Daniel Vetteree9300b2013-06-03 22:40:22 +0200603 /**
604 * find_dpll() - Find the best values for the PLL
605 * @limit: limits for the PLL
606 * @crtc: current CRTC
607 * @target: target frequency in kHz
608 * @refclk: reference clock frequency in kHz
609 * @match_clock: if provided, @best_clock P divider must
610 * match the P divider from @match_clock
611 * used for LVDS downclocking
612 * @best_clock: best PLL values found
613 *
614 * Returns true on success, false on failure.
615 */
616 bool (*find_dpll)(const struct intel_limit *limit,
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200617 struct intel_crtc_state *crtc_state,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200618 int target, int refclk,
619 struct dpll *match_clock,
620 struct dpll *best_clock);
Ville Syrjälä46ba6142013-09-10 11:40:40 +0300621 void (*update_wm)(struct drm_crtc *crtc);
Ville Syrjäläadf3d352013-08-06 22:24:11 +0300622 void (*update_sprite_wm)(struct drm_plane *plane,
623 struct drm_crtc *crtc,
Damien Lespiaued57cb82014-07-15 09:21:24 +0200624 uint32_t sprite_width, uint32_t sprite_height,
625 int pixel_size, bool enable, bool scaled);
Maarten Lankhorst27c329e2015-06-15 12:33:56 +0200626 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
627 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100628 /* Returns the active state of the crtc, and if the crtc is active,
629 * fills out the pipe-config with the hw state. */
630 bool (*get_pipe_config)(struct intel_crtc *,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200631 struct intel_crtc_state *);
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000632 void (*get_initial_plane_config)(struct intel_crtc *,
633 struct intel_initial_plane_config *);
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +0200634 int (*crtc_compute_clock)(struct intel_crtc *crtc,
635 struct intel_crtc_state *crtc_state);
Daniel Vetter76e5a892012-06-29 22:39:33 +0200636 void (*crtc_enable)(struct drm_crtc *crtc);
637 void (*crtc_disable)(struct drm_crtc *crtc);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200638 void (*audio_codec_enable)(struct drm_connector *connector,
639 struct intel_encoder *encoder,
640 struct drm_display_mode *mode);
641 void (*audio_codec_disable)(struct intel_encoder *encoder);
Jesse Barnes674cf962011-04-28 14:27:04 -0700642 void (*fdi_link_train)(struct drm_crtc *crtc);
Jesse Barnes6067aae2011-04-28 15:04:31 -0700643 void (*init_clock_gating)(struct drm_device *dev);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -0700644 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
645 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -0700646 struct drm_i915_gem_object *obj,
John Harrison6258fbe2015-05-29 17:43:48 +0100647 struct drm_i915_gem_request *req,
Keith Packarded8d1972013-07-22 18:49:58 -0700648 uint32_t flags);
Daniel Vetter29b9bde2014-04-24 23:55:01 +0200649 void (*update_primary_plane)(struct drm_crtc *crtc,
650 struct drm_framebuffer *fb,
651 int x, int y);
Daniel Vetter20afbda2012-12-11 14:05:07 +0100652 void (*hpd_irq_setup)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700653 /* clock updates for mode set */
654 /* cursor updates */
655 /* render clock increase/decrease */
656 /* display clock increase/decrease */
657 /* pll clock increase/decrease */
Jani Nikula7bd688c2013-11-08 16:48:56 +0200658
Ville Syrjälä6517d272014-11-07 11:16:02 +0200659 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
Jani Nikula7bd688c2013-11-08 16:48:56 +0200660 uint32_t (*get_backlight)(struct intel_connector *connector);
661 void (*set_backlight)(struct intel_connector *connector,
662 uint32_t level);
663 void (*disable_backlight)(struct intel_connector *connector);
664 void (*enable_backlight)(struct intel_connector *connector);
Jesse Barnese70236a2009-09-21 10:42:27 -0700665};
666
Mika Kuoppala48c10262015-01-16 11:34:41 +0200667enum forcewake_domain_id {
668 FW_DOMAIN_ID_RENDER = 0,
669 FW_DOMAIN_ID_BLITTER,
670 FW_DOMAIN_ID_MEDIA,
671
672 FW_DOMAIN_ID_COUNT
673};
674
675enum forcewake_domains {
676 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
677 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
678 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
679 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
680 FORCEWAKE_BLITTER |
681 FORCEWAKE_MEDIA)
682};
683
Chris Wilson907b28c2013-07-19 20:36:52 +0100684struct intel_uncore_funcs {
Deepak Sc8d9a592013-11-23 14:55:42 +0530685 void (*force_wake_get)(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +0200686 enum forcewake_domains domains);
Deepak Sc8d9a592013-11-23 14:55:42 +0530687 void (*force_wake_put)(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +0200688 enum forcewake_domains domains);
Ben Widawsky0b274482013-10-04 21:22:51 -0700689
690 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
691 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
692 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
693 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
694
695 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
696 uint8_t val, bool trace);
697 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
698 uint16_t val, bool trace);
699 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
700 uint32_t val, bool trace);
701 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
702 uint64_t val, bool trace);
Chris Wilson990bbda2012-07-02 11:51:02 -0300703};
704
Chris Wilson907b28c2013-07-19 20:36:52 +0100705struct intel_uncore {
706 spinlock_t lock; /** lock is also taken in irq contexts. */
707
708 struct intel_uncore_funcs funcs;
709
710 unsigned fifo_count;
Mika Kuoppala48c10262015-01-16 11:34:41 +0200711 enum forcewake_domains fw_domains;
Chris Wilsonaec347a2013-08-26 13:46:09 +0100712
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200713 struct intel_uncore_forcewake_domain {
714 struct drm_i915_private *i915;
Mika Kuoppala48c10262015-01-16 11:34:41 +0200715 enum forcewake_domain_id id;
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200716 unsigned wake_count;
717 struct timer_list timer;
Mika Kuoppala05a2fb12015-01-19 16:20:43 +0200718 u32 reg_set;
719 u32 val_set;
720 u32 val_clear;
721 u32 reg_ack;
722 u32 reg_post;
723 u32 val_reset;
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200724 } fw_domain[FW_DOMAIN_ID_COUNT];
Chris Wilson907b28c2013-07-19 20:36:52 +0100725};
726
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200727/* Iterate over initialised fw domains */
728#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
729 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
730 (i__) < FW_DOMAIN_ID_COUNT; \
731 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
732 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
733
734#define for_each_fw_domain(domain__, dev_priv__, i__) \
735 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
736
Suketu Shahdc174302015-04-17 19:46:16 +0530737enum csr_state {
738 FW_UNINITIALIZED = 0,
739 FW_LOADED,
740 FW_FAILED
741};
742
Daniel Vettereb805622015-05-04 14:58:44 +0200743struct intel_csr {
744 const char *fw_path;
745 __be32 *dmc_payload;
746 uint32_t dmc_fw_size;
747 uint32_t mmio_count;
748 uint32_t mmioaddr[8];
749 uint32_t mmiodata[8];
Suketu Shahdc174302015-04-17 19:46:16 +0530750 enum csr_state state;
Daniel Vettereb805622015-05-04 14:58:44 +0200751};
752
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100753#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
754 func(is_mobile) sep \
755 func(is_i85x) sep \
756 func(is_i915g) sep \
757 func(is_i945gm) sep \
758 func(is_g33) sep \
759 func(need_gfx_hws) sep \
760 func(is_g4x) sep \
761 func(is_pineview) sep \
762 func(is_broadwater) sep \
763 func(is_crestline) sep \
764 func(is_ivybridge) sep \
765 func(is_valleyview) sep \
766 func(is_haswell) sep \
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +0530767 func(is_skylake) sep \
Ben Widawskyb833d682013-08-23 16:00:07 -0700768 func(is_preliminary) sep \
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100769 func(has_fbc) sep \
770 func(has_pipe_cxsr) sep \
771 func(has_hotplug) sep \
772 func(cursor_needs_physical) sep \
773 func(has_overlay) sep \
774 func(overlay_needs_physical) sep \
775 func(supports_tv) sep \
Damien Lespiaudd93be52013-04-22 18:40:39 +0100776 func(has_llc) sep \
Damien Lespiau30568c42013-04-22 18:40:41 +0100777 func(has_ddi) sep \
778 func(has_fpga_dbg)
Daniel Vetterc96ea642012-08-08 22:01:51 +0200779
Damien Lespiaua587f772013-04-22 18:40:38 +0100780#define DEFINE_FLAG(name) u8 name:1
781#define SEP_SEMICOLON ;
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200782
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500783struct intel_device_info {
Ville Syrjälä10fce672013-01-24 15:29:28 +0200784 u32 display_mmio_offset;
Chris Wilson87f1f462014-08-09 19:18:42 +0100785 u16 device_id;
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700786 u8 num_pipes:3;
Damien Lespiaud615a162014-03-03 17:31:48 +0000787 u8 num_sprites[I915_MAX_PIPES];
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000788 u8 gen;
Ben Widawsky73ae4782013-10-15 10:02:57 -0700789 u8 ring_mask; /* Rings supported by the HW */
Damien Lespiaua587f772013-04-22 18:40:38 +0100790 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200791 /* Register offsets for the various display pipes and transcoders */
792 int pipe_offsets[I915_MAX_TRANSCODERS];
793 int trans_offsets[I915_MAX_TRANSCODERS];
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200794 int palette_offsets[I915_MAX_PIPES];
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300795 int cursor_offsets[I915_MAX_PIPES];
Jeff McGee38732182015-02-13 10:27:54 -0600796
797 /* Slice/subslice/EU info */
798 u8 slice_total;
799 u8 subslice_total;
800 u8 subslice_per_slice;
801 u8 eu_total;
802 u8 eu_per_subslice;
Damien Lespiaub7668792015-02-14 18:30:29 +0000803 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
804 u8 subslice_7eu[3];
Jeff McGee38732182015-02-13 10:27:54 -0600805 u8 has_slice_pg:1;
806 u8 has_subslice_pg:1;
807 u8 has_eu_pg:1;
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500808};
809
Damien Lespiaua587f772013-04-22 18:40:38 +0100810#undef DEFINE_FLAG
811#undef SEP_SEMICOLON
812
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800813enum i915_cache_level {
814 I915_CACHE_NONE = 0,
Chris Wilson350ec882013-08-06 13:17:02 +0100815 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
816 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
817 caches, eg sampler/render caches, and the
818 large Last-Level-Cache. LLC is coherent with
819 the CPU, but L3 is only visible to the GPU. */
Chris Wilson651d7942013-08-08 14:41:10 +0100820 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800821};
822
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300823struct i915_ctx_hang_stats {
824 /* This context had batch pending when hang was declared */
825 unsigned batch_pending;
826
827 /* This context had batch active when hang was declared */
828 unsigned batch_active;
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300829
830 /* Time when this context was last blamed for a GPU reset */
831 unsigned long guilty_ts;
832
Chris Wilson676fa572014-12-24 08:13:39 -0800833 /* If the contexts causes a second GPU hang within this time,
834 * it is permanently banned from submitting any more work.
835 */
836 unsigned long ban_period_seconds;
837
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300838 /* This context is banned to submit more work */
839 bool banned;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300840};
Ben Widawsky40521052012-06-04 14:42:43 -0700841
842/* This must match up with the value previously used for execbuf2.rsvd1. */
Oscar Mateo821d66d2014-07-03 16:28:00 +0100843#define DEFAULT_CONTEXT_HANDLE 0
David Weinehallb1b38272015-05-20 17:00:13 +0300844
845#define CONTEXT_NO_ZEROMAP (1<<0)
Oscar Mateo31b7a882014-07-03 16:28:01 +0100846/**
847 * struct intel_context - as the name implies, represents a context.
848 * @ref: reference count.
849 * @user_handle: userspace tracking identity for this context.
850 * @remap_slice: l3 row remapping information.
David Weinehallb1b38272015-05-20 17:00:13 +0300851 * @flags: context specific flags:
852 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
Oscar Mateo31b7a882014-07-03 16:28:01 +0100853 * @file_priv: filp associated with this context (NULL for global default
854 * context).
855 * @hang_stats: information about the role of this context in possible GPU
856 * hangs.
Tvrtko Ursulin7df113e2015-04-17 12:49:07 +0100857 * @ppgtt: virtual memory space used by this context.
Oscar Mateo31b7a882014-07-03 16:28:01 +0100858 * @legacy_hw_ctx: render context backing object and whether it is correctly
859 * initialized (legacy ring submission mechanism only).
860 * @link: link in the global list of contexts.
861 *
862 * Contexts are memory images used by the hardware to store copies of their
863 * internal state.
864 */
Oscar Mateo273497e2014-05-22 14:13:37 +0100865struct intel_context {
Mika Kuoppaladce32712013-04-30 13:30:33 +0300866 struct kref ref;
Oscar Mateo821d66d2014-07-03 16:28:00 +0100867 int user_handle;
Ben Widawsky3ccfd192013-09-18 19:03:18 -0700868 uint8_t remap_slice;
David Weinehallb1b38272015-05-20 17:00:13 +0300869 int flags;
Ben Widawsky40521052012-06-04 14:42:43 -0700870 struct drm_i915_file_private *file_priv;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300871 struct i915_ctx_hang_stats hang_stats;
Daniel Vetterae6c4802014-08-06 15:04:53 +0200872 struct i915_hw_ppgtt *ppgtt;
Ben Widawskya33afea2013-09-17 21:12:45 -0700873
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100874 /* Legacy ring buffer submission */
Oscar Mateoea0c76f2014-07-03 16:27:59 +0100875 struct {
876 struct drm_i915_gem_object *rcs_state;
877 bool initialized;
878 } legacy_hw_ctx;
879
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100880 /* Execlists */
Oscar Mateo564ddb22014-08-21 11:40:54 +0100881 bool rcs_initialized;
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100882 struct {
883 struct drm_i915_gem_object *state;
Oscar Mateo84c23772014-07-24 17:04:15 +0100884 struct intel_ringbuffer *ringbuf;
Mika Kuoppalaa7cbede2015-01-13 11:32:25 +0200885 int pin_count;
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100886 } engine[I915_NUM_RINGS];
887
Ben Widawskya33afea2013-09-17 21:12:45 -0700888 struct list_head link;
Ben Widawsky40521052012-06-04 14:42:43 -0700889};
890
Paulo Zanonia4001f12015-02-13 17:23:44 -0200891enum fb_op_origin {
892 ORIGIN_GTT,
893 ORIGIN_CPU,
894 ORIGIN_CS,
895 ORIGIN_FLIP,
896};
897
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700898struct i915_fbc {
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300899 /* This is always the inner lock when overlapping with struct_mutex and
900 * it's the outer lock when overlapping with stolen_lock. */
901 struct mutex lock;
Jani Nikula60ee5cd2015-02-05 12:04:27 +0200902 unsigned long uncompressed_size;
Ben Widawsky5e59f712014-06-30 10:41:24 -0700903 unsigned threshold;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700904 unsigned int fb_id;
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200905 unsigned int possible_framebuffer_bits;
906 unsigned int busy_bits;
Paulo Zanonie35fef22015-02-09 14:46:29 -0200907 struct intel_crtc *crtc;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700908 int y;
909
Ben Widawskyc4213882014-06-19 12:06:10 -0700910 struct drm_mm_node compressed_fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700911 struct drm_mm_node *compressed_llb;
912
Rodrigo Vivida46f932014-08-01 02:04:45 -0700913 bool false_color;
914
Paulo Zanoni9adccc62014-09-19 16:04:55 -0300915 /* Tracks whether the HW is actually enabled, not whether the feature is
916 * possible. */
917 bool enabled;
918
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700919 struct intel_fbc_work {
920 struct delayed_work work;
Paulo Zanoni220285f2015-07-07 15:26:05 -0300921 struct intel_crtc *crtc;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700922 struct drm_framebuffer *fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700923 } *fbc_work;
924
Chris Wilson29ebf902013-07-27 17:23:55 +0100925 enum no_fbc_reason {
926 FBC_OK, /* FBC is enabled */
927 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700928 FBC_NO_OUTPUT, /* no outputs enabled to compress */
929 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
930 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
931 FBC_MODE_TOO_LARGE, /* mode too large for compression */
932 FBC_BAD_PLANE, /* fbc not supported on plane */
933 FBC_NOT_TILED, /* buffer not tiled */
934 FBC_MULTIPLE_PIPES, /* more than one pipe active */
935 FBC_MODULE_PARAM,
936 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
Paulo Zanoni87f5ff02015-06-12 14:36:19 -0300937 FBC_ROTATION, /* rotation is not supported */
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700938 } no_fbc_reason;
Paulo Zanoniff2a3112015-07-07 15:26:03 -0300939
Paulo Zanoni7733b492015-07-07 15:26:04 -0300940 bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
Paulo Zanoni220285f2015-07-07 15:26:05 -0300941 void (*enable_fbc)(struct intel_crtc *crtc);
Paulo Zanoni7733b492015-07-07 15:26:04 -0300942 void (*disable_fbc)(struct drm_i915_private *dev_priv);
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800943};
944
Vandana Kannan96178ee2015-01-10 02:25:56 +0530945/**
946 * HIGH_RR is the highest eDP panel refresh rate read from EDID
947 * LOW_RR is the lowest eDP panel refresh rate found from EDID
948 * parsing for same resolution.
949 */
950enum drrs_refresh_rate_type {
951 DRRS_HIGH_RR,
952 DRRS_LOW_RR,
953 DRRS_MAX_RR, /* RR count */
954};
955
956enum drrs_support_type {
957 DRRS_NOT_SUPPORTED = 0,
958 STATIC_DRRS_SUPPORT = 1,
959 SEAMLESS_DRRS_SUPPORT = 2
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530960};
961
Daniel Vetter2807cf62014-07-11 10:30:11 -0700962struct intel_dp;
Vandana Kannan96178ee2015-01-10 02:25:56 +0530963struct i915_drrs {
964 struct mutex mutex;
965 struct delayed_work work;
966 struct intel_dp *dp;
967 unsigned busy_frontbuffer_bits;
968 enum drrs_refresh_rate_type refresh_rate_type;
969 enum drrs_support_type type;
970};
971
Rodrigo Vivia031d702013-10-03 16:15:06 -0300972struct i915_psr {
Daniel Vetterf0355c42014-07-11 10:30:15 -0700973 struct mutex lock;
Rodrigo Vivia031d702013-10-03 16:15:06 -0300974 bool sink_support;
975 bool source_ok;
Daniel Vetter2807cf62014-07-11 10:30:11 -0700976 struct intel_dp *enabled;
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -0700977 bool active;
978 struct delayed_work work;
Daniel Vetter9ca15302014-07-11 10:30:16 -0700979 unsigned busy_frontbuffer_bits;
Sonika Jindal474d1ec2015-04-02 11:02:44 +0530980 bool psr2_support;
981 bool aux_frame_sync;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -0300982};
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700983
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800984enum intel_pch {
Paulo Zanonif0350832012-07-03 18:48:16 -0300985 PCH_NONE = 0, /* No PCH present */
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800986 PCH_IBX, /* Ibexpeak PCH */
987 PCH_CPT, /* Cougarpoint PCH */
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300988 PCH_LPT, /* Lynxpoint PCH */
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530989 PCH_SPT, /* Sunrisepoint PCH */
Ben Widawsky40c7ead2013-04-05 13:12:40 -0700990 PCH_NOP,
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800991};
992
Paulo Zanoni988d6ee2012-12-01 12:04:24 -0200993enum intel_sbi_destination {
994 SBI_ICLK,
995 SBI_MPHY,
996};
997
Jesse Barnesb690e962010-07-19 13:53:12 -0700998#define QUIRK_PIPEA_FORCE (1<<0)
Keith Packard435793d2011-07-12 14:56:22 -0700999#define QUIRK_LVDS_SSC_DISABLE (1<<1)
Carsten Emde4dca20e2012-03-15 15:56:26 +01001000#define QUIRK_INVERT_BRIGHTNESS (1<<2)
Scot Doyle9c72cc62014-07-03 23:27:50 +00001001#define QUIRK_BACKLIGHT_PRESENT (1<<3)
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001002#define QUIRK_PIPEB_FORCE (1<<4)
Daniel Vetter656bfa32014-11-20 09:26:30 +01001003#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
Jesse Barnesb690e962010-07-19 13:53:12 -07001004
Dave Airlie8be48d92010-03-30 05:34:14 +00001005struct intel_fbdev;
Chris Wilson1630fe72011-07-08 12:22:42 +01001006struct intel_fbc_work;
Dave Airlie38651672010-03-30 05:34:13 +00001007
Daniel Vetterc2b91522012-02-14 22:37:19 +01001008struct intel_gmbus {
1009 struct i2c_adapter adapter;
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +00001010 u32 force_bit;
Daniel Vetterc2b91522012-02-14 22:37:19 +01001011 u32 reg0;
Daniel Vetter36c785f2012-02-14 22:37:22 +01001012 u32 gpio_reg;
Daniel Vetterc167a6f2012-02-28 00:43:09 +01001013 struct i2c_algo_bit_data bit_algo;
Daniel Vetterc2b91522012-02-14 22:37:19 +01001014 struct drm_i915_private *dev_priv;
1015};
1016
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001017struct i915_suspend_saved_registers {
Keith Packarde948e992008-05-07 12:27:53 +10001018 u32 saveDSPARB;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001019 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -07001020 u32 savePP_ON_DELAYS;
1021 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001022 u32 savePP_ON;
1023 u32 savePP_OFF;
1024 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -07001025 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001026 u32 saveFBC_CONTROL;
Keith Packard1f84e552008-02-16 19:19:29 -08001027 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -08001028 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001029 u32 saveSWF0[16];
1030 u32 saveSWF1[16];
1031 u32 saveSWF2[3];
Daniel Vetter4b9de732011-10-09 21:52:02 +02001032 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
Adam Jacksoncda2bb72011-07-26 16:53:06 -04001033 u32 savePCH_PORT_HOTPLUG;
Jesse Barnes9f49c372014-12-10 12:16:05 -08001034 u16 saveGCDGMBUS;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001035};
Daniel Vetterc85aa882012-11-02 19:55:03 +01001036
Imre Deakddeea5b2014-05-05 15:19:56 +03001037struct vlv_s0ix_state {
1038 /* GAM */
1039 u32 wr_watermark;
1040 u32 gfx_prio_ctrl;
1041 u32 arb_mode;
1042 u32 gfx_pend_tlb0;
1043 u32 gfx_pend_tlb1;
1044 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1045 u32 media_max_req_count;
1046 u32 gfx_max_req_count;
1047 u32 render_hwsp;
1048 u32 ecochk;
1049 u32 bsd_hwsp;
1050 u32 blt_hwsp;
1051 u32 tlb_rd_addr;
1052
1053 /* MBC */
1054 u32 g3dctl;
1055 u32 gsckgctl;
1056 u32 mbctl;
1057
1058 /* GCP */
1059 u32 ucgctl1;
1060 u32 ucgctl3;
1061 u32 rcgctl1;
1062 u32 rcgctl2;
1063 u32 rstctl;
1064 u32 misccpctl;
1065
1066 /* GPM */
1067 u32 gfxpause;
1068 u32 rpdeuhwtc;
1069 u32 rpdeuc;
1070 u32 ecobus;
1071 u32 pwrdwnupctl;
1072 u32 rp_down_timeout;
1073 u32 rp_deucsw;
1074 u32 rcubmabdtmr;
1075 u32 rcedata;
1076 u32 spare2gh;
1077
1078 /* Display 1 CZ domain */
1079 u32 gt_imr;
1080 u32 gt_ier;
1081 u32 pm_imr;
1082 u32 pm_ier;
1083 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1084
1085 /* GT SA CZ domain */
1086 u32 tilectl;
1087 u32 gt_fifoctl;
1088 u32 gtlc_wake_ctrl;
1089 u32 gtlc_survive;
1090 u32 pmwgicz;
1091
1092 /* Display 2 CZ domain */
1093 u32 gu_ctl0;
1094 u32 gu_ctl1;
Jesse Barnes9c252102015-04-01 14:22:57 -07001095 u32 pcbr;
Imre Deakddeea5b2014-05-05 15:19:56 +03001096 u32 clock_gate_dis2;
1097};
1098
Chris Wilsonbf225f22014-07-10 20:31:18 +01001099struct intel_rps_ei {
1100 u32 cz_clock;
1101 u32 render_c0;
1102 u32 media_c0;
Deepak S31685c22014-07-03 17:33:01 -04001103};
1104
Daniel Vetterc85aa882012-11-02 19:55:03 +01001105struct intel_gen6_power_mgmt {
Imre Deakd4d70aa2014-11-19 15:30:04 +02001106 /*
1107 * work, interrupts_enabled and pm_iir are protected by
1108 * dev_priv->irq_lock
1109 */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001110 struct work_struct work;
Imre Deakd4d70aa2014-11-19 15:30:04 +02001111 bool interrupts_enabled;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001112 u32 pm_iir;
Daniel Vetter59cdb632013-07-04 23:35:28 +02001113
Ben Widawskyb39fb292014-03-19 18:31:11 -07001114 /* Frequencies are stored in potentially platform dependent multiples.
1115 * In other words, *_freq needs to be multiplied by X to be interesting.
1116 * Soft limits are those which are used for the dynamic reclocking done
1117 * by the driver (raise frequencies under heavy loads, and lower for
1118 * lighter loads). Hard limits are those imposed by the hardware.
1119 *
1120 * A distinction is made for overclocking, which is never enabled by
1121 * default, and is considered to be above the hard limit if it's
1122 * possible at all.
1123 */
1124 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1125 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1126 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1127 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1128 u8 min_freq; /* AKA RPn. Minimum frequency */
Chris Wilsonaed242f2015-03-18 09:48:21 +00001129 u8 idle_freq; /* Frequency to request when we are idle */
Ben Widawskyb39fb292014-03-19 18:31:11 -07001130 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1131 u8 rp1_freq; /* "less than" RP0 power/freqency */
1132 u8 rp0_freq; /* Non-overclocked max frequency. */
Deepak S67c3bf62014-07-10 13:16:24 +05301133 u32 cz_freq;
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001134
Chris Wilson8fb55192015-04-07 16:20:28 +01001135 u8 up_threshold; /* Current %busy required to uplock */
1136 u8 down_threshold; /* Current %busy required to downclock */
1137
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001138 int last_adj;
1139 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1140
Chris Wilson8d3afd72015-05-21 21:01:47 +01001141 spinlock_t client_lock;
1142 struct list_head clients;
1143 bool client_boost;
1144
Chris Wilsonc0951f02013-10-10 21:58:50 +01001145 bool enabled;
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001146 struct delayed_work delayed_resume_work;
Chris Wilson1854d5c2015-04-07 16:20:32 +01001147 unsigned boosts;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001148
Chris Wilson2e1b8732015-04-27 13:41:22 +01001149 struct intel_rps_client semaphores, mmioflips;
Chris Wilsona6f766f2015-04-27 13:41:20 +01001150
Chris Wilsonbf225f22014-07-10 20:31:18 +01001151 /* manual wa residency calculations */
1152 struct intel_rps_ei up_ei, down_ei;
1153
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001154 /*
1155 * Protects RPS/RC6 register access and PCU communication.
Chris Wilson8d3afd72015-05-21 21:01:47 +01001156 * Must be taken after struct_mutex if nested. Note that
1157 * this lock may be held for long periods of time when
1158 * talking to hw - so only take it when talking to hw!
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001159 */
1160 struct mutex hw_lock;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001161};
1162
Daniel Vetter1a240d42012-11-29 22:18:51 +01001163/* defined intel_pm.c */
1164extern spinlock_t mchdev_lock;
1165
Daniel Vetterc85aa882012-11-02 19:55:03 +01001166struct intel_ilk_power_mgmt {
1167 u8 cur_delay;
1168 u8 min_delay;
1169 u8 max_delay;
1170 u8 fmax;
1171 u8 fstart;
1172
1173 u64 last_count1;
1174 unsigned long last_time1;
1175 unsigned long chipset_power;
1176 u64 last_count2;
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001177 u64 last_time2;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001178 unsigned long gfx_power;
1179 u8 corr;
1180
1181 int c_m;
1182 int r_t;
1183};
1184
Imre Deakc6cb5822014-03-04 19:22:55 +02001185struct drm_i915_private;
1186struct i915_power_well;
1187
1188struct i915_power_well_ops {
1189 /*
1190 * Synchronize the well's hw state to match the current sw state, for
1191 * example enable/disable it based on the current refcount. Called
1192 * during driver init and resume time, possibly after first calling
1193 * the enable/disable handlers.
1194 */
1195 void (*sync_hw)(struct drm_i915_private *dev_priv,
1196 struct i915_power_well *power_well);
1197 /*
1198 * Enable the well and resources that depend on it (for example
1199 * interrupts located on the well). Called after the 0->1 refcount
1200 * transition.
1201 */
1202 void (*enable)(struct drm_i915_private *dev_priv,
1203 struct i915_power_well *power_well);
1204 /*
1205 * Disable the well and resources that depend on it. Called after
1206 * the 1->0 refcount transition.
1207 */
1208 void (*disable)(struct drm_i915_private *dev_priv,
1209 struct i915_power_well *power_well);
1210 /* Returns the hw enabled state. */
1211 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1212 struct i915_power_well *power_well);
1213};
1214
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001215/* Power well structure for haswell */
1216struct i915_power_well {
Imre Deakc1ca7272013-11-25 17:15:29 +02001217 const char *name;
Imre Deak6f3ef5d2013-11-25 17:15:30 +02001218 bool always_on;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001219 /* power well enable/disable usage count */
1220 int count;
Imre Deakbfafe932014-06-05 20:31:47 +03001221 /* cached hw enabled state */
1222 bool hw_enabled;
Imre Deakc1ca7272013-11-25 17:15:29 +02001223 unsigned long domains;
Imre Deak77961eb2014-03-05 16:20:56 +02001224 unsigned long data;
Imre Deakc6cb5822014-03-04 19:22:55 +02001225 const struct i915_power_well_ops *ops;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001226};
1227
Imre Deak83c00f52013-10-25 17:36:47 +03001228struct i915_power_domains {
Imre Deakbaa70702013-10-25 17:36:48 +03001229 /*
1230 * Power wells needed for initialization at driver init and suspend
1231 * time are on. They are kept on until after the first modeset.
1232 */
1233 bool init_power_on;
Imre Deak0d116a22014-04-25 13:19:05 +03001234 bool initializing;
Imre Deakc1ca7272013-11-25 17:15:29 +02001235 int power_well_count;
Imre Deakbaa70702013-10-25 17:36:48 +03001236
Imre Deak83c00f52013-10-25 17:36:47 +03001237 struct mutex lock;
Imre Deak1da51582013-11-25 17:15:35 +02001238 int domain_use_count[POWER_DOMAIN_NUM];
Imre Deakc1ca7272013-11-25 17:15:29 +02001239 struct i915_power_well *power_wells;
Imre Deak83c00f52013-10-25 17:36:47 +03001240};
1241
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001242#define MAX_L3_SLICES 2
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001243struct intel_l3_parity {
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001244 u32 *remap_info[MAX_L3_SLICES];
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001245 struct work_struct error_work;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001246 int which_slice;
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001247};
1248
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001249struct i915_gem_mm {
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001250 /** Memory allocator for GTT stolen memory */
1251 struct drm_mm stolen;
Paulo Zanoni92e97d22015-07-02 19:25:09 -03001252 /** Protects the usage of the GTT stolen memory allocator. This is
1253 * always the inner lock when overlapping with struct_mutex. */
1254 struct mutex stolen_lock;
1255
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001256 /** List of all objects in gtt_space. Used to restore gtt
1257 * mappings on resume */
1258 struct list_head bound_list;
1259 /**
1260 * List of objects which are not bound to the GTT (thus
1261 * are idle and not used by the GPU) but still have
1262 * (presumably uncached) pages still attached.
1263 */
1264 struct list_head unbound_list;
1265
1266 /** Usable portion of the GTT for GEM */
1267 unsigned long stolen_base; /* limited to low memory (32-bit) */
1268
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001269 /** PPGTT used for aliasing the PPGTT with the GTT */
1270 struct i915_hw_ppgtt *aliasing_ppgtt;
1271
Chris Wilson2cfcd322014-05-20 08:28:43 +01001272 struct notifier_block oom_notifier;
Chris Wilsonceabbba52014-03-25 13:23:04 +00001273 struct shrinker shrinker;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001274 bool shrinker_no_lock_stealing;
1275
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001276 /** LRU list of objects with fence regs on them. */
1277 struct list_head fence_list;
1278
1279 /**
1280 * We leave the user IRQ off as much as possible,
1281 * but this means that requests will finish and never
1282 * be retired once the system goes idle. Set a timer to
1283 * fire periodically while the ring is running. When it
1284 * fires, go retire requests.
1285 */
1286 struct delayed_work retire_work;
1287
1288 /**
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001289 * When we detect an idle GPU, we want to turn on
1290 * powersaving features. So once we see that there
1291 * are no more requests outstanding and no more
1292 * arrive within a small period of time, we fire
1293 * off the idle_work.
1294 */
1295 struct delayed_work idle_work;
1296
1297 /**
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001298 * Are we in a non-interruptible section of code like
1299 * modesetting?
1300 */
1301 bool interruptible;
1302
Chris Wilsonf62a0072014-02-21 17:55:39 +00001303 /**
1304 * Is the GPU currently considered idle, or busy executing userspace
1305 * requests? Whilst idle, we attempt to power down the hardware and
1306 * display clocks. In order to reduce the effect on performance, there
1307 * is a slight delay before we do so.
1308 */
1309 bool busy;
1310
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001311 /* the indicator for dispatch video commands on two BSD rings */
1312 int bsd_ring_dispatch_index;
1313
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001314 /** Bit 6 swizzling required for X tiling */
1315 uint32_t bit_6_swizzle_x;
1316 /** Bit 6 swizzling required for Y tiling */
1317 uint32_t bit_6_swizzle_y;
1318
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001319 /* accounting, useful for userland debugging */
Daniel Vetterc20e8352013-07-24 22:40:23 +02001320 spinlock_t object_stat_lock;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001321 size_t object_memory;
1322 u32 object_count;
1323};
1324
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001325struct drm_i915_error_state_buf {
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01001326 struct drm_i915_private *i915;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001327 unsigned bytes;
1328 unsigned size;
1329 int err;
1330 u8 *buf;
1331 loff_t start;
1332 loff_t pos;
1333};
1334
Mika Kuoppalafc16b482013-06-06 15:18:39 +03001335struct i915_error_state_file_priv {
1336 struct drm_device *dev;
1337 struct drm_i915_error_state *error;
1338};
1339
Daniel Vetter99584db2012-11-14 17:14:04 +01001340struct i915_gpu_error {
1341 /* For hangcheck timer */
1342#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1343#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03001344 /* Hang gpu twice in this window and your context gets banned */
1345#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1346
Chris Wilson737b1502015-01-26 18:03:03 +02001347 struct workqueue_struct *hangcheck_wq;
1348 struct delayed_work hangcheck_work;
Daniel Vetter99584db2012-11-14 17:14:04 +01001349
1350 /* For reset and error_state handling. */
1351 spinlock_t lock;
1352 /* Protected by the above dev->gpu_error.lock. */
1353 struct drm_i915_error_state *first_error;
Chris Wilson094f9a52013-09-25 17:34:55 +01001354
1355 unsigned long missed_irq_rings;
1356
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001357 /**
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001358 * State variable controlling the reset flow and count
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001359 *
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001360 * This is a counter which gets incremented when reset is triggered,
1361 * and again when reset has been handled. So odd values (lowest bit set)
1362 * means that reset is in progress and even values that
1363 * (reset_counter >> 1):th reset was successfully completed.
1364 *
1365 * If reset is not completed succesfully, the I915_WEDGE bit is
1366 * set meaning that hardware is terminally sour and there is no
1367 * recovery. All waiters on the reset_queue will be woken when
1368 * that happens.
1369 *
1370 * This counter is used by the wait_seqno code to notice that reset
1371 * event happened and it needs to restart the entire ioctl (since most
1372 * likely the seqno it waited for won't ever signal anytime soon).
Daniel Vetterf69061b2012-12-06 09:01:42 +01001373 *
1374 * This is important for lock-free wait paths, where no contended lock
1375 * naturally enforces the correct ordering between the bail-out of the
1376 * waiter and the gpu reset work code.
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001377 */
1378 atomic_t reset_counter;
1379
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001380#define I915_RESET_IN_PROGRESS_FLAG 1
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001381#define I915_WEDGED (1 << 31)
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001382
1383 /**
1384 * Waitqueue to signal when the reset has completed. Used by clients
1385 * that wait for dev_priv->mm.wedged to settle.
1386 */
1387 wait_queue_head_t reset_queue;
Daniel Vetter33196de2012-11-14 17:14:05 +01001388
Mika Kuoppala88b4aa82014-03-28 18:18:18 +02001389 /* Userspace knobs for gpu hang simulation;
1390 * combines both a ring mask, and extra flags
1391 */
1392 u32 stop_rings;
1393#define I915_STOP_RING_ALLOW_BAN (1 << 31)
1394#define I915_STOP_RING_ALLOW_WARN (1 << 30)
Chris Wilson094f9a52013-09-25 17:34:55 +01001395
1396 /* For missed irq/seqno simulation. */
1397 unsigned int test_irq_rings;
McAulay, Alistair6689c162014-08-15 18:51:35 +01001398
1399 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1400 bool reload_in_reset;
Daniel Vetter99584db2012-11-14 17:14:04 +01001401};
1402
Zhang Ruib8efb172013-02-05 15:41:53 +08001403enum modeset_restore {
1404 MODESET_ON_LID_OPEN,
1405 MODESET_DONE,
1406 MODESET_SUSPENDED,
1407};
1408
Paulo Zanoni6acab152013-09-12 17:06:24 -03001409struct ddi_vbt_port_info {
Damien Lespiauce4dd492014-08-01 11:07:54 +01001410 /*
1411 * This is an index in the HDMI/DVI DDI buffer translation table.
1412 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1413 * populate this field.
1414 */
1415#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
Paulo Zanoni6acab152013-09-12 17:06:24 -03001416 uint8_t hdmi_level_shift;
Paulo Zanoni311a2092013-09-12 17:12:18 -03001417
1418 uint8_t supports_dvi:1;
1419 uint8_t supports_hdmi:1;
1420 uint8_t supports_dp:1;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001421};
1422
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001423enum psr_lines_to_wait {
1424 PSR_0_LINES_TO_WAIT = 0,
1425 PSR_1_LINE_TO_WAIT,
1426 PSR_4_LINES_TO_WAIT,
1427 PSR_8_LINES_TO_WAIT
Pradeep Bhat83a72802014-03-28 10:14:57 +05301428};
1429
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001430struct intel_vbt_data {
1431 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1432 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1433
1434 /* Feature bits */
1435 unsigned int int_tv_support:1;
1436 unsigned int lvds_dither:1;
1437 unsigned int lvds_vbt:1;
1438 unsigned int int_crt_support:1;
1439 unsigned int lvds_use_ssc:1;
1440 unsigned int display_clock_mode:1;
1441 unsigned int fdi_rx_polarity_inverted:1;
Shobhit Kumar3e6bd012014-05-27 19:33:59 +05301442 unsigned int has_mipi:1;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001443 int lvds_ssc_freq;
1444 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1445
Pradeep Bhat83a72802014-03-28 10:14:57 +05301446 enum drrs_support_type drrs_type;
1447
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001448 /* eDP */
1449 int edp_rate;
1450 int edp_lanes;
1451 int edp_preemphasis;
1452 int edp_vswing;
1453 bool edp_initialized;
1454 bool edp_support;
1455 int edp_bpp;
1456 struct edp_power_seq edp_pps;
1457
Jani Nikulaf00076d2013-12-14 20:38:29 -02001458 struct {
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001459 bool full_link;
1460 bool require_aux_wakeup;
1461 int idle_frames;
1462 enum psr_lines_to_wait lines_to_wait;
1463 int tp1_wakeup_time;
1464 int tp2_tp3_wakeup_time;
1465 } psr;
1466
1467 struct {
Jani Nikulaf00076d2013-12-14 20:38:29 -02001468 u16 pwm_freq_hz;
Jani Nikula39fbc9c2014-04-09 11:22:06 +03001469 bool present;
Jani Nikulaf00076d2013-12-14 20:38:29 -02001470 bool active_low_pwm;
Jani Nikula1de60682014-06-24 18:27:39 +03001471 u8 min_brightness; /* min_brightness/255 of max */
Jani Nikulaf00076d2013-12-14 20:38:29 -02001472 } backlight;
1473
Shobhit Kumard17c5442013-08-27 15:12:25 +03001474 /* MIPI DSI */
1475 struct {
Shobhit Kumar3e6bd012014-05-27 19:33:59 +05301476 u16 port;
Shobhit Kumard17c5442013-08-27 15:12:25 +03001477 u16 panel_id;
Shobhit Kumard3b542f2014-04-14 11:00:34 +05301478 struct mipi_config *config;
1479 struct mipi_pps_data *pps;
1480 u8 seq_version;
1481 u32 size;
1482 u8 *data;
1483 u8 *sequence[MIPI_SEQ_MAX];
Shobhit Kumard17c5442013-08-27 15:12:25 +03001484 } dsi;
1485
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001486 int crt_ddc_pin;
1487
1488 int child_dev_num;
Paulo Zanoni768f69c2013-09-11 18:02:47 -03001489 union child_device_config *child_dev;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001490
1491 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001492};
1493
Ville Syrjälä77c122b2013-08-06 22:24:04 +03001494enum intel_ddb_partitioning {
1495 INTEL_DDB_PART_1_2,
1496 INTEL_DDB_PART_5_6, /* IVB+ */
1497};
1498
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03001499struct intel_wm_level {
1500 bool enable;
1501 uint32_t pri_val;
1502 uint32_t spr_val;
1503 uint32_t cur_val;
1504 uint32_t fbc_val;
1505};
1506
Imre Deak820c1982013-12-17 14:46:36 +02001507struct ilk_wm_values {
Ville Syrjälä609cede2013-10-09 19:18:03 +03001508 uint32_t wm_pipe[3];
1509 uint32_t wm_lp[3];
1510 uint32_t wm_lp_spr[3];
1511 uint32_t wm_linetime[3];
1512 bool enable_fbc_wm;
1513 enum intel_ddb_partitioning partitioning;
1514};
1515
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001516struct vlv_pipe_wm {
1517 uint16_t primary;
1518 uint16_t sprite[2];
1519 uint8_t cursor;
1520};
1521
1522struct vlv_sr_wm {
1523 uint16_t plane;
1524 uint8_t cursor;
1525};
1526
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001527struct vlv_wm_values {
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001528 struct vlv_pipe_wm pipe[3];
1529 struct vlv_sr_wm sr;
Ville Syrjäläae801522015-03-05 21:19:49 +02001530 struct {
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001531 uint8_t cursor;
1532 uint8_t sprite[2];
1533 uint8_t primary;
1534 } ddl[3];
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03001535 uint8_t level;
1536 bool cxsr;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001537};
1538
Damien Lespiauc1939242014-11-04 17:06:41 +00001539struct skl_ddb_entry {
Damien Lespiau16160e32014-11-04 17:06:53 +00001540 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
Damien Lespiauc1939242014-11-04 17:06:41 +00001541};
1542
1543static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1544{
Damien Lespiau16160e32014-11-04 17:06:53 +00001545 return entry->end - entry->start;
Damien Lespiauc1939242014-11-04 17:06:41 +00001546}
1547
Damien Lespiau08db6652014-11-04 17:06:52 +00001548static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1549 const struct skl_ddb_entry *e2)
1550{
1551 if (e1->start == e2->start && e1->end == e2->end)
1552 return true;
1553
1554 return false;
1555}
1556
Damien Lespiauc1939242014-11-04 17:06:41 +00001557struct skl_ddb_allocation {
Damien Lespiau34bb56a2014-11-04 17:07:01 +00001558 struct skl_ddb_entry pipe[I915_MAX_PIPES];
Chandra Konduru2cd601c2015-04-27 15:47:37 -07001559 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1560 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */
Damien Lespiauc1939242014-11-04 17:06:41 +00001561 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1562};
1563
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001564struct skl_wm_values {
1565 bool dirty[I915_MAX_PIPES];
Damien Lespiauc1939242014-11-04 17:06:41 +00001566 struct skl_ddb_allocation ddb;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001567 uint32_t wm_linetime[I915_MAX_PIPES];
1568 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1569 uint32_t cursor[I915_MAX_PIPES][8];
1570 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1571 uint32_t cursor_trans[I915_MAX_PIPES];
1572};
1573
1574struct skl_wm_level {
1575 bool plane_en[I915_MAX_PLANES];
Damien Lespiaub99f58d2014-11-04 17:06:56 +00001576 bool cursor_en;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001577 uint16_t plane_res_b[I915_MAX_PLANES];
1578 uint8_t plane_res_l[I915_MAX_PLANES];
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001579 uint16_t cursor_res_b;
1580 uint8_t cursor_res_l;
1581};
1582
Paulo Zanonic67a4702013-08-19 13:18:09 -03001583/*
Paulo Zanoni765dab672014-03-07 20:08:18 -03001584 * This struct helps tracking the state needed for runtime PM, which puts the
1585 * device in PCI D3 state. Notice that when this happens, nothing on the
1586 * graphics device works, even register access, so we don't get interrupts nor
1587 * anything else.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001588 *
Paulo Zanoni765dab672014-03-07 20:08:18 -03001589 * Every piece of our code that needs to actually touch the hardware needs to
1590 * either call intel_runtime_pm_get or call intel_display_power_get with the
1591 * appropriate power domain.
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001592 *
Paulo Zanoni765dab672014-03-07 20:08:18 -03001593 * Our driver uses the autosuspend delay feature, which means we'll only really
1594 * suspend if we stay with zero refcount for a certain amount of time. The
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001595 * default value is currently very conservative (see intel_runtime_pm_enable), but
Paulo Zanoni765dab672014-03-07 20:08:18 -03001596 * it can be changed with the standard runtime PM files from sysfs.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001597 *
1598 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1599 * goes back to false exactly before we reenable the IRQs. We use this variable
1600 * to check if someone is trying to enable/disable IRQs while they're supposed
1601 * to be disabled. This shouldn't happen and we'll print some error messages in
Paulo Zanoni730488b2014-03-07 20:12:32 -03001602 * case it happens.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001603 *
Paulo Zanoni765dab672014-03-07 20:08:18 -03001604 * For more, read the Documentation/power/runtime_pm.txt.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001605 */
Paulo Zanoni5d584b22014-03-07 20:08:15 -03001606struct i915_runtime_pm {
1607 bool suspended;
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02001608 bool irqs_enabled;
Paulo Zanonic67a4702013-08-19 13:18:09 -03001609};
1610
Daniel Vetter926321d2013-10-16 13:30:34 +02001611enum intel_pipe_crc_source {
1612 INTEL_PIPE_CRC_SOURCE_NONE,
1613 INTEL_PIPE_CRC_SOURCE_PLANE1,
1614 INTEL_PIPE_CRC_SOURCE_PLANE2,
1615 INTEL_PIPE_CRC_SOURCE_PF,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001616 INTEL_PIPE_CRC_SOURCE_PIPE,
Daniel Vetter3d099a02013-10-16 22:55:58 +02001617 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1618 INTEL_PIPE_CRC_SOURCE_TV,
1619 INTEL_PIPE_CRC_SOURCE_DP_B,
1620 INTEL_PIPE_CRC_SOURCE_DP_C,
1621 INTEL_PIPE_CRC_SOURCE_DP_D,
Daniel Vetter46a19182013-11-01 10:50:20 +01001622 INTEL_PIPE_CRC_SOURCE_AUTO,
Daniel Vetter926321d2013-10-16 13:30:34 +02001623 INTEL_PIPE_CRC_SOURCE_MAX,
1624};
1625
Shuang He8bf1e9f2013-10-15 18:55:27 +01001626struct intel_pipe_crc_entry {
Damien Lespiauac2300d2013-10-15 18:55:30 +01001627 uint32_t frame;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001628 uint32_t crc[5];
1629};
1630
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001631#define INTEL_PIPE_CRC_ENTRIES_NR 128
Shuang He8bf1e9f2013-10-15 18:55:27 +01001632struct intel_pipe_crc {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001633 spinlock_t lock;
1634 bool opened; /* exclusive access to the result file */
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01001635 struct intel_pipe_crc_entry *entries;
Daniel Vetter926321d2013-10-16 13:30:34 +02001636 enum intel_pipe_crc_source source;
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001637 int head, tail;
Damien Lespiau07144422013-10-15 18:55:40 +01001638 wait_queue_head_t wq;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001639};
1640
Daniel Vetterf99d7062014-06-19 16:01:59 +02001641struct i915_frontbuffer_tracking {
1642 struct mutex lock;
1643
1644 /*
1645 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1646 * scheduled flips.
1647 */
1648 unsigned busy_bits;
1649 unsigned flip_bits;
1650};
1651
Mika Kuoppala72253422014-10-07 17:21:26 +03001652struct i915_wa_reg {
1653 u32 addr;
1654 u32 value;
1655 /* bitmask representing WA bits */
1656 u32 mask;
1657};
1658
1659#define I915_MAX_WA_REGS 16
1660
1661struct i915_workarounds {
1662 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1663 u32 count;
1664};
1665
Yu Zhangcf9d2892015-02-10 19:05:47 +08001666struct i915_virtual_gpu {
1667 bool active;
1668};
1669
John Harrison5f19e2b2015-05-29 17:43:27 +01001670struct i915_execbuffer_params {
1671 struct drm_device *dev;
1672 struct drm_file *file;
1673 uint32_t dispatch_flags;
1674 uint32_t args_batch_start_offset;
1675 uint32_t batch_obj_vm_offset;
1676 struct intel_engine_cs *ring;
1677 struct drm_i915_gem_object *batch_obj;
1678 struct intel_context *ctx;
John Harrison6a6ae792015-05-29 17:43:30 +01001679 struct drm_i915_gem_request *request;
John Harrison5f19e2b2015-05-29 17:43:27 +01001680};
1681
Jani Nikula77fec552014-03-31 14:27:22 +03001682struct drm_i915_private {
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001683 struct drm_device *dev;
Chris Wilsonefab6d82015-04-07 16:20:57 +01001684 struct kmem_cache *objects;
Chris Wilsone20d2ab2015-04-07 16:20:58 +01001685 struct kmem_cache *vmas;
Chris Wilsonefab6d82015-04-07 16:20:57 +01001686 struct kmem_cache *requests;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001687
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001688 const struct intel_device_info info;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001689
1690 int relative_constants_mode;
1691
1692 void __iomem *regs;
1693
Chris Wilson907b28c2013-07-19 20:36:52 +01001694 struct intel_uncore uncore;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001695
Yu Zhangcf9d2892015-02-10 19:05:47 +08001696 struct i915_virtual_gpu vgpu;
1697
Daniel Vettereb805622015-05-04 14:58:44 +02001698 struct intel_csr csr;
1699
1700 /* Display CSR-related protection */
1701 struct mutex csr_lock;
1702
Jani Nikula5ea6e5e2015-04-01 10:55:04 +03001703 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
Daniel Vetter28c70f12012-12-01 13:53:45 +01001704
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001705 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1706 * controller on different i2c buses. */
1707 struct mutex gmbus_mutex;
1708
1709 /**
1710 * Base address of the gmbus and gpio block.
1711 */
1712 uint32_t gpio_mmio_base;
1713
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301714 /* MMIO base address for MIPI regs */
1715 uint32_t mipi_mmio_base;
1716
Daniel Vetter28c70f12012-12-01 13:53:45 +01001717 wait_queue_head_t gmbus_wait_queue;
1718
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001719 struct pci_dev *bridge_dev;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001720 struct intel_engine_cs ring[I915_NUM_RINGS];
Ben Widawsky3e789982014-06-30 09:53:37 -07001721 struct drm_i915_gem_object *semaphore_obj;
Mika Kuoppalaf72b3432012-12-10 15:41:48 +02001722 uint32_t last_seqno, next_seqno;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001723
Daniel Vetterba8286f2014-09-11 07:43:25 +02001724 struct drm_dma_handle *status_page_dmah;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001725 struct resource mch_res;
1726
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001727 /* protects the irq masks */
1728 spinlock_t irq_lock;
1729
Sourab Gupta84c33a62014-06-02 16:47:17 +05301730 /* protects the mmio flip data */
1731 spinlock_t mmio_flip_lock;
1732
Imre Deakf8b79e52014-03-04 19:23:07 +02001733 bool display_irqs_enabled;
1734
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001735 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1736 struct pm_qos_request pm_qos;
1737
Ville Syrjäläa5805162015-05-26 20:42:30 +03001738 /* Sideband mailbox protection */
1739 struct mutex sb_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001740
1741 /** Cached value of IMR to avoid reads in updating the bitfield */
Ben Widawskyabd58f02013-11-02 21:07:09 -07001742 union {
1743 u32 irq_mask;
1744 u32 de_irq_mask[I915_MAX_PIPES];
1745 };
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001746 u32 gt_irq_mask;
Paulo Zanoni605cd252013-08-06 18:57:15 -03001747 u32 pm_irq_mask;
Deepak Sa6706b42014-03-15 20:23:22 +05301748 u32 pm_rps_events;
Imre Deak91d181d2014-02-10 18:42:49 +02001749 u32 pipestat_irq_mask[I915_MAX_PIPES];
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001750
Jani Nikula5fcece82015-05-27 15:03:42 +03001751 struct i915_hotplug hotplug;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07001752 struct i915_fbc fbc;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05301753 struct i915_drrs drrs;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001754 struct intel_opregion opregion;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001755 struct intel_vbt_data vbt;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001756
Jesse Barnesd9ceb812014-10-09 12:57:43 -07001757 bool preserve_bios_swizzle;
1758
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001759 /* overlay */
1760 struct intel_overlay *overlay;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001761
Jani Nikula58c68772013-11-08 16:48:54 +02001762 /* backlight registers and fields in struct intel_panel */
Daniel Vetter07f11d42014-09-15 14:35:09 +02001763 struct mutex backlight_lock;
Jani Nikula31ad8ec2013-04-02 15:48:09 +03001764
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001765 /* LVDS info */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001766 bool no_aux_handshake;
1767
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001768 /* protects panel power sequencer state */
1769 struct mutex pps_mutex;
1770
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001771 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1772 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1773 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1774
1775 unsigned int fsb_freq, mem_freq, is_ddr3;
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01001776 unsigned int skl_boot_cdclk;
Ville Syrjälä44913152015-06-03 15:45:10 +03001777 unsigned int cdclk_freq, max_cdclk_freq;
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03001778 unsigned int hpll_freq;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001779
Daniel Vetter645416f2013-09-02 16:22:25 +02001780 /**
1781 * wq - Driver workqueue for GEM.
1782 *
1783 * NOTE: Work items scheduled here are not allowed to grab any modeset
1784 * locks, for otherwise the flushing done in the pageflip code will
1785 * result in deadlocks.
1786 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001787 struct workqueue_struct *wq;
1788
1789 /* Display functions */
1790 struct drm_i915_display_funcs display;
1791
1792 /* PCH chipset type */
1793 enum intel_pch pch_type;
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001794 unsigned short pch_id;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001795
1796 unsigned long quirks;
1797
Zhang Ruib8efb172013-02-05 15:41:53 +08001798 enum modeset_restore modeset_restore;
1799 struct mutex modeset_restore_lock;
Eric Anholt673a3942008-07-30 12:06:12 -07001800
Ben Widawskya7bbbd62013-07-16 16:50:07 -07001801 struct list_head vm_list; /* Global list of all address spaces */
Ben Widawsky0260c422014-03-22 22:47:21 -07001802 struct i915_gtt gtt; /* VM representing the global address space */
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001803
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001804 struct i915_gem_mm mm;
Chris Wilsonad46cb52014-08-07 14:20:40 +01001805 DECLARE_HASHTABLE(mm_structs, 7);
1806 struct mutex mm_lock;
Daniel Vetter87813422012-05-02 11:49:32 +02001807
Daniel Vetter87813422012-05-02 11:49:32 +02001808 /* Kernel Modesetting */
1809
yakui_zhao9b9d1722009-05-31 17:17:17 +08001810 struct sdvo_device_mapping sdvo_mappings[2];
Jesse Barnes652c3932009-08-17 13:31:43 -07001811
Damien Lespiau76c4ac02014-02-07 19:12:52 +00001812 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1813 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001814 wait_queue_head_t pending_flip_queue;
1815
Daniel Vetterc4597872013-10-21 21:04:07 +02001816#ifdef CONFIG_DEBUG_FS
1817 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1818#endif
1819
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001820 int num_shared_dpll;
1821 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001822 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001823
Mika Kuoppala72253422014-10-07 17:21:26 +03001824 struct i915_workarounds workarounds;
Arun Siluvery888b5992014-08-26 14:44:51 +01001825
Jesse Barnes652c3932009-08-17 13:31:43 -07001826 /* Reclocking support */
1827 bool render_reclock_avail;
Daniel Vetterf99d7062014-06-19 16:01:59 +02001828
1829 struct i915_frontbuffer_tracking fb_tracking;
1830
Jesse Barnes652c3932009-08-17 13:31:43 -07001831 u16 orig_clock;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001832
Zhenyu Wangc48044112009-12-17 14:48:43 +08001833 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001834
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001835 struct intel_l3_parity l3_parity;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001836
Ben Widawsky59124502013-07-04 11:02:05 -07001837 /* Cannot be determined by PCIID. You must always read a register. */
1838 size_t ellc_size;
1839
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001840 /* gen6+ rps state */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001841 struct intel_gen6_power_mgmt rps;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001842
Daniel Vetter20e4d402012-08-08 23:35:39 +02001843 /* ilk-only ips/rps state. Everything in here is protected by the global
1844 * mchdev_lock in intel_pm.c */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001845 struct intel_ilk_power_mgmt ips;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001846
Imre Deak83c00f52013-10-25 17:36:47 +03001847 struct i915_power_domains power_domains;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001848
Rodrigo Vivia031d702013-10-03 16:15:06 -03001849 struct i915_psr psr;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001850
Daniel Vetter99584db2012-11-14 17:14:04 +01001851 struct i915_gpu_error gpu_error;
Chris Wilsonae681d92010-10-01 14:57:56 +01001852
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001853 struct drm_i915_gem_object *vlv_pctx;
1854
Daniel Vetter4520f532013-10-09 09:18:51 +02001855#ifdef CONFIG_DRM_I915_FBDEV
Dave Airlie8be48d92010-03-30 05:34:14 +00001856 /* list of fbdev register on this device */
1857 struct intel_fbdev *fbdev;
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001858 struct work_struct fbdev_suspend_work;
Daniel Vetter4520f532013-10-09 09:18:51 +02001859#endif
Chris Wilsone953fd72011-02-21 22:23:52 +00001860
1861 struct drm_property *broadcast_rgb_property;
Chris Wilson3f43c482011-05-12 22:17:24 +01001862 struct drm_property *force_audio_property;
Ben Widawskye3689192012-05-25 16:56:22 -07001863
Imre Deak58fddc22015-01-08 17:54:14 +02001864 /* hda/i915 audio component */
1865 bool audio_component_registered;
1866
Ben Widawsky254f9652012-06-04 14:42:42 -07001867 uint32_t hw_context_size;
Ben Widawskya33afea2013-09-17 21:12:45 -07001868 struct list_head context_list;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001869
Damien Lespiau3e683202012-12-11 18:48:29 +00001870 u32 fdi_rx_config;
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02001871
Ville Syrjälä70722462015-04-10 18:21:28 +03001872 u32 chv_phy_control;
1873
Daniel Vetter842f1c82014-03-10 10:01:44 +01001874 u32 suspend_count;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001875 struct i915_suspend_saved_registers regfile;
Imre Deakddeea5b2014-05-05 15:19:56 +03001876 struct vlv_s0ix_state vlv_s0ix_state;
Daniel Vetter231f42a2012-11-02 19:55:05 +01001877
Ville Syrjälä53615a52013-08-01 16:18:50 +03001878 struct {
1879 /*
1880 * Raw watermark latency values:
1881 * in 0.1us units for WM0,
1882 * in 0.5us units for WM1+.
1883 */
1884 /* primary */
1885 uint16_t pri_latency[5];
1886 /* sprite */
1887 uint16_t spr_latency[5];
1888 /* cursor */
1889 uint16_t cur_latency[5];
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001890 /*
1891 * Raw watermark memory latency values
1892 * for SKL for all 8 levels
1893 * in 1us units.
1894 */
1895 uint16_t skl_latency[8];
Ville Syrjälä609cede2013-10-09 19:18:03 +03001896
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001897 /*
1898 * The skl_wm_values structure is a bit too big for stack
1899 * allocation, so we keep the staging struct where we store
1900 * intermediate results here instead.
1901 */
1902 struct skl_wm_values skl_results;
1903
Ville Syrjälä609cede2013-10-09 19:18:03 +03001904 /* current hardware state */
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001905 union {
1906 struct ilk_wm_values hw;
1907 struct skl_wm_values skl_hw;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001908 struct vlv_wm_values vlv;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001909 };
Ville Syrjälä53615a52013-08-01 16:18:50 +03001910 } wm;
1911
Paulo Zanoni8a187452013-12-06 20:32:13 -02001912 struct i915_runtime_pm pm;
1913
Oscar Mateoa83014d2014-07-24 17:04:21 +01001914 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1915 struct {
John Harrison5f19e2b2015-05-29 17:43:27 +01001916 int (*execbuf_submit)(struct i915_execbuffer_params *params,
John Harrisonf3dc74c2015-03-19 12:30:06 +00001917 struct drm_i915_gem_execbuffer2 *args,
John Harrison5f19e2b2015-05-29 17:43:27 +01001918 struct list_head *vmas);
Oscar Mateoa83014d2014-07-24 17:04:21 +01001919 int (*init_rings)(struct drm_device *dev);
1920 void (*cleanup_ring)(struct intel_engine_cs *ring);
1921 void (*stop_ring)(struct intel_engine_cs *ring);
1922 } gt;
1923
Sonika Jindal9e458032015-05-06 17:35:48 +05301924 bool edp_low_vswing;
1925
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001926 /*
1927 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1928 * will be rejected. Instead look for a better place.
1929 */
Jani Nikula77fec552014-03-31 14:27:22 +03001930};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001931
Chris Wilson2c1792a2013-08-01 18:39:55 +01001932static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1933{
1934 return dev->dev_private;
1935}
1936
Imre Deak888d0d42015-01-08 17:54:13 +02001937static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1938{
1939 return to_i915(dev_get_drvdata(dev));
1940}
1941
Chris Wilsonb4519512012-05-11 14:29:30 +01001942/* Iterate over initialised rings */
1943#define for_each_ring(ring__, dev_priv__, i__) \
1944 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1945 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1946
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001947enum hdmi_force_audio {
1948 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1949 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1950 HDMI_AUDIO_AUTO, /* trust EDID */
1951 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1952};
1953
Daniel Vetter190d6cd2013-07-04 13:06:28 +02001954#define I915_GTT_OFFSET_NONE ((u32)-1)
Chris Wilsoned2f3452012-11-15 11:32:19 +00001955
Chris Wilson37e680a2012-06-07 15:38:42 +01001956struct drm_i915_gem_object_ops {
1957 /* Interface between the GEM object and its backing storage.
1958 * get_pages() is called once prior to the use of the associated set
1959 * of pages before to binding them into the GTT, and put_pages() is
1960 * called after we no longer need them. As we expect there to be
1961 * associated cost with migrating pages between the backing storage
1962 * and making them available for the GPU (e.g. clflush), we may hold
1963 * onto the pages after they are no longer referenced by the GPU
1964 * in case they may be used again shortly (for example migrating the
1965 * pages to a different memory domain within the GTT). put_pages()
1966 * will therefore most likely be called when the object itself is
1967 * being released or under memory pressure (where we attempt to
1968 * reap pages for the shrinker).
1969 */
1970 int (*get_pages)(struct drm_i915_gem_object *);
1971 void (*put_pages)(struct drm_i915_gem_object *);
Chris Wilson5cc9ed42014-05-16 14:22:37 +01001972 int (*dmabuf_export)(struct drm_i915_gem_object *);
1973 void (*release)(struct drm_i915_gem_object *);
Chris Wilson37e680a2012-06-07 15:38:42 +01001974};
1975
Daniel Vettera071fa02014-06-18 23:28:09 +02001976/*
1977 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1978 * considered to be the frontbuffer for the given plane interface-vise. This
1979 * doesn't mean that the hw necessarily already scans it out, but that any
1980 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1981 *
1982 * We have one bit per pipe and per scanout plane type.
1983 */
1984#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1985#define INTEL_FRONTBUFFER_BITS \
1986 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1987#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1988 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1989#define INTEL_FRONTBUFFER_CURSOR(pipe) \
1990 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1991#define INTEL_FRONTBUFFER_SPRITE(pipe) \
1992 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1993#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1994 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
Daniel Vettercc365132014-06-18 13:59:13 +02001995#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1996 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
Daniel Vettera071fa02014-06-18 23:28:09 +02001997
Eric Anholt673a3942008-07-30 12:06:12 -07001998struct drm_i915_gem_object {
Daniel Vetterc397b902010-04-09 19:05:07 +00001999 struct drm_gem_object base;
Eric Anholt673a3942008-07-30 12:06:12 -07002000
Chris Wilson37e680a2012-06-07 15:38:42 +01002001 const struct drm_i915_gem_object_ops *ops;
2002
Ben Widawsky2f633152013-07-17 12:19:03 -07002003 /** List of VMAs backed by this object */
2004 struct list_head vma_list;
2005
Chris Wilsonc1ad11f2012-11-15 11:32:21 +00002006 /** Stolen memory for this object, instead of being backed by shmem. */
2007 struct drm_mm_node *stolen;
Ben Widawsky35c20a62013-05-31 11:28:48 -07002008 struct list_head global_list;
Eric Anholt673a3942008-07-30 12:06:12 -07002009
Chris Wilsonb4716182015-04-27 13:41:17 +01002010 struct list_head ring_list[I915_NUM_RINGS];
Ben Widawskyb25cb2f2013-08-14 11:38:33 +02002011 /** Used in execbuf to temporarily hold a ref */
2012 struct list_head obj_exec_link;
Eric Anholt673a3942008-07-30 12:06:12 -07002013
Chris Wilson8d9d5742015-04-07 16:20:38 +01002014 struct list_head batch_pool_link;
Brad Volkin493018d2014-12-11 12:13:08 -08002015
Eric Anholt673a3942008-07-30 12:06:12 -07002016 /**
Chris Wilson65ce3022012-07-20 12:41:02 +01002017 * This is set if the object is on the active lists (has pending
2018 * rendering and so a non-zero seqno), and is not set if it i s on
2019 * inactive (ready to be unbound) list.
Eric Anholt673a3942008-07-30 12:06:12 -07002020 */
Chris Wilsonb4716182015-04-27 13:41:17 +01002021 unsigned int active:I915_NUM_RINGS;
Eric Anholt673a3942008-07-30 12:06:12 -07002022
2023 /**
2024 * This is set if the object has been written to since last bound
2025 * to the GTT
2026 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002027 unsigned int dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02002028
2029 /**
2030 * Fence register bits (if any) for this object. Will be set
2031 * as needed when mapped into the GTT.
2032 * Protected by dev->struct_mutex.
Daniel Vetter778c3542010-05-13 11:49:44 +02002033 */
Daniel Vetter4b9de732011-10-09 21:52:02 +02002034 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
Daniel Vetter778c3542010-05-13 11:49:44 +02002035
2036 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02002037 * Advice: are the backing pages purgeable?
2038 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002039 unsigned int madv:2;
Daniel Vetter778c3542010-05-13 11:49:44 +02002040
2041 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02002042 * Current tiling mode for the object.
2043 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002044 unsigned int tiling_mode:2;
Chris Wilson5d82e3e2012-04-21 16:23:23 +01002045 /**
2046 * Whether the tiling parameters for the currently associated fence
2047 * register have changed. Note that for the purposes of tracking
2048 * tiling changes we also treat the unfenced register, the register
2049 * slot that the object occupies whilst it executes a fenced
2050 * command (such as BLT on gen2/3), as a "fence".
2051 */
2052 unsigned int fence_dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02002053
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002054 /**
Daniel Vetter75e9e912010-11-04 17:11:09 +01002055 * Is the object at the current location in the gtt mappable and
2056 * fenceable? Used to avoid costly recalculations.
2057 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002058 unsigned int map_and_fenceable:1;
Daniel Vetter75e9e912010-11-04 17:11:09 +01002059
2060 /**
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002061 * Whether the current gtt mapping needs to be mappable (and isn't just
2062 * mappable by accident). Track pin and fault separate for a more
2063 * accurate mappable working set.
2064 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002065 unsigned int fault_mappable:1;
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002066
Chris Wilsoncaea7472010-11-12 13:53:37 +00002067 /*
Akash Goel24f3a8c2014-06-17 10:59:42 +05302068 * Is the object to be mapped as read-only to the GPU
2069 * Only honoured if hardware has relevant pte bit
2070 */
2071 unsigned long gt_ro:1;
Chris Wilson651d7942013-08-08 14:41:10 +01002072 unsigned int cache_level:3;
Chris Wilson0f719792015-01-13 13:32:52 +00002073 unsigned int cache_dirty:1;
Chris Wilson93dfb402011-03-29 16:59:50 -07002074
Chris Wilson9da3da62012-06-01 15:20:22 +01002075 unsigned int has_dma_mapping:1;
Daniel Vetter7bddb012012-02-09 17:15:47 +01002076
Daniel Vettera071fa02014-06-18 23:28:09 +02002077 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2078
Tvrtko Ursulin8a0c39b2015-04-13 11:50:09 +01002079 unsigned int pin_display;
2080
Chris Wilson9da3da62012-06-01 15:20:22 +01002081 struct sg_table *pages;
Chris Wilsona5570172012-09-04 21:02:54 +01002082 int pages_pin_count;
Chris Wilsonee286372015-04-07 16:20:25 +01002083 struct get_page {
2084 struct scatterlist *sg;
2085 int last;
2086 } get_page;
Eric Anholt673a3942008-07-30 12:06:12 -07002087
Daniel Vetter1286ff72012-05-10 15:25:09 +02002088 /* prime dma-buf support */
Dave Airlie9a70cc22012-05-22 13:09:21 +01002089 void *dma_buf_vmapping;
2090 int vmapping_count;
2091
Chris Wilsonb4716182015-04-27 13:41:17 +01002092 /** Breadcrumb of last rendering to the buffer.
2093 * There can only be one writer, but we allow for multiple readers.
2094 * If there is a writer that necessarily implies that all other
2095 * read requests are complete - but we may only be lazily clearing
2096 * the read requests. A read request is naturally the most recent
2097 * request on a ring, so we may have two different write and read
2098 * requests on one ring where the write request is older than the
2099 * read request. This allows for the CPU to read from an active
2100 * buffer by only waiting for the write to complete.
2101 * */
2102 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
John Harrison97b2a6a2014-11-24 18:49:26 +00002103 struct drm_i915_gem_request *last_write_req;
Chris Wilsoncaea7472010-11-12 13:53:37 +00002104 /** Breadcrumb of last fenced GPU access to the buffer. */
John Harrison97b2a6a2014-11-24 18:49:26 +00002105 struct drm_i915_gem_request *last_fenced_req;
Eric Anholt673a3942008-07-30 12:06:12 -07002106
Daniel Vetter778c3542010-05-13 11:49:44 +02002107 /** Current tiling stride for the object, if it's tiled. */
Jesse Barnesde151cf2008-11-12 10:03:55 -08002108 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -07002109
Daniel Vetter80075d42013-10-09 21:23:52 +02002110 /** References from framebuffers, locks out tiling changes. */
2111 unsigned long framebuffer_references;
2112
Eric Anholt280b7132009-03-12 16:56:27 -07002113 /** Record of address bit 17 of each page at last unbind. */
Chris Wilsond312ec22010-06-06 15:40:22 +01002114 unsigned long *bit_17;
Eric Anholt280b7132009-03-12 16:56:27 -07002115
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002116 union {
Chris Wilson6a2c4232014-11-04 04:51:40 -08002117 /** for phy allocated objects */
2118 struct drm_dma_handle *phys_handle;
2119
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002120 struct i915_gem_userptr {
2121 uintptr_t ptr;
2122 unsigned read_only :1;
2123 unsigned workers :4;
2124#define I915_GEM_USERPTR_MAX_WORKERS 15
2125
Chris Wilsonad46cb52014-08-07 14:20:40 +01002126 struct i915_mm_struct *mm;
2127 struct i915_mmu_object *mmu_object;
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002128 struct work_struct *work;
2129 } userptr;
2130 };
2131};
Daniel Vetter62b8b212010-04-09 19:05:08 +00002132#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
Daniel Vetter23010e42010-03-08 13:35:02 +01002133
Daniel Vettera071fa02014-06-18 23:28:09 +02002134void i915_gem_track_fb(struct drm_i915_gem_object *old,
2135 struct drm_i915_gem_object *new,
2136 unsigned frontbuffer_bits);
2137
Eric Anholt673a3942008-07-30 12:06:12 -07002138/**
2139 * Request queue structure.
2140 *
2141 * The request queue allows us to note sequence numbers that have been emitted
2142 * and may be associated with active buffers to be retired.
2143 *
John Harrison97b2a6a2014-11-24 18:49:26 +00002144 * By keeping this list, we can avoid having to do questionable sequence
2145 * number comparisons on buffer last_read|write_seqno. It also allows an
2146 * emission time to be associated with the request for tracking how far ahead
2147 * of the GPU the submission is.
Nick Hoathb3a38992015-02-19 16:30:47 +00002148 *
2149 * The requests are reference counted, so upon creation they should have an
2150 * initial reference taken using kref_init
Eric Anholt673a3942008-07-30 12:06:12 -07002151 */
2152struct drm_i915_gem_request {
John Harrisonabfe2622014-11-24 18:49:24 +00002153 struct kref ref;
2154
Zou Nan hai852835f2010-05-21 09:08:56 +08002155 /** On Which ring this request was generated */
Chris Wilsonefab6d82015-04-07 16:20:57 +01002156 struct drm_i915_private *i915;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002157 struct intel_engine_cs *ring;
Zou Nan hai852835f2010-05-21 09:08:56 +08002158
Eric Anholt673a3942008-07-30 12:06:12 -07002159 /** GEM sequence number associated with this request. */
2160 uint32_t seqno;
2161
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002162 /** Position in the ringbuffer of the start of the request */
2163 u32 head;
2164
Nick Hoath72f95af2015-01-15 13:10:37 +00002165 /**
2166 * Position in the ringbuffer of the start of the postfix.
2167 * This is required to calculate the maximum available ringbuffer
2168 * space without overwriting the postfix.
2169 */
2170 u32 postfix;
2171
2172 /** Position in the ringbuffer of the end of the whole request */
Chris Wilsona71d8d92012-02-15 11:25:36 +00002173 u32 tail;
2174
Nick Hoathb3a38992015-02-19 16:30:47 +00002175 /**
Dave Airliea8c6ecb2015-03-09 19:58:30 +10002176 * Context and ring buffer related to this request
Nick Hoathb3a38992015-02-19 16:30:47 +00002177 * Contexts are refcounted, so when this request is associated with a
2178 * context, we must increment the context's refcount, to guarantee that
2179 * it persists while any request is linked to it. Requests themselves
2180 * are also refcounted, so the request will only be freed when the last
2181 * reference to it is dismissed, and the code in
2182 * i915_gem_request_free() will then decrement the refcount on the
2183 * context.
2184 */
Oscar Mateo273497e2014-05-22 14:13:37 +01002185 struct intel_context *ctx;
John Harrison98e1bd42015-02-13 11:48:12 +00002186 struct intel_ringbuffer *ringbuf;
Mika Kuoppala0e50e962013-05-02 16:48:08 +03002187
John Harrisondc4be60712015-05-29 17:43:39 +01002188 /** Batch buffer related to this request if any (used for
2189 error state dump only) */
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002190 struct drm_i915_gem_object *batch_obj;
2191
Eric Anholt673a3942008-07-30 12:06:12 -07002192 /** Time at which this request was emitted, in jiffies. */
2193 unsigned long emitted_jiffies;
2194
Eric Anholtb9624422009-06-03 07:27:35 +00002195 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -07002196 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +00002197
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002198 struct drm_i915_file_private *file_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00002199 /** file_priv list entry for this request */
2200 struct list_head client_list;
John Harrison67e29372014-12-05 13:49:35 +00002201
Mika Kuoppala071c92d2015-02-12 10:26:02 +02002202 /** process identifier submitting this request */
2203 struct pid *pid;
2204
Nick Hoath6d3d8272015-01-15 13:10:39 +00002205 /**
2206 * The ELSP only accepts two elements at a time, so we queue
2207 * context/tail pairs on a given queue (ring->execlist_queue) until the
2208 * hardware is available. The queue serves a double purpose: we also use
2209 * it to keep track of the up to 2 contexts currently in the hardware
2210 * (usually one in execution and the other queued up by the GPU): We
2211 * only remove elements from the head of the queue when the hardware
2212 * informs us that an element has been completed.
2213 *
2214 * All accesses to the queue are mediated by a spinlock
2215 * (ring->execlist_lock).
2216 */
2217
2218 /** Execlist link in the submission queue.*/
2219 struct list_head execlist_link;
2220
2221 /** Execlists no. of times this request has been sent to the ELSP */
2222 int elsp_submitted;
2223
Eric Anholt673a3942008-07-30 12:06:12 -07002224};
2225
John Harrison6689cb22015-03-19 12:30:08 +00002226int i915_gem_request_alloc(struct intel_engine_cs *ring,
John Harrison217e46b2015-05-29 17:43:29 +01002227 struct intel_context *ctx,
2228 struct drm_i915_gem_request **req_out);
John Harrison29b1b412015-06-18 13:10:09 +01002229void i915_gem_request_cancel(struct drm_i915_gem_request *req);
John Harrisonabfe2622014-11-24 18:49:24 +00002230void i915_gem_request_free(struct kref *req_ref);
John Harrisonfcfa423c2015-05-29 17:44:12 +01002231int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2232 struct drm_file *file);
John Harrisonabfe2622014-11-24 18:49:24 +00002233
John Harrisonb793a002014-11-24 18:49:25 +00002234static inline uint32_t
2235i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2236{
2237 return req ? req->seqno : 0;
2238}
2239
2240static inline struct intel_engine_cs *
2241i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2242{
2243 return req ? req->ring : NULL;
2244}
2245
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +01002246static inline struct drm_i915_gem_request *
John Harrisonabfe2622014-11-24 18:49:24 +00002247i915_gem_request_reference(struct drm_i915_gem_request *req)
2248{
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +01002249 if (req)
2250 kref_get(&req->ref);
2251 return req;
John Harrisonabfe2622014-11-24 18:49:24 +00002252}
2253
2254static inline void
2255i915_gem_request_unreference(struct drm_i915_gem_request *req)
2256{
Daniel Vetterf2458602014-11-26 10:26:05 +01002257 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
John Harrisonabfe2622014-11-24 18:49:24 +00002258 kref_put(&req->ref, i915_gem_request_free);
2259}
2260
Chris Wilson41037f92015-03-27 11:01:36 +00002261static inline void
2262i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2263{
Maarten Lankhorstb833bb62015-04-07 11:32:02 +02002264 struct drm_device *dev;
Chris Wilson41037f92015-03-27 11:01:36 +00002265
Maarten Lankhorstb833bb62015-04-07 11:32:02 +02002266 if (!req)
2267 return;
2268
2269 dev = req->ring->dev;
2270 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
Chris Wilson41037f92015-03-27 11:01:36 +00002271 mutex_unlock(&dev->struct_mutex);
Chris Wilson41037f92015-03-27 11:01:36 +00002272}
2273
John Harrisonabfe2622014-11-24 18:49:24 +00002274static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2275 struct drm_i915_gem_request *src)
2276{
2277 if (src)
2278 i915_gem_request_reference(src);
2279
2280 if (*pdst)
2281 i915_gem_request_unreference(*pdst);
2282
2283 *pdst = src;
2284}
2285
John Harrison1b5a4332014-11-24 18:49:42 +00002286/*
2287 * XXX: i915_gem_request_completed should be here but currently needs the
2288 * definition of i915_seqno_passed() which is below. It will be moved in
2289 * a later patch when the call to i915_seqno_passed() is obsoleted...
2290 */
2291
Brad Volkin351e3db2014-02-18 10:15:46 -08002292/*
2293 * A command that requires special handling by the command parser.
2294 */
2295struct drm_i915_cmd_descriptor {
2296 /*
2297 * Flags describing how the command parser processes the command.
2298 *
2299 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2300 * a length mask if not set
2301 * CMD_DESC_SKIP: The command is allowed but does not follow the
2302 * standard length encoding for the opcode range in
2303 * which it falls
2304 * CMD_DESC_REJECT: The command is never allowed
2305 * CMD_DESC_REGISTER: The command should be checked against the
2306 * register whitelist for the appropriate ring
2307 * CMD_DESC_MASTER: The command is allowed if the submitting process
2308 * is the DRM master
2309 */
2310 u32 flags;
2311#define CMD_DESC_FIXED (1<<0)
2312#define CMD_DESC_SKIP (1<<1)
2313#define CMD_DESC_REJECT (1<<2)
2314#define CMD_DESC_REGISTER (1<<3)
2315#define CMD_DESC_BITMASK (1<<4)
2316#define CMD_DESC_MASTER (1<<5)
2317
2318 /*
2319 * The command's unique identification bits and the bitmask to get them.
2320 * This isn't strictly the opcode field as defined in the spec and may
2321 * also include type, subtype, and/or subop fields.
2322 */
2323 struct {
2324 u32 value;
2325 u32 mask;
2326 } cmd;
2327
2328 /*
2329 * The command's length. The command is either fixed length (i.e. does
2330 * not include a length field) or has a length field mask. The flag
2331 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2332 * a length mask. All command entries in a command table must include
2333 * length information.
2334 */
2335 union {
2336 u32 fixed;
2337 u32 mask;
2338 } length;
2339
2340 /*
2341 * Describes where to find a register address in the command to check
2342 * against the ring's register whitelist. Only valid if flags has the
2343 * CMD_DESC_REGISTER bit set.
Francisco Jerez6a65c5b2015-05-29 16:44:13 +03002344 *
2345 * A non-zero step value implies that the command may access multiple
2346 * registers in sequence (e.g. LRI), in that case step gives the
2347 * distance in dwords between individual offset fields.
Brad Volkin351e3db2014-02-18 10:15:46 -08002348 */
2349 struct {
2350 u32 offset;
2351 u32 mask;
Francisco Jerez6a65c5b2015-05-29 16:44:13 +03002352 u32 step;
Brad Volkin351e3db2014-02-18 10:15:46 -08002353 } reg;
2354
2355#define MAX_CMD_DESC_BITMASKS 3
2356 /*
2357 * Describes command checks where a particular dword is masked and
2358 * compared against an expected value. If the command does not match
2359 * the expected value, the parser rejects it. Only valid if flags has
2360 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2361 * are valid.
Brad Volkind4d48032014-02-18 10:15:54 -08002362 *
2363 * If the check specifies a non-zero condition_mask then the parser
2364 * only performs the check when the bits specified by condition_mask
2365 * are non-zero.
Brad Volkin351e3db2014-02-18 10:15:46 -08002366 */
2367 struct {
2368 u32 offset;
2369 u32 mask;
2370 u32 expected;
Brad Volkind4d48032014-02-18 10:15:54 -08002371 u32 condition_offset;
2372 u32 condition_mask;
Brad Volkin351e3db2014-02-18 10:15:46 -08002373 } bits[MAX_CMD_DESC_BITMASKS];
2374};
2375
2376/*
2377 * A table of commands requiring special handling by the command parser.
2378 *
2379 * Each ring has an array of tables. Each table consists of an array of command
2380 * descriptors, which must be sorted with command opcodes in ascending order.
2381 */
2382struct drm_i915_cmd_table {
2383 const struct drm_i915_cmd_descriptor *table;
2384 int count;
2385};
2386
Chris Wilsondbbe9122014-08-09 19:18:43 +01002387/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
Chris Wilson7312e2d2014-08-13 12:14:12 +01002388#define __I915__(p) ({ \
2389 struct drm_i915_private *__p; \
2390 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2391 __p = (struct drm_i915_private *)p; \
2392 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2393 __p = to_i915((struct drm_device *)p); \
2394 else \
2395 BUILD_BUG(); \
2396 __p; \
2397})
Chris Wilsondbbe9122014-08-09 19:18:43 +01002398#define INTEL_INFO(p) (&__I915__(p)->info)
Chris Wilson87f1f462014-08-09 19:18:42 +01002399#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
Hoath, Nicholase90a21d2015-02-05 10:47:17 +00002400#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
Zou Nan haicae58522010-11-09 17:17:32 +08002401
Chris Wilson87f1f462014-08-09 19:18:42 +01002402#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2403#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
Zou Nan haicae58522010-11-09 17:17:32 +08002404#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002405#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
Zou Nan haicae58522010-11-09 17:17:32 +08002406#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
Chris Wilson87f1f462014-08-09 19:18:42 +01002407#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2408#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
Zou Nan haicae58522010-11-09 17:17:32 +08002409#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2410#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2411#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
Chris Wilson87f1f462014-08-09 19:18:42 +01002412#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
Zou Nan haicae58522010-11-09 17:17:32 +08002413#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002414#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2415#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
Zou Nan haicae58522010-11-09 17:17:32 +08002416#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2417#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
Chris Wilson87f1f462014-08-09 19:18:42 +01002418#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
Jesse Barnes4b651772011-04-28 14:33:09 -07002419#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
Chris Wilson87f1f462014-08-09 19:18:42 +01002420#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2421 INTEL_DEVID(dev) == 0x0152 || \
2422 INTEL_DEVID(dev) == 0x015a)
Jesse Barnes70a3eb72012-03-28 13:39:21 -07002423#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
Ville Syrjälä6df40272014-04-09 13:28:00 +03002424#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -03002425#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
Ville Syrjälä8179f1f2014-04-09 13:27:59 +03002426#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +05302427#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
Satheeshakrishna M1feed882015-03-17 11:39:29 +02002428#define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
Zou Nan haicae58522010-11-09 17:17:32 +08002429#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
Paulo Zanonied1c9e22013-08-12 14:34:08 -03002430#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002431 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002432#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
Rodrigo Vivi6b96d702015-01-19 16:16:15 -08002433 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
Rodrigo Vivi0dc6f202015-01-21 11:46:32 -08002434 (INTEL_DEVID(dev) & 0xf) == 0xb || \
Chris Wilson87f1f462014-08-09 19:18:42 +01002435 (INTEL_DEVID(dev) & 0xf) == 0xe))
Ville Syrjäläebb72aa2015-06-03 15:45:12 +03002436/* ULX machines are also considered ULT. */
2437#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2438 (INTEL_DEVID(dev) & 0xf) == 0xe)
Rodrigo Vivia0fcbd92014-09-19 20:16:26 -04002439#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2440 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002441#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002442 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
Rodrigo Vivi94353732013-08-28 16:45:46 -03002443#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002444 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Paulo Zanoni9bbfd202014-04-29 11:00:22 -03002445/* ULX machines are also considered ULT. */
Chris Wilson87f1f462014-08-09 19:18:42 +01002446#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2447 INTEL_DEVID(dev) == 0x0A1E)
David Weinehallf8896f52015-06-25 11:11:03 +03002448#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2449 INTEL_DEVID(dev) == 0x1913 || \
2450 INTEL_DEVID(dev) == 0x1916 || \
2451 INTEL_DEVID(dev) == 0x1921 || \
2452 INTEL_DEVID(dev) == 0x1926)
2453#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2454 INTEL_DEVID(dev) == 0x1915 || \
2455 INTEL_DEVID(dev) == 0x191E)
Ben Widawskyb833d682013-08-23 16:00:07 -07002456#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
Zou Nan haicae58522010-11-09 17:17:32 +08002457
Hoath, Nicholase90a21d2015-02-05 10:47:17 +00002458#define SKL_REVID_A0 (0x0)
2459#define SKL_REVID_B0 (0x1)
2460#define SKL_REVID_C0 (0x2)
2461#define SKL_REVID_D0 (0x3)
Damien Lespiau8bc0ccf2015-02-09 19:33:18 +00002462#define SKL_REVID_E0 (0x4)
Imre Deakb88baa22015-05-19 15:05:00 +03002463#define SKL_REVID_F0 (0x5)
Hoath, Nicholase90a21d2015-02-05 10:47:17 +00002464
Nick Hoath6c74c872015-03-20 09:03:52 +00002465#define BXT_REVID_A0 (0x0)
2466#define BXT_REVID_B0 (0x3)
2467#define BXT_REVID_C0 (0x6)
2468
Jesse Barnes85436692011-04-06 12:11:14 -07002469/*
2470 * The genX designation typically refers to the render engine, so render
2471 * capability related checks should use IS_GEN, while display and other checks
2472 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2473 * chips, etc.).
2474 */
Zou Nan haicae58522010-11-09 17:17:32 +08002475#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2476#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2477#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2478#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2479#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
Jesse Barnes85436692011-04-06 12:11:14 -07002480#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
Ben Widawskyd2980842013-11-02 21:06:59 -07002481#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
Damien Lespiaub71252d2013-02-13 15:27:24 +00002482#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
Zou Nan haicae58522010-11-09 17:17:32 +08002483
Ben Widawsky73ae4782013-10-15 10:02:57 -07002484#define RENDER_RING (1<<RCS)
2485#define BSD_RING (1<<VCS)
2486#define BLT_RING (1<<BCS)
2487#define VEBOX_RING (1<<VECS)
Zhao Yakui845f74a2014-04-17 10:37:37 +08002488#define BSD2_RING (1<<VCS2)
Ben Widawsky63c42e52014-04-18 18:04:27 -03002489#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
Zhao Yakui845f74a2014-04-17 10:37:37 +08002490#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
Ben Widawsky63c42e52014-04-18 18:04:27 -03002491#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2492#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2493#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2494#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
Chris Wilsonf2fbc692014-08-24 19:35:31 +01002495 __I915__(dev)->ellc_size)
Zou Nan haicae58522010-11-09 17:17:32 +08002496#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2497
Ben Widawsky254f9652012-06-04 14:42:42 -07002498#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
Oscar Mateod7f621e2014-07-24 17:04:49 +01002499#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
Jesse Barnes692ef702014-08-05 07:51:18 -07002500#define USES_PPGTT(dev) (i915.enable_ppgtt)
2501#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
Daniel Vetter1d2a3142012-02-09 17:15:46 +01002502
Chris Wilson05394f32010-11-08 19:18:58 +00002503#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
Zou Nan haicae58522010-11-09 17:17:32 +08002504#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2505
Daniel Vetterb45305f2012-12-17 16:21:27 +01002506/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2507#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
Daniel Vetter4e6b7882014-02-07 16:33:20 +01002508/*
2509 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2510 * even when in MSI mode. This results in spurious interrupt warnings if the
2511 * legacy irq no. is shared with another device. The kernel then disables that
2512 * interrupt source and so prevents the other device from working properly.
2513 */
2514#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2515#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
Daniel Vetterb45305f2012-12-17 16:21:27 +01002516
Zou Nan haicae58522010-11-09 17:17:32 +08002517/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2518 * rows, which changed the alignment requirements and fence programming.
2519 */
2520#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2521 IS_I915GM(dev)))
Zou Nan haicae58522010-11-09 17:17:32 +08002522#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2523#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
Zou Nan haicae58522010-11-09 17:17:32 +08002524
2525#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2526#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01002527#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
Zou Nan haicae58522010-11-09 17:17:32 +08002528
Damien Lespiaudbf77862014-10-01 20:04:14 +01002529#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
Damien Lespiauf5adf942013-06-24 18:29:34 +01002530
Jani Nikula0c9b3712015-05-18 17:10:01 +03002531#define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2532 INTEL_INFO(dev)->gen >= 9)
2533
Damien Lespiaudd93be52013-04-22 18:40:39 +01002534#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
Damien Lespiau30568c42013-04-22 18:40:41 +01002535#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
Rodrigo Vivib32c6f42014-11-20 03:44:37 -08002536#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
Sonika Jindale3d99842015-01-22 14:30:54 +05302537 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2538 IS_SKYLAKE(dev))
Paulo Zanoni6157d3c2014-03-07 20:12:37 -03002539#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
Suketu Shah00776512015-04-16 14:22:14 +05302540 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2541 IS_SKYLAKE(dev))
Rodrigo Vivi58abf1d2014-10-07 07:06:50 -07002542#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2543#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002544
Daniel Vettereb805622015-05-04 14:58:44 +02002545#define HAS_CSR(dev) (IS_SKYLAKE(dev))
2546
Abdiel Janulguea9ed33c2015-07-01 10:12:23 +03002547#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2548 INTEL_INFO(dev)->gen >= 8)
2549
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002550#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2551#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2552#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2553#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2554#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2555#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302556#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2557#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002558
Chris Wilsonf2fbc692014-08-24 19:35:31 +01002559#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302560#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -03002561#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
Zou Nan haicae58522010-11-09 17:17:32 +08002562#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2563#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
Ben Widawsky40c7ead2013-04-05 13:12:40 -07002564#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
Paulo Zanoni45e6e3a2012-07-03 15:57:32 -03002565#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
Zou Nan haicae58522010-11-09 17:17:32 +08002566
Sonika Jindal5fafe292014-07-21 15:23:38 +05302567#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2568
Ben Widawsky040d2ba2013-09-19 11:01:40 -07002569/* DPF == dynamic parity feature */
2570#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2571#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
Ben Widawskye1ef7cc2012-07-24 20:47:31 -07002572
Ben Widawskyc8735b02012-09-07 19:43:39 -07002573#define GT_FREQUENCY_MULTIPLIER 50
Akash Goelde43ae92015-03-06 11:07:14 +05302574#define GEN9_FREQ_SCALER 3
Ben Widawskyc8735b02012-09-07 19:43:39 -07002575
Chris Wilson05394f32010-11-08 19:18:58 +00002576#include "i915_trace.h"
2577
Rob Clarkbaa70942013-08-02 13:27:49 -04002578extern const struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +10002579extern int i915_max_ioctl;
2580
Imre Deakfc49b3d2014-10-23 19:23:27 +03002581extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2582extern int i915_resume_legacy(struct drm_device *dev);
Dave Airlie7c1c2872008-11-28 14:22:24 +10002583
Jani Nikulad330a952014-01-21 11:24:25 +02002584/* i915_params.c */
2585struct i915_params {
2586 int modeset;
2587 int panel_ignore_lid;
Jani Nikulad330a952014-01-21 11:24:25 +02002588 int semaphores;
Jani Nikulad330a952014-01-21 11:24:25 +02002589 int lvds_channel_mode;
2590 int panel_use_ssc;
2591 int vbt_sdvo_panel_type;
2592 int enable_rc6;
2593 int enable_fbc;
Jani Nikulad330a952014-01-21 11:24:25 +02002594 int enable_ppgtt;
Oscar Mateo127f1002014-07-24 17:04:11 +01002595 int enable_execlists;
Jani Nikulad330a952014-01-21 11:24:25 +02002596 int enable_psr;
2597 unsigned int preliminary_hw_support;
2598 int disable_power_well;
2599 int enable_ips;
Damien Lespiaue5aa6542014-02-07 19:12:53 +00002600 int invert_brightness;
Brad Volkin351e3db2014-02-18 10:15:46 -08002601 int enable_cmd_parser;
Damien Lespiaue5aa6542014-02-07 19:12:53 +00002602 /* leave bools at the end to not create holes */
2603 bool enable_hangcheck;
2604 bool fastboot;
Jani Nikulad330a952014-01-21 11:24:25 +02002605 bool prefault_disable;
Daniel Vetter5bedeb22015-03-03 18:03:47 +01002606 bool load_detect_test;
Jani Nikulad330a952014-01-21 11:24:25 +02002607 bool reset;
Damien Lespiaua0bae572014-02-10 17:20:55 +00002608 bool disable_display;
Daniel Vetter7a10dfa2014-04-01 09:33:47 +02002609 bool disable_vtd_wa;
Sourab Gupta84c33a62014-06-02 16:47:17 +05302610 int use_mmio_flip;
Chris Wilson48572ed2014-12-18 10:55:50 +00002611 int mmio_debug;
Rob Clarke2c719b2014-12-15 13:56:32 -05002612 bool verbose_state_checks;
Matt Roperb2e77232015-01-22 16:53:12 -08002613 bool nuclear_pageflip;
Sonika Jindal9e458032015-05-06 17:35:48 +05302614 int edp_vswing;
Jani Nikulad330a952014-01-21 11:24:25 +02002615};
2616extern struct i915_params i915 __read_mostly;
2617
Linus Torvalds1da177e2005-04-16 15:20:36 -07002618 /* i915_dma.c */
Dave Airlie22eae942005-11-10 22:16:34 +11002619extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002620extern int i915_driver_unload(struct drm_device *);
John Harrison2885f6a2014-06-26 18:23:52 +01002621extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
Dave Airlie84b1fd12007-07-11 15:53:27 +10002622extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +10002623extern void i915_driver_preclose(struct drm_device *dev,
John Harrison2885f6a2014-06-26 18:23:52 +01002624 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002625extern void i915_driver_postclose(struct drm_device *dev,
John Harrison2885f6a2014-06-26 18:23:52 +01002626 struct drm_file *file);
Dave Airlie84b1fd12007-07-11 15:53:27 +10002627extern int i915_driver_device_is_agp(struct drm_device * dev);
Ben Widawskyc43b5632012-04-16 14:07:40 -07002628#ifdef CONFIG_COMPAT
Dave Airlie0d6aa602006-01-02 20:14:23 +11002629extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2630 unsigned long arg);
Ben Widawskyc43b5632012-04-16 14:07:40 -07002631#endif
Ben Widawsky8e96d9c2012-06-04 14:42:56 -07002632extern int intel_gpu_reset(struct drm_device *dev);
Chris Wilson49e4d8422015-06-15 12:23:48 +01002633extern bool intel_has_gpu_reset(struct drm_device *dev);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +02002634extern int i915_reset(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002635extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2636extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2637extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2638extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
Imre Deak650ad972014-04-18 16:35:02 +03002639int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
Daniel Vettereb805622015-05-04 14:58:44 +02002640void i915_firmware_load_error_print(const char *fw_path, int err);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002641
Jani Nikula77913b32015-06-18 13:06:16 +03002642/* intel_hotplug.c */
2643void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2644void intel_hpd_init(struct drm_i915_private *dev_priv);
2645void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2646void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2647enum port intel_hpd_pin_to_port(enum hpd_pin pin);
2648
Linus Torvalds1da177e2005-04-16 15:20:36 -07002649/* i915_irq.c */
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03002650void i915_queue_hangcheck(struct drm_device *dev);
Mika Kuoppala58174462014-02-25 17:11:26 +02002651__printf(3, 4)
2652void i915_handle_error(struct drm_device *dev, bool wedged,
2653 const char *fmt, ...);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002654
Daniel Vetterb9632912014-09-30 10:56:44 +02002655extern void intel_irq_init(struct drm_i915_private *dev_priv);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02002656int intel_irq_install(struct drm_i915_private *dev_priv);
2657void intel_irq_uninstall(struct drm_i915_private *dev_priv);
Chris Wilson907b28c2013-07-19 20:36:52 +01002658
2659extern void intel_uncore_sanitize(struct drm_device *dev);
Imre Deak10018602014-06-06 12:59:39 +03002660extern void intel_uncore_early_sanitize(struct drm_device *dev,
2661 bool restore_forcewake);
Chris Wilson907b28c2013-07-19 20:36:52 +01002662extern void intel_uncore_init(struct drm_device *dev);
Chris Wilson907b28c2013-07-19 20:36:52 +01002663extern void intel_uncore_check_errors(struct drm_device *dev);
Chris Wilsonaec347a2013-08-26 13:46:09 +01002664extern void intel_uncore_fini(struct drm_device *dev);
Jesse Barnes156c7ca2014-06-12 08:35:45 -07002665extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
Mika Kuoppala48c10262015-01-16 11:34:41 +02002666const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002667void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +02002668 enum forcewake_domains domains);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002669void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +02002670 enum forcewake_domains domains);
Chris Wilsona6111f72015-04-07 16:21:02 +01002671/* Like above but the caller must manage the uncore.lock itself.
2672 * Must be used with I915_READ_FW and friends.
2673 */
2674void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2675 enum forcewake_domains domains);
2676void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2677 enum forcewake_domains domains);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002678void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
Yu Zhangcf9d2892015-02-10 19:05:47 +08002679static inline bool intel_vgpu_active(struct drm_device *dev)
2680{
2681 return to_i915(dev)->vgpu.active;
2682}
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002683
Keith Packard7c463582008-11-04 02:03:27 -08002684void
Jani Nikula50227e12014-03-31 14:27:21 +03002685i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002686 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002687
2688void
Jani Nikula50227e12014-03-31 14:27:21 +03002689i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002690 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002691
Imre Deakf8b79e52014-03-04 19:23:07 +02002692void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2693void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
Daniel Vetter47339cd2014-09-30 10:56:46 +02002694void
2695ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2696void
2697ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2698void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2699 uint32_t interrupt_mask,
2700 uint32_t enabled_irq_mask);
2701#define ibx_enable_display_interrupt(dev_priv, bits) \
2702 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2703#define ibx_disable_display_interrupt(dev_priv, bits) \
2704 ibx_display_interrupt_update((dev_priv), (bits), 0)
Imre Deakf8b79e52014-03-04 19:23:07 +02002705
Eric Anholt673a3942008-07-30 12:06:12 -07002706/* i915_gem.c */
Eric Anholt673a3942008-07-30 12:06:12 -07002707int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2708 struct drm_file *file_priv);
2709int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2710 struct drm_file *file_priv);
2711int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2712 struct drm_file *file_priv);
2713int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2714 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002715int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2716 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002717int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2718 struct drm_file *file_priv);
2719int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2720 struct drm_file *file_priv);
Oscar Mateoba8b7cc2014-07-24 17:04:33 +01002721void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
John Harrison8a8edb52015-05-29 17:43:33 +01002722 struct drm_i915_gem_request *req);
John Harrisonadeca762015-05-29 17:43:28 +01002723void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
John Harrison5f19e2b2015-05-29 17:43:27 +01002724int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
Oscar Mateoa83014d2014-07-24 17:04:21 +01002725 struct drm_i915_gem_execbuffer2 *args,
John Harrison5f19e2b2015-05-29 17:43:27 +01002726 struct list_head *vmas);
Eric Anholt673a3942008-07-30 12:06:12 -07002727int i915_gem_execbuffer(struct drm_device *dev, void *data,
2728 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -05002729int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2730 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002731int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2732 struct drm_file *file_priv);
Ben Widawsky199adf42012-09-21 17:01:20 -07002733int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2734 struct drm_file *file);
2735int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2736 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002737int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2738 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +01002739int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2740 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002741int i915_gem_set_tiling(struct drm_device *dev, void *data,
2742 struct drm_file *file_priv);
2743int i915_gem_get_tiling(struct drm_device *dev, void *data,
2744 struct drm_file *file_priv);
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002745int i915_gem_init_userptr(struct drm_device *dev);
2746int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2747 struct drm_file *file);
Eric Anholt5a125c32008-10-22 21:40:13 -07002748int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2749 struct drm_file *file_priv);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002750int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2751 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002752void i915_gem_load(struct drm_device *dev);
Chris Wilson42dcedd2012-11-15 11:32:30 +00002753void *i915_gem_object_alloc(struct drm_device *dev);
2754void i915_gem_object_free(struct drm_i915_gem_object *obj);
Chris Wilson37e680a2012-06-07 15:38:42 +01002755void i915_gem_object_init(struct drm_i915_gem_object *obj,
2756 const struct drm_i915_gem_object_ops *ops);
Chris Wilson05394f32010-11-08 19:18:58 +00002757struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2758 size_t size);
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08002759void i915_init_vm(struct drm_i915_private *dev_priv,
2760 struct i915_address_space *vm);
Eric Anholt673a3942008-07-30 12:06:12 -07002761void i915_gem_free_object(struct drm_gem_object *obj);
Ben Widawsky2f633152013-07-17 12:19:03 -07002762void i915_gem_vma_destroy(struct i915_vma *vma);
Chris Wilson42dcedd2012-11-15 11:32:30 +00002763
Daniel Vetter08755462015-04-20 09:04:05 -07002764/* Flags used by pin/bind&friends. */
2765#define PIN_MAPPABLE (1<<0)
2766#define PIN_NONBLOCK (1<<1)
2767#define PIN_GLOBAL (1<<2)
2768#define PIN_OFFSET_BIAS (1<<3)
2769#define PIN_USER (1<<4)
2770#define PIN_UPDATE (1<<5)
Chris Wilsond23db882014-05-23 08:48:08 +02002771#define PIN_OFFSET_MASK (~4095)
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002772int __must_check
2773i915_gem_object_pin(struct drm_i915_gem_object *obj,
2774 struct i915_address_space *vm,
2775 uint32_t alignment,
2776 uint64_t flags);
2777int __must_check
2778i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2779 const struct i915_ggtt_view *view,
2780 uint32_t alignment,
2781 uint64_t flags);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002782
2783int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2784 u32 flags);
Ben Widawsky07fe0b12013-07-31 17:00:10 -07002785int __must_check i915_vma_unbind(struct i915_vma *vma);
Chris Wilsondd624af2013-01-15 12:39:35 +00002786int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
Paulo Zanoni48018a52013-12-13 15:22:31 -02002787void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
Chris Wilson05394f32010-11-08 19:18:58 +00002788void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002789
Brad Volkin4c914c02014-02-18 10:15:45 -08002790int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2791 int *needs_clflush);
2792
Chris Wilson37e680a2012-06-07 15:38:42 +01002793int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
Chris Wilsonee286372015-04-07 16:20:25 +01002794
2795static inline int __sg_page_count(struct scatterlist *sg)
Chris Wilson9da3da62012-06-01 15:20:22 +01002796{
Chris Wilsonee286372015-04-07 16:20:25 +01002797 return sg->length >> PAGE_SHIFT;
Chris Wilson9da3da62012-06-01 15:20:22 +01002798}
Chris Wilsonee286372015-04-07 16:20:25 +01002799
2800static inline struct page *
2801i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2802{
2803 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2804 return NULL;
2805
2806 if (n < obj->get_page.last) {
2807 obj->get_page.sg = obj->pages->sgl;
2808 obj->get_page.last = 0;
2809 }
2810
2811 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2812 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2813 if (unlikely(sg_is_chain(obj->get_page.sg)))
2814 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2815 }
2816
2817 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2818}
2819
Chris Wilsona5570172012-09-04 21:02:54 +01002820static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2821{
2822 BUG_ON(obj->pages == NULL);
2823 obj->pages_pin_count++;
2824}
2825static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2826{
2827 BUG_ON(obj->pages_pin_count == 0);
2828 obj->pages_pin_count--;
2829}
2830
Chris Wilson54cf91d2010-11-25 18:00:26 +00002831int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
Ben Widawsky2911a352012-04-05 14:47:36 -07002832int i915_gem_object_sync(struct drm_i915_gem_object *obj,
John Harrison91af1272015-06-18 13:14:56 +01002833 struct intel_engine_cs *to,
2834 struct drm_i915_gem_request **to_req);
Ben Widawskye2d05a82013-09-24 09:57:58 -07002835void i915_vma_move_to_active(struct i915_vma *vma,
John Harrisonb2af0372015-05-29 17:43:50 +01002836 struct drm_i915_gem_request *req);
Dave Airlieff72145b2011-02-07 12:16:14 +10002837int i915_gem_dumb_create(struct drm_file *file_priv,
2838 struct drm_device *dev,
2839 struct drm_mode_create_dumb *args);
Dave Airlieda6b51d2014-12-24 13:11:17 +10002840int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2841 uint32_t handle, uint64_t *offset);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002842/**
2843 * Returns true if seq1 is later than seq2.
2844 */
2845static inline bool
2846i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2847{
2848 return (int32_t)(seq1 - seq2) >= 0;
2849}
2850
John Harrison1b5a4332014-11-24 18:49:42 +00002851static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2852 bool lazy_coherency)
2853{
2854 u32 seqno;
2855
2856 BUG_ON(req == NULL);
2857
2858 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2859
2860 return i915_seqno_passed(seqno, req->seqno);
2861}
2862
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02002863int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2864int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
Chris Wilson06d98132012-04-17 15:31:24 +01002865int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
Chris Wilsond9e86c02010-11-10 16:40:20 +00002866int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00002867
Daniel Vetterd8ffa602014-05-13 12:11:26 +02002868bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2869void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002870
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002871struct drm_i915_gem_request *
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002872i915_gem_find_active_request(struct intel_engine_cs *ring);
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002873
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002874bool i915_gem_retire_requests(struct drm_device *dev);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002875void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
Daniel Vetter33196de2012-11-14 17:14:05 +01002876int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
Daniel Vetterd6b2c792012-07-04 22:54:13 +02002877 bool interruptible);
Sourab Gupta84c33a62014-06-02 16:47:17 +05302878
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002879static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2880{
2881 return unlikely(atomic_read(&error->reset_counter)
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002882 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002883}
2884
2885static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2886{
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002887 return atomic_read(&error->reset_counter) & I915_WEDGED;
2888}
2889
2890static inline u32 i915_reset_count(struct i915_gpu_error *error)
2891{
2892 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002893}
Chris Wilsona71d8d92012-02-15 11:25:36 +00002894
Mika Kuoppala88b4aa82014-03-28 18:18:18 +02002895static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2896{
2897 return dev_priv->gpu_error.stop_rings == 0 ||
2898 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2899}
2900
2901static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2902{
2903 return dev_priv->gpu_error.stop_rings == 0 ||
2904 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2905}
2906
Chris Wilson069efc12010-09-30 16:53:18 +01002907void i915_gem_reset(struct drm_device *dev);
Chris Wilson000433b2013-08-08 14:41:09 +01002908bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
Chris Wilson1070a422012-04-24 15:47:41 +01002909int __must_check i915_gem_init(struct drm_device *dev);
Oscar Mateoa83014d2014-07-24 17:04:21 +01002910int i915_gem_init_rings(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002911int __must_check i915_gem_init_hw(struct drm_device *dev);
John Harrison6909a662015-05-29 17:43:51 +01002912int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002913void i915_gem_init_swizzling(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002914void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07002915int __must_check i915_gpu_idle(struct drm_device *dev);
Chris Wilson45c5f202013-10-16 11:50:01 +01002916int __must_check i915_gem_suspend(struct drm_device *dev);
John Harrison75289872015-05-29 17:43:49 +01002917void __i915_add_request(struct drm_i915_gem_request *req,
John Harrison5b4a60c2015-05-29 17:43:34 +01002918 struct drm_i915_gem_object *batch_obj,
2919 bool flush_caches);
John Harrison75289872015-05-29 17:43:49 +01002920#define i915_add_request(req) \
John Harrisonfcfa423c2015-05-29 17:44:12 +01002921 __i915_add_request(req, NULL, true)
John Harrison75289872015-05-29 17:43:49 +01002922#define i915_add_request_no_flush(req) \
John Harrisonfcfa423c2015-05-29 17:44:12 +01002923 __i915_add_request(req, NULL, false)
John Harrison9c654812014-11-24 18:49:35 +00002924int __i915_wait_request(struct drm_i915_gem_request *req,
Ander Conselvan de Oliveira16e9a212014-11-06 09:26:38 +02002925 unsigned reset_counter,
2926 bool interruptible,
2927 s64 *timeout,
Chris Wilson2e1b8732015-04-27 13:41:22 +01002928 struct intel_rps_client *rps);
Daniel Vettera4b3a572014-11-26 14:17:05 +01002929int __must_check i915_wait_request(struct drm_i915_gem_request *req);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002930int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Chris Wilson20217462010-11-23 15:26:33 +00002931int __must_check
Chris Wilson2e2f3512015-04-27 13:41:14 +01002932i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2933 bool readonly);
2934int __must_check
Chris Wilson20217462010-11-23 15:26:33 +00002935i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2936 bool write);
2937int __must_check
Chris Wilsondabdfe02012-03-26 10:10:27 +02002938i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2939int __must_check
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002940i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2941 u32 alignment,
Tvrtko Ursuline6617332015-03-23 11:10:33 +00002942 struct intel_engine_cs *pipelined,
John Harrison91af1272015-06-18 13:14:56 +01002943 struct drm_i915_gem_request **pipelined_request,
Tvrtko Ursuline6617332015-03-23 11:10:33 +00002944 const struct i915_ggtt_view *view);
2945void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
2946 const struct i915_ggtt_view *view);
Chris Wilson00731152014-05-21 12:42:56 +01002947int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01002948 int align);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002949int i915_gem_open(struct drm_device *dev, struct drm_file *file);
Chris Wilson05394f32010-11-08 19:18:58 +00002950void i915_gem_release(struct drm_device *dev, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002951
Chris Wilson467cffb2011-03-07 10:42:03 +00002952uint32_t
Imre Deak0fa87792013-01-07 21:47:35 +02002953i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2954uint32_t
Imre Deakd865110c2013-01-07 21:47:33 +02002955i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2956 int tiling_mode, bool fenced);
Chris Wilson467cffb2011-03-07 10:42:03 +00002957
Chris Wilsone4ffd172011-04-04 09:44:39 +01002958int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2959 enum i915_cache_level cache_level);
2960
Daniel Vetter1286ff72012-05-10 15:25:09 +02002961struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2962 struct dma_buf *dma_buf);
2963
2964struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2965 struct drm_gem_object *gem_obj, int flags);
2966
Chris Wilson19b2dbd2013-06-12 10:15:12 +01002967void i915_gem_restore_fences(struct drm_device *dev);
2968
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002969unsigned long
2970i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02002971 const struct i915_ggtt_view *view);
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002972unsigned long
2973i915_gem_obj_offset(struct drm_i915_gem_object *o,
2974 struct i915_address_space *vm);
2975static inline unsigned long
2976i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002977{
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02002978 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002979}
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002980
Ben Widawskya70a3142013-07-31 16:59:56 -07002981bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002982bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02002983 const struct i915_ggtt_view *view);
Ben Widawskya70a3142013-07-31 16:59:56 -07002984bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002985 struct i915_address_space *vm);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002986
Ben Widawskya70a3142013-07-31 16:59:56 -07002987unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2988 struct i915_address_space *vm);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002989struct i915_vma *
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002990i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2991 struct i915_address_space *vm);
2992struct i915_vma *
2993i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
2994 const struct i915_ggtt_view *view);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002995
Ben Widawskyaccfef22013-08-14 11:38:35 +02002996struct i915_vma *
2997i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002998 struct i915_address_space *vm);
2999struct i915_vma *
3000i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3001 const struct i915_ggtt_view *view);
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07003002
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003003static inline struct i915_vma *
3004i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3005{
3006 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08003007}
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003008bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07003009
Ben Widawskya70a3142013-07-31 16:59:56 -07003010/* Some GGTT VM helpers */
Daniel Vetter5dc383b2014-08-06 15:04:49 +02003011#define i915_obj_to_ggtt(obj) \
Ben Widawskya70a3142013-07-31 16:59:56 -07003012 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3013static inline bool i915_is_ggtt(struct i915_address_space *vm)
3014{
3015 struct i915_address_space *ggtt =
3016 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3017 return vm == ggtt;
3018}
3019
Daniel Vetter841cd772014-08-06 15:04:48 +02003020static inline struct i915_hw_ppgtt *
3021i915_vm_to_ppgtt(struct i915_address_space *vm)
3022{
3023 WARN_ON(i915_is_ggtt(vm));
3024
3025 return container_of(vm, struct i915_hw_ppgtt, base);
3026}
3027
3028
Ben Widawskya70a3142013-07-31 16:59:56 -07003029static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3030{
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02003031 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
Ben Widawskya70a3142013-07-31 16:59:56 -07003032}
3033
3034static inline unsigned long
3035i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3036{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02003037 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
Ben Widawskya70a3142013-07-31 16:59:56 -07003038}
Ben Widawskyc37e2202013-07-31 16:59:58 -07003039
3040static inline int __must_check
3041i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3042 uint32_t alignment,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003043 unsigned flags)
Ben Widawskyc37e2202013-07-31 16:59:58 -07003044{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02003045 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3046 alignment, flags | PIN_GLOBAL);
Ben Widawskyc37e2202013-07-31 16:59:58 -07003047}
Ben Widawskya70a3142013-07-31 16:59:56 -07003048
Daniel Vetterb2871102014-02-14 14:01:19 +01003049static inline int
3050i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3051{
3052 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3053}
3054
Tvrtko Ursuline6617332015-03-23 11:10:33 +00003055void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3056 const struct i915_ggtt_view *view);
3057static inline void
3058i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3059{
3060 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3061}
Daniel Vetterb2871102014-02-14 14:01:19 +01003062
Ben Widawsky254f9652012-06-04 14:42:42 -07003063/* i915_gem_context.c */
Ben Widawsky8245be32013-11-06 13:56:29 -02003064int __must_check i915_gem_context_init(struct drm_device *dev);
Ben Widawsky254f9652012-06-04 14:42:42 -07003065void i915_gem_context_fini(struct drm_device *dev);
Ben Widawskyacce9ff2013-12-06 14:11:03 -08003066void i915_gem_context_reset(struct drm_device *dev);
Ben Widawskye422b882013-12-06 14:10:58 -08003067int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
John Harrisonb3dd6b92015-05-29 17:43:40 +01003068int i915_gem_context_enable(struct drm_i915_gem_request *req);
Ben Widawsky254f9652012-06-04 14:42:42 -07003069void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
John Harrisonba01cc92015-05-29 17:43:41 +01003070int i915_switch_context(struct drm_i915_gem_request *req);
Oscar Mateo273497e2014-05-22 14:13:37 +01003071struct intel_context *
Ben Widawsky41bde552013-12-06 14:11:21 -08003072i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
Mika Kuoppaladce32712013-04-30 13:30:33 +03003073void i915_gem_context_free(struct kref *ctx_ref);
Oscar Mateo8c8579172014-07-24 17:04:14 +01003074struct drm_i915_gem_object *
3075i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
Oscar Mateo273497e2014-05-22 14:13:37 +01003076static inline void i915_gem_context_reference(struct intel_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03003077{
Chris Wilson691e6412014-04-09 09:07:36 +01003078 kref_get(&ctx->ref);
Mika Kuoppaladce32712013-04-30 13:30:33 +03003079}
3080
Oscar Mateo273497e2014-05-22 14:13:37 +01003081static inline void i915_gem_context_unreference(struct intel_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03003082{
Chris Wilson691e6412014-04-09 09:07:36 +01003083 kref_put(&ctx->ref, i915_gem_context_free);
Mika Kuoppaladce32712013-04-30 13:30:33 +03003084}
3085
Oscar Mateo273497e2014-05-22 14:13:37 +01003086static inline bool i915_gem_context_is_default(const struct intel_context *c)
Mika Kuoppala3fac8972014-01-30 16:05:48 +02003087{
Oscar Mateo821d66d2014-07-03 16:28:00 +01003088 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
Mika Kuoppala3fac8972014-01-30 16:05:48 +02003089}
3090
Ben Widawsky84624812012-06-04 14:42:54 -07003091int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3092 struct drm_file *file);
3093int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3094 struct drm_file *file);
Chris Wilsonc9dc0f32014-12-24 08:13:40 -08003095int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3096 struct drm_file *file_priv);
3097int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3098 struct drm_file *file_priv);
Daniel Vetter1286ff72012-05-10 15:25:09 +02003099
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01003100/* i915_gem_evict.c */
Ben Widawskyf6cd1f12013-07-31 17:00:11 -07003101int __must_check i915_gem_evict_something(struct drm_device *dev,
3102 struct i915_address_space *vm,
3103 int min_size,
Chris Wilson42d6ab42012-07-26 11:49:32 +01003104 unsigned alignment,
3105 unsigned cache_level,
Chris Wilsond23db882014-05-23 08:48:08 +02003106 unsigned long start,
3107 unsigned long end,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003108 unsigned flags);
Ben Widawsky68c8c172013-09-11 14:57:50 -07003109int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
Chris Wilson6c085a72012-08-20 11:40:46 +02003110int i915_gem_evict_everything(struct drm_device *dev);
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01003111
Ben Widawsky0260c422014-03-22 22:47:21 -07003112/* belongs in i915_gem_gtt.h */
Eric Anholt673a3942008-07-30 12:06:12 -07003113static inline void i915_gem_chipset_flush(struct drm_device *dev)
3114{
Chris Wilson05394f32010-11-08 19:18:58 +00003115 if (INTEL_INFO(dev)->gen < 6)
3116 intel_gtt_chipset_flush();
Chris Wilson9797fbf2012-04-24 15:47:39 +01003117}
Ben Widawsky246cbfb2013-12-06 14:11:14 -08003118
Chris Wilson9797fbf2012-04-24 15:47:39 +01003119/* i915_gem_stolen.c */
Paulo Zanonid713fd42015-07-02 19:25:07 -03003120int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3121 struct drm_mm_node *node, u64 size,
3122 unsigned alignment);
3123void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3124 struct drm_mm_node *node);
Chris Wilson9797fbf2012-04-24 15:47:39 +01003125int i915_gem_init_stolen(struct drm_device *dev);
3126void i915_gem_cleanup_stolen(struct drm_device *dev);
Chris Wilson0104fdb2012-11-15 11:32:26 +00003127struct drm_i915_gem_object *
3128i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
Chris Wilson866d12b2013-02-19 13:31:37 -08003129struct drm_i915_gem_object *
3130i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3131 u32 stolen_offset,
3132 u32 gtt_offset,
3133 u32 size);
Chris Wilson9797fbf2012-04-24 15:47:39 +01003134
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003135/* i915_gem_shrinker.c */
3136unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3137 long target,
3138 unsigned flags);
3139#define I915_SHRINK_PURGEABLE 0x1
3140#define I915_SHRINK_UNBOUND 0x2
3141#define I915_SHRINK_BOUND 0x4
3142unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3143void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3144
3145
Eric Anholt673a3942008-07-30 12:06:12 -07003146/* i915_gem_tiling.c */
Chris Wilson2c1792a2013-08-01 18:39:55 +01003147static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
Chris Wilsone9b73c62012-12-03 21:03:14 +00003148{
Jani Nikula50227e12014-03-31 14:27:21 +03003149 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilsone9b73c62012-12-03 21:03:14 +00003150
3151 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3152 obj->tiling_mode != I915_TILING_NONE;
3153}
3154
Eric Anholt673a3942008-07-30 12:06:12 -07003155void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
Eric Anholt280b7132009-03-12 16:56:27 -07003156void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3157void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003158
3159/* i915_gem_debug.c */
Chris Wilson23bc5982010-09-29 16:10:57 +01003160#if WATCH_LISTS
3161int i915_verify_lists(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -07003162#else
Chris Wilson23bc5982010-09-29 16:10:57 +01003163#define i915_verify_lists(dev) 0
Eric Anholt673a3942008-07-30 12:06:12 -07003164#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003165
Ben Gamari20172632009-02-17 20:08:50 -05003166/* i915_debugfs.c */
Ben Gamari27c202a2009-07-01 22:26:52 -04003167int i915_debugfs_init(struct drm_minor *minor);
3168void i915_debugfs_cleanup(struct drm_minor *minor);
Daniel Vetterf8c168f2013-10-16 11:49:58 +02003169#ifdef CONFIG_DEBUG_FS
Jani Nikula249e87d2015-04-10 16:59:32 +03003170int i915_debugfs_connector_add(struct drm_connector *connector);
Damien Lespiau07144422013-10-15 18:55:40 +01003171void intel_display_crc_init(struct drm_device *dev);
3172#else
Jani Nikula249e87d2015-04-10 16:59:32 +03003173static inline int i915_debugfs_connector_add(struct drm_connector *connector) {}
Daniel Vetterf8c168f2013-10-16 11:49:58 +02003174static inline void intel_display_crc_init(struct drm_device *dev) {}
Damien Lespiau07144422013-10-15 18:55:40 +01003175#endif
Mika Kuoppala84734a02013-07-12 16:50:57 +03003176
3177/* i915_gpu_error.c */
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003178__printf(2, 3)
3179void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
Mika Kuoppalafc16b482013-06-06 15:18:39 +03003180int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3181 const struct i915_error_state_file_priv *error);
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03003182int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01003183 struct drm_i915_private *i915,
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03003184 size_t count, loff_t pos);
3185static inline void i915_error_state_buf_release(
3186 struct drm_i915_error_state_buf *eb)
3187{
3188 kfree(eb->buf);
3189}
Mika Kuoppala58174462014-02-25 17:11:26 +02003190void i915_capture_error_state(struct drm_device *dev, bool wedge,
3191 const char *error_msg);
Mika Kuoppala84734a02013-07-12 16:50:57 +03003192void i915_error_state_get(struct drm_device *dev,
3193 struct i915_error_state_file_priv *error_priv);
3194void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3195void i915_destroy_error_state(struct drm_device *dev);
3196
3197void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01003198const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
Ben Gamari20172632009-02-17 20:08:50 -05003199
Brad Volkin351e3db2014-02-18 10:15:46 -08003200/* i915_cmd_parser.c */
Brad Volkind728c8e2014-02-18 10:15:56 -08003201int i915_cmd_parser_get_version(void);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01003202int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3203void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3204bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3205int i915_parse_cmds(struct intel_engine_cs *ring,
Brad Volkin351e3db2014-02-18 10:15:46 -08003206 struct drm_i915_gem_object *batch_obj,
Brad Volkin78a42372014-12-11 12:13:09 -08003207 struct drm_i915_gem_object *shadow_batch_obj,
Brad Volkin351e3db2014-02-18 10:15:46 -08003208 u32 batch_start_offset,
Brad Volkinb9ffd802014-12-11 12:13:10 -08003209 u32 batch_len,
Brad Volkin351e3db2014-02-18 10:15:46 -08003210 bool is_master);
3211
Jesse Barnes317c35d2008-08-25 15:11:06 -07003212/* i915_suspend.c */
3213extern int i915_save_state(struct drm_device *dev);
3214extern int i915_restore_state(struct drm_device *dev);
3215
Ben Widawsky0136db52012-04-10 21:17:01 -07003216/* i915_sysfs.c */
3217void i915_setup_sysfs(struct drm_device *dev_priv);
3218void i915_teardown_sysfs(struct drm_device *dev_priv);
3219
Chris Wilsonf899fc62010-07-20 15:44:45 -07003220/* intel_i2c.c */
3221extern int intel_setup_gmbus(struct drm_device *dev);
3222extern void intel_teardown_gmbus(struct drm_device *dev);
Jani Nikula88ac7932015-03-27 00:20:22 +02003223extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3224 unsigned int pin);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08003225
Jani Nikula0184df462015-03-27 00:20:20 +02003226extern struct i2c_adapter *
3227intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
Chris Wilsone957d772010-09-24 12:52:03 +01003228extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3229extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02003230static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
Chris Wilsonb8232e92010-09-28 16:41:32 +01003231{
3232 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3233}
Chris Wilsonf899fc62010-07-20 15:44:45 -07003234extern void intel_i2c_reset(struct drm_device *dev);
3235
Chris Wilson3b617962010-08-24 09:02:58 +01003236/* intel_opregion.c */
Chris Wilson44834a62010-08-19 16:09:23 +01003237#ifdef CONFIG_ACPI
Lv Zheng27d50c82013-12-06 16:52:05 +08003238extern int intel_opregion_setup(struct drm_device *dev);
Chris Wilson44834a62010-08-19 16:09:23 +01003239extern void intel_opregion_init(struct drm_device *dev);
3240extern void intel_opregion_fini(struct drm_device *dev);
Chris Wilson3b617962010-08-24 09:02:58 +01003241extern void intel_opregion_asle_intr(struct drm_device *dev);
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003242extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3243 bool enable);
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003244extern int intel_opregion_notify_adapter(struct drm_device *dev,
3245 pci_power_t state);
Len Brown65e082c2008-10-24 17:18:10 -04003246#else
Lv Zheng27d50c82013-12-06 16:52:05 +08003247static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
Chris Wilson44834a62010-08-19 16:09:23 +01003248static inline void intel_opregion_init(struct drm_device *dev) { return; }
3249static inline void intel_opregion_fini(struct drm_device *dev) { return; }
Chris Wilson3b617962010-08-24 09:02:58 +01003250static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003251static inline int
3252intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3253{
3254 return 0;
3255}
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003256static inline int
3257intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3258{
3259 return 0;
3260}
Len Brown65e082c2008-10-24 17:18:10 -04003261#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01003262
Jesse Barnes723bfd72010-10-07 16:01:13 -07003263/* intel_acpi.c */
3264#ifdef CONFIG_ACPI
3265extern void intel_register_dsm_handler(void);
3266extern void intel_unregister_dsm_handler(void);
3267#else
3268static inline void intel_register_dsm_handler(void) { return; }
3269static inline void intel_unregister_dsm_handler(void) { return; }
3270#endif /* CONFIG_ACPI */
3271
Jesse Barnes79e53942008-11-07 14:24:08 -08003272/* modesetting */
Daniel Vetterf8175862012-04-10 15:50:11 +02003273extern void intel_modeset_init_hw(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003274extern void intel_modeset_init(struct drm_device *dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01003275extern void intel_modeset_gem_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003276extern void intel_modeset_cleanup(struct drm_device *dev);
Imre Deak4932e2c2014-02-11 17:12:48 +02003277extern void intel_connector_unregister(struct intel_connector *);
Dave Airlie28d52042009-09-21 14:33:58 +10003278extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01003279extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3280 bool force_restore);
Daniel Vetter44cec742013-01-25 17:53:21 +01003281extern void i915_redisable_vga(struct drm_device *dev);
Imre Deak04098752014-02-18 00:02:16 +02003282extern void i915_redisable_vga_power_on(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07003283extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
Paulo Zanonidde86e22012-12-01 12:04:25 -02003284extern void intel_init_pch_refclk(struct drm_device *dev);
Ville Syrjäläffe02b42015-02-02 19:09:50 +02003285extern void intel_set_rps(struct drm_device *dev, u8 val);
Imre Deak5209b1f2014-07-01 12:36:17 +03003286extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3287 bool enable);
Akshay Joshi0206e352011-08-16 15:34:10 -04003288extern void intel_detect_pch(struct drm_device *dev);
3289extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
Ben Widawsky0136db52012-04-10 21:17:01 -07003290extern int intel_enable_rc6(const struct drm_device *dev);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08003291
Ben Widawsky2911a352012-04-05 14:47:36 -07003292extern bool i915_semaphore_is_enabled(struct drm_device *dev);
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07003293int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3294 struct drm_file *file);
Mika Kuoppalab6359912013-10-30 15:44:16 +02003295int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3296 struct drm_file *file);
Jesse Barnes575155a2012-03-28 13:39:37 -07003297
Chris Wilson6ef3d422010-08-04 20:26:07 +01003298/* overlay */
3299extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003300extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3301 struct intel_overlay_error_state *error);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003302
3303extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003304extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003305 struct drm_device *dev,
3306 struct intel_display_error_state *error);
Chris Wilson6ef3d422010-08-04 20:26:07 +01003307
Tom O'Rourke151a49d2014-11-13 18:50:10 -08003308int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3309int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03003310
3311/* intel_sideband.c */
Deepak S707b6e32015-01-16 20:42:17 +05303312u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3313void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
Jani Nikula64936252013-05-22 15:36:20 +03003314u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
Jani Nikulae9f882a2013-08-27 15:12:14 +03003315u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3316void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3317u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3318void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3319u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3320void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnesf3419152013-11-04 11:52:44 -08003321u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3322void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jani Nikulae9f882a2013-08-27 15:12:14 +03003323u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3324void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08003325u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3326void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03003327u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3328 enum intel_sbi_destination destination);
3329void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3330 enum intel_sbi_destination destination);
Shobhit Kumare9fe51c2013-12-10 12:14:55 +05303331u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3332void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07003333
Ville Syrjälä616bc822015-01-23 21:04:25 +02003334int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3335int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
Deepak Sc8d9a592013-11-23 14:55:42 +05303336
Ben Widawsky0b274482013-10-04 21:22:51 -07003337#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3338#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
Keith Packard5f753772010-11-22 09:24:22 +00003339
Ben Widawsky0b274482013-10-04 21:22:51 -07003340#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3341#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3342#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3343#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00003344
Ben Widawsky0b274482013-10-04 21:22:51 -07003345#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3346#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3347#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3348#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00003349
Chris Wilson698b3132014-03-21 13:16:43 +00003350/* Be very careful with read/write 64-bit values. On 32-bit machines, they
3351 * will be implemented using 2 32-bit writes in an arbitrary order with
3352 * an arbitrary delay between them. This can cause the hardware to
3353 * act upon the intermediate value, possibly leading to corruption and
3354 * machine death. You have been warned.
3355 */
Ben Widawsky0b274482013-10-04 21:22:51 -07003356#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3357#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
Zou Nan haicae58522010-11-09 17:17:32 +08003358
Chris Wilson50877442014-03-21 12:41:53 +00003359#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3360 u32 upper = I915_READ(upper_reg); \
3361 u32 lower = I915_READ(lower_reg); \
3362 u32 tmp = I915_READ(upper_reg); \
3363 if (upper != tmp) { \
3364 upper = tmp; \
3365 lower = I915_READ(lower_reg); \
3366 WARN_ON(I915_READ(upper_reg) != upper); \
3367 } \
3368 (u64)upper << 32 | lower; })
3369
Zou Nan haicae58522010-11-09 17:17:32 +08003370#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3371#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3372
Chris Wilsona6111f72015-04-07 16:21:02 +01003373/* These are untraced mmio-accessors that are only valid to be used inside
3374 * criticial sections inside IRQ handlers where forcewake is explicitly
3375 * controlled.
3376 * Think twice, and think again, before using these.
3377 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3378 * intel_uncore_forcewake_irqunlock().
3379 */
3380#define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3381#define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3382#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3383
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02003384/* "Broadcast RGB" property */
3385#define INTEL_BROADCAST_RGB_AUTO 0
3386#define INTEL_BROADCAST_RGB_FULL 1
3387#define INTEL_BROADCAST_RGB_LIMITED 2
Yuanhan Liuba4f01a2010-11-08 17:09:41 +08003388
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003389static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3390{
Sonika Jindal92e23b92014-07-21 15:23:40 +05303391 if (IS_VALLEYVIEW(dev))
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003392 return VLV_VGACNTRL;
Sonika Jindal92e23b92014-07-21 15:23:40 +05303393 else if (INTEL_INFO(dev)->gen >= 5)
3394 return CPU_VGACNTRL;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003395 else
3396 return VGACNTRL;
3397}
3398
Ville Syrjälä2bb46292013-02-22 16:12:51 +02003399static inline void __user *to_user_ptr(u64 address)
3400{
3401 return (void __user *)(uintptr_t)address;
3402}
3403
Imre Deakdf977292013-05-21 20:03:17 +03003404static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3405{
3406 unsigned long j = msecs_to_jiffies(m);
3407
3408 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3409}
3410
Daniel Vetter7bd0e222014-12-04 11:12:54 +01003411static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3412{
3413 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3414}
3415
Imre Deakdf977292013-05-21 20:03:17 +03003416static inline unsigned long
3417timespec_to_jiffies_timeout(const struct timespec *value)
3418{
3419 unsigned long j = timespec_to_jiffies(value);
3420
3421 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3422}
3423
Paulo Zanonidce56b32013-12-19 14:29:40 -02003424/*
3425 * If you need to wait X milliseconds between events A and B, but event B
3426 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3427 * when event A happened, then just before event B you call this function and
3428 * pass the timestamp as the first argument, and X as the second argument.
3429 */
3430static inline void
3431wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3432{
Imre Deakec5e0cf2014-01-29 13:25:40 +02003433 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
Paulo Zanonidce56b32013-12-19 14:29:40 -02003434
3435 /*
3436 * Don't re-read the value of "jiffies" every time since it may change
3437 * behind our back and break the math.
3438 */
3439 tmp_jiffies = jiffies;
3440 target_jiffies = timestamp_jiffies +
3441 msecs_to_jiffies_timeout(to_wait_ms);
3442
3443 if (time_after(target_jiffies, tmp_jiffies)) {
Imre Deakec5e0cf2014-01-29 13:25:40 +02003444 remaining_jiffies = target_jiffies - tmp_jiffies;
3445 while (remaining_jiffies)
3446 remaining_jiffies =
3447 schedule_timeout_uninterruptible(remaining_jiffies);
Paulo Zanonidce56b32013-12-19 14:29:40 -02003448 }
3449}
3450
John Harrison581c26e82014-11-24 18:49:39 +00003451static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3452 struct drm_i915_gem_request *req)
3453{
3454 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3455 i915_gem_request_assign(&ring->trace_irq_req, req);
3456}
3457
Linus Torvalds1da177e2005-04-16 15:20:36 -07003458#endif