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Lennert Buytenhek2e16a772008-10-07 13:46:22 +00001/*
2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
Lennert Buytenheke84665c2009-03-20 09:52:09 +00003 * Copyright (c) 2008-2009 Marvell Semiconductor
Lennert Buytenhek2e16a772008-10-07 13:46:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
Barry Grussling19b2f972013-01-08 16:05:54 +000011#include <linux/delay.h>
12#include <linux/jiffies.h>
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000013#include <linux/list.h>
Paul Gortmaker2bbba272012-01-24 10:41:40 +000014#include <linux/module.h>
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000015#include <linux/netdevice.h>
16#include <linux/phy.h>
Ben Hutchingsc8f0b862011-11-27 17:06:08 +000017#include <net/dsa.h>
Neil Armstrong6a4b2982015-11-10 16:51:36 +010018#include "mv88e6060.h"
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000019
20static int reg_read(struct dsa_switch *ds, int addr, int reg)
21{
Guenter Roeckb184e492014-10-17 12:30:58 -070022 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
23
24 if (bus == NULL)
25 return -EINVAL;
26
Neil Armstrongf0505612015-10-22 10:37:57 +020027 return mdiobus_read_nested(bus, ds->pd->sw_addr + addr, reg);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000028}
29
30#define REG_READ(addr, reg) \
31 ({ \
32 int __ret; \
33 \
34 __ret = reg_read(ds, addr, reg); \
35 if (__ret < 0) \
36 return __ret; \
37 __ret; \
38 })
39
40
41static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
42{
Guenter Roeckb184e492014-10-17 12:30:58 -070043 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
44
45 if (bus == NULL)
46 return -EINVAL;
47
Neil Armstrongf0505612015-10-22 10:37:57 +020048 return mdiobus_write_nested(bus, ds->pd->sw_addr + addr, reg, val);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000049}
50
51#define REG_WRITE(addr, reg, val) \
52 ({ \
53 int __ret; \
54 \
55 __ret = reg_write(ds, addr, reg, val); \
56 if (__ret < 0) \
57 return __ret; \
58 })
59
Alexander Duyckb4d23942014-09-15 13:00:27 -040060static char *mv88e6060_probe(struct device *host_dev, int sw_addr)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000061{
Alexander Duyckb4d23942014-09-15 13:00:27 -040062 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000063 int ret;
64
Alexander Duyckb4d23942014-09-15 13:00:27 -040065 if (bus == NULL)
66 return NULL;
67
Neil Armstrong6a4b2982015-11-10 16:51:36 +010068 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000069 if (ret >= 0) {
Neil Armstrong6a4b2982015-11-10 16:51:36 +010070 if (ret == PORT_SWITCH_ID_6060)
Guenter Roeck3de6aa4c2014-10-29 10:44:54 -070071 return "Marvell 88E6060 (A0)";
Neil Armstrong6a4b2982015-11-10 16:51:36 +010072 if (ret == PORT_SWITCH_ID_6060_R1 ||
73 ret == PORT_SWITCH_ID_6060_R2)
Guenter Roeck3de6aa4c2014-10-29 10:44:54 -070074 return "Marvell 88E6060 (B0)";
Neil Armstrong6a4b2982015-11-10 16:51:36 +010075 if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000076 return "Marvell 88E6060";
77 }
78
79 return NULL;
80}
81
82static int mv88e6060_switch_reset(struct dsa_switch *ds)
83{
84 int i;
85 int ret;
Barry Grussling19b2f972013-01-08 16:05:54 +000086 unsigned long timeout;
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000087
Barry Grussling3675c8d2013-01-08 16:05:53 +000088 /* Set all ports to the disabled state. */
Neil Armstrong6a4b2982015-11-10 16:51:36 +010089 for (i = 0; i < MV88E6060_PORTS; i++) {
90 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
91 REG_WRITE(REG_PORT(i), PORT_CONTROL,
92 ret & ~PORT_CONTROL_STATE_MASK);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000093 }
94
Barry Grussling3675c8d2013-01-08 16:05:53 +000095 /* Wait for transmit queues to drain. */
Barry Grussling19b2f972013-01-08 16:05:54 +000096 usleep_range(2000, 4000);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000097
Barry Grussling3675c8d2013-01-08 16:05:53 +000098 /* Reset the switch. */
Neil Armstrong6a4b2982015-11-10 16:51:36 +010099 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
100 GLOBAL_ATU_CONTROL_SWRESET |
101 GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
102 GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000103
Barry Grussling3675c8d2013-01-08 16:05:53 +0000104 /* Wait up to one second for reset to complete. */
Barry Grussling19b2f972013-01-08 16:05:54 +0000105 timeout = jiffies + 1 * HZ;
106 while (time_before(jiffies, timeout)) {
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100107 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
108 if (ret & GLOBAL_STATUS_INIT_READY)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000109 break;
110
Barry Grussling19b2f972013-01-08 16:05:54 +0000111 usleep_range(1000, 2000);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000112 }
Barry Grussling19b2f972013-01-08 16:05:54 +0000113 if (time_after(jiffies, timeout))
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000114 return -ETIMEDOUT;
115
116 return 0;
117}
118
119static int mv88e6060_setup_global(struct dsa_switch *ds)
120{
Barry Grussling3675c8d2013-01-08 16:05:53 +0000121 /* Disable discarding of frames with excessive collisions,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000122 * set the maximum frame size to 1536 bytes, and mask all
123 * interrupt sources.
124 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100125 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000126
Barry Grussling3675c8d2013-01-08 16:05:53 +0000127 /* Enable automatic address learning, set the address
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000128 * database size to 1024 entries, and set the default aging
129 * time to 5 minutes.
130 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100131 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
132 GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
133 GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000134
135 return 0;
136}
137
138static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
139{
140 int addr = REG_PORT(p);
141
Barry Grussling3675c8d2013-01-08 16:05:53 +0000142 /* Do not force flow control, disable Ingress and Egress
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000143 * Header tagging, disable VLAN tunneling, and set the port
144 * state to Forwarding. Additionally, if this is the CPU
145 * port, enable Ingress and Egress Trailer tagging mode.
146 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100147 REG_WRITE(addr, PORT_CONTROL,
148 dsa_is_cpu_port(ds, p) ?
149 PORT_CONTROL_TRAILER |
150 PORT_CONTROL_INGRESS_MODE |
151 PORT_CONTROL_STATE_FORWARDING :
152 PORT_CONTROL_STATE_FORWARDING);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000153
Barry Grussling3675c8d2013-01-08 16:05:53 +0000154 /* Port based VLAN map: give each port its own address
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000155 * database, allow the CPU port to talk to each of the 'real'
156 * ports, and allow each of the 'real' ports to only talk to
157 * the CPU port.
158 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100159 REG_WRITE(addr, PORT_VLAN_MAP,
160 ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
161 (dsa_is_cpu_port(ds, p) ?
162 ds->phys_port_mask :
163 BIT(ds->dst->cpu_port)));
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000164
Barry Grussling3675c8d2013-01-08 16:05:53 +0000165 /* Port Association Vector: when learning source addresses
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000166 * of packets, add the address to the address database using
167 * a port bitmap that has only the bit for this port set and
168 * the other bits clear.
169 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100170 REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000171
172 return 0;
173}
174
175static int mv88e6060_setup(struct dsa_switch *ds)
176{
177 int i;
178 int ret;
179
180 ret = mv88e6060_switch_reset(ds);
181 if (ret < 0)
182 return ret;
183
184 /* @@@ initialise atu */
185
186 ret = mv88e6060_setup_global(ds);
187 if (ret < 0)
188 return ret;
189
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100190 for (i = 0; i < MV88E6060_PORTS; i++) {
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000191 ret = mv88e6060_setup_port(ds, i);
192 if (ret < 0)
193 return ret;
194 }
195
196 return 0;
197}
198
199static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
200{
Neil Armstrong83ea0f42015-11-10 16:51:32 +0100201 /* Use the same MAC Address as FD Pause frames for all ports */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100202 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]);
203 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
204 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000205
206 return 0;
207}
208
209static int mv88e6060_port_to_phy_addr(int port)
210{
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100211 if (port >= 0 && port < MV88E6060_PORTS)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000212 return port;
213 return -1;
214}
215
216static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
217{
218 int addr;
219
220 addr = mv88e6060_port_to_phy_addr(port);
221 if (addr == -1)
222 return 0xffff;
223
224 return reg_read(ds, addr, regnum);
225}
226
227static int
228mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
229{
230 int addr;
231
232 addr = mv88e6060_port_to_phy_addr(port);
233 if (addr == -1)
234 return 0xffff;
235
236 return reg_write(ds, addr, regnum, val);
237}
238
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000239static struct dsa_switch_driver mv88e6060_switch_driver = {
Florian Fainelliac7a04c2014-09-11 21:18:09 -0700240 .tag_protocol = DSA_TAG_PROTO_TRAILER,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000241 .probe = mv88e6060_probe,
242 .setup = mv88e6060_setup,
243 .set_addr = mv88e6060_set_addr,
244 .phy_read = mv88e6060_phy_read,
245 .phy_write = mv88e6060_phy_write,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000246};
247
Roel Kluin5eaa65b2008-12-10 15:18:31 -0800248static int __init mv88e6060_init(void)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000249{
250 register_switch_driver(&mv88e6060_switch_driver);
251 return 0;
252}
253module_init(mv88e6060_init);
254
Roel Kluin5eaa65b2008-12-10 15:18:31 -0800255static void __exit mv88e6060_cleanup(void)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000256{
257 unregister_switch_driver(&mv88e6060_switch_driver);
258}
259module_exit(mv88e6060_cleanup);
Ben Hutchings3d825ed2011-11-25 14:37:16 +0000260
261MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
262MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
263MODULE_LICENSE("GPL");
264MODULE_ALIAS("platform:mv88e6060");