blob: a074459f8f2fb7761c046518d7ce0ac947ff0cda [file] [log] [blame]
Thomas Gleixnercaab2772019-06-03 07:44:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Catalin Marinasf1a0c4a2012-03-05 11:49:28 +00002/*
3 * Copyright (C) 2012 ARM Ltd.
Catalin Marinasf1a0c4a2012-03-05 11:49:28 +00004 */
5#ifndef __ASM_CACHE_H
6#define __ASM_CACHE_H
7
Will Deacon02f77602017-03-10 20:32:23 +00008#include <asm/cputype.h>
9
10#define CTR_L1IP_SHIFT 14
11#define CTR_L1IP_MASK 3
Shanker Donthineni6ae4b6e2018-03-07 09:00:08 -060012#define CTR_DMINLINE_SHIFT 16
Suzuki K Poulose4c4a39d2018-07-04 23:07:45 +010013#define CTR_IMINLINE_SHIFT 0
James Morseee9d90b2019-10-17 18:42:59 +010014#define CTR_IMINLINE_MASK 0xf
Shanker Donthineni6ae4b6e2018-03-07 09:00:08 -060015#define CTR_ERG_SHIFT 20
Will Deacon02f77602017-03-10 20:32:23 +000016#define CTR_CWG_SHIFT 24
17#define CTR_CWG_MASK 15
Shanker Donthineni6ae4b6e2018-03-07 09:00:08 -060018#define CTR_IDC_SHIFT 28
19#define CTR_DIC_SHIFT 29
Will Deacon02f77602017-03-10 20:32:23 +000020
Suzuki K Poulose4c4a39d2018-07-04 23:07:45 +010021#define CTR_CACHE_MINLINE_MASK \
James Morseee9d90b2019-10-17 18:42:59 +010022 (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
Suzuki K Poulose4c4a39d2018-07-04 23:07:45 +010023
Will Deacon02f77602017-03-10 20:32:23 +000024#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
25
Will Deacondda288d2017-03-10 20:32:24 +000026#define ICACHE_POLICY_VPIPT 0
Arnd Bergmann332576e2020-10-26 20:37:46 +010027#define ICACHE_POLICY_RESERVED 1
Will Deacon02f77602017-03-10 20:32:23 +000028#define ICACHE_POLICY_VIPT 2
29#define ICACHE_POLICY_PIPT 3
Catalin Marinasa41dc0e2014-04-03 17:48:54 +010030
Catalin Marinasd93277b2018-05-11 13:25:49 +010031#define L1_CACHE_SHIFT (6)
Catalin Marinasf1a0c4a2012-03-05 11:49:28 +000032#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
33
Suzuki K Poulose1602df02018-10-09 14:47:06 +010034
35#define CLIDR_LOUU_SHIFT 27
36#define CLIDR_LOC_SHIFT 24
37#define CLIDR_LOUIS_SHIFT 21
38
39#define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
40#define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
41#define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
42
Catalin Marinasf1a0c4a2012-03-05 11:49:28 +000043/*
44 * Memory returned by kmalloc() may be used for DMA, so we must make
45 * sure that all such allocations are cache aligned. Otherwise,
46 * unrelated code may cause parts of the buffer to be read into the
47 * cache before the transfer is done, causing old data to be seen by
48 * the CPU.
49 */
Catalin Marinasebc7e212018-05-11 13:33:12 +010050#define ARCH_DMA_MINALIGN (128)
Catalin Marinasa41dc0e2014-04-03 17:48:54 +010051
Andrey Konovaloveb214f22019-01-08 15:23:11 -080052#ifdef CONFIG_KASAN_SW_TAGS
53#define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT)
Andrey Konovalov03c75812020-12-22 12:01:52 -080054#elif defined(CONFIG_KASAN_HW_TAGS)
55#define ARCH_SLAB_MINALIGN MTE_GRANULE_SIZE
Andrey Konovaloveb214f22019-01-08 15:23:11 -080056#endif
57
Catalin Marinasa41dc0e2014-04-03 17:48:54 +010058#ifndef __ASSEMBLY__
59
Will Deacon02f77602017-03-10 20:32:23 +000060#include <linux/bitops.h>
61
62#define ICACHEF_ALIASING 0
Will Deacondda288d2017-03-10 20:32:24 +000063#define ICACHEF_VPIPT 1
Will Deacon02f77602017-03-10 20:32:23 +000064extern unsigned long __icache_flags;
65
66/*
67 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
68 * permitted in the I-cache.
69 */
70static inline int icache_is_aliasing(void)
71{
72 return test_bit(ICACHEF_ALIASING, &__icache_flags);
73}
74
James Morsee43f1332020-02-20 16:58:39 +000075static __always_inline int icache_is_vpipt(void)
Will Deacondda288d2017-03-10 20:32:24 +000076{
77 return test_bit(ICACHEF_VPIPT, &__icache_flags);
78}
79
Will Deacon02f77602017-03-10 20:32:23 +000080static inline u32 cache_type_cwg(void)
81{
82 return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
83}
84
Joe Perches33def842020-10-21 19:36:07 -070085#define __read_mostly __section(".data..read_mostly")
Jungseok Leee4f88d82014-12-02 17:49:24 +000086
Masayoshi Mizuma8f5c9032019-06-14 09:11:41 -040087static inline int cache_line_size_of_cpu(void)
Catalin Marinasa41dc0e2014-04-03 17:48:54 +010088{
89 u32 cwg = cache_type_cwg();
Masayoshi Mizuma8f5c9032019-06-14 09:11:41 -040090
Catalin Marinasebc7e212018-05-11 13:33:12 +010091 return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
Catalin Marinasa41dc0e2014-04-03 17:48:54 +010092}
93
Shaokun Zhang7b8c87b2019-05-28 10:16:54 +080094int cache_line_size(void);
Catalin Marinasa41dc0e2014-04-03 17:48:54 +010095
Suzuki K Poulose1602df02018-10-09 14:47:06 +010096/*
97 * Read the effective value of CTR_EL0.
98 *
99 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
100 * section D10.2.33 "CTR_EL0, Cache Type Register" :
101 *
102 * CTR_EL0.IDC reports the data cache clean requirements for
103 * instruction to data coherence.
104 *
105 * 0 - dcache clean to PoU is required unless :
106 * (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
107 * 1 - dcache clean to PoU is not required for i-to-d coherence.
108 *
109 * This routine provides the CTR_EL0 with the IDC field updated to the
110 * effective state.
111 */
112static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
113{
114 u32 ctr = read_cpuid_cachetype();
115
116 if (!(ctr & BIT(CTR_IDC_SHIFT))) {
117 u64 clidr = read_sysreg(clidr_el1);
118
119 if (CLIDR_LOC(clidr) == 0 ||
120 (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
121 ctr |= BIT(CTR_IDC_SHIFT);
122 }
123
124 return ctr;
125}
126
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100127#endif /* __ASSEMBLY__ */
Catalin Marinasf1a0c4a2012-03-05 11:49:28 +0000128
129#endif