Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / kernel / common / 1a422724c6995004d0b9e95596ec4623e8ca1fc2 / . / arch / arm / mach-omap2 / clockdomains44xx.h
blob: 6fc55e4ed2b5ee76c316f0ca0d4c3d3389d32a35 [file] [log] [blame]
Abhijit Pagare30b88632010-01-26 20:12:54 -0700[diff] [blame]1/*
2 * OMAP4 Clock domains framework
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation
6 *
7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
Abhijit Pagare1a422722010-01-26 20:12:54 -0700[diff] [blame^]21/*
22 * To-Do List
23 * -> Populate the Sleep/Wakeup dependencies for the domains
24 */
25
Abhijit Pagare30b88632010-01-26 20:12:54 -0700[diff] [blame]26#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
27#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
28
29#include <plat/clockdomain.h>
30
31#if defined(CONFIG_ARCH_OMAP4)
32
33static struct clockdomain l4_cefuse_44xx_clkdm = {
34 .name = "l4_cefuse_clkdm",
35 .pwrdm = { .name = "cefuse_pwrdm" },
36 .clkstctrl_reg = OMAP4430_CM_CEFUSE_CLKSTCTRL,
37 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
38 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
39 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
40};
41
42static struct clockdomain l4_cfg_44xx_clkdm = {
43 .name = "l4_cfg_clkdm",
44 .pwrdm = { .name = "core_pwrdm" },
45 .clkstctrl_reg = OMAP4430_CM_L4CFG_CLKSTCTRL,
46 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
47 .flags = CLKDM_CAN_HWSUP,
48 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
49};
50
51static struct clockdomain tesla_44xx_clkdm = {
52 .name = "tesla_clkdm",
53 .pwrdm = { .name = "tesla_pwrdm" },
54 .clkstctrl_reg = OMAP4430_CM_TESLA_CLKSTCTRL,
55 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
56 .flags = CLKDM_CAN_HWSUP_SWSUP,
57 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
58};
59
60static struct clockdomain l3_gfx_44xx_clkdm = {
61 .name = "l3_gfx_clkdm",
62 .pwrdm = { .name = "gfx_pwrdm" },
63 .clkstctrl_reg = OMAP4430_CM_GFX_CLKSTCTRL,
64 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
65 .flags = CLKDM_CAN_HWSUP_SWSUP,
66 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
67};
68
69static struct clockdomain ivahd_44xx_clkdm = {
70 .name = "ivahd_clkdm",
71 .pwrdm = { .name = "ivahd_pwrdm" },
72 .clkstctrl_reg = OMAP4430_CM_IVAHD_CLKSTCTRL,
73 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
74 .flags = CLKDM_CAN_HWSUP_SWSUP,
75 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
76};
77
78static struct clockdomain l4_secure_44xx_clkdm = {
79 .name = "l4_secure_clkdm",
80 .pwrdm = { .name = "l4per_pwrdm" },
81 .clkstctrl_reg = OMAP4430_CM_L4SEC_CLKSTCTRL,
82 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
83 .flags = CLKDM_CAN_HWSUP_SWSUP,
84 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
85};
86
87static struct clockdomain l4_per_44xx_clkdm = {
88 .name = "l4_per_clkdm",
89 .pwrdm = { .name = "l4per_pwrdm" },
90 .clkstctrl_reg = OMAP4430_CM_L4PER_CLKSTCTRL,
91 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
92 .flags = CLKDM_CAN_HWSUP_SWSUP,
93 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
94};
95
96static struct clockdomain abe_44xx_clkdm = {
97 .name = "abe_clkdm",
98 .pwrdm = { .name = "abe_pwrdm" },
99 .clkstctrl_reg = OMAP4430_CM1_ABE_CLKSTCTRL,
100 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
101 .flags = CLKDM_CAN_HWSUP_SWSUP,
102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
103};
104
105static struct clockdomain l3_init_44xx_clkdm = {
106 .name = "l3_init_clkdm",
107 .pwrdm = { .name = "l3init_pwrdm" },
108 .clkstctrl_reg = OMAP4430_CM_L3INIT_CLKSTCTRL,
109 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
110 .flags = CLKDM_CAN_HWSUP_SWSUP,
111 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
112};
113
114static struct clockdomain mpuss_44xx_clkdm = {
115 .name = "mpuss_clkdm",
116 .pwrdm = { .name = "mpu_pwrdm" },
117 .clkstctrl_reg = OMAP4430_CM_MPU_CLKSTCTRL,
118 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
119 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
120 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
121};
122
123static struct clockdomain mpu0_44xx_clkdm = {
124 .name = "mpu0_clkdm",
125 .pwrdm = { .name = "cpu0_pwrdm" },
126 .clkstctrl_reg = OMAP4430_CM_PDA_CPU0_CLKSTCTRL,
127 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
128 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
129 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
130};
131
132static struct clockdomain mpu1_44xx_clkdm = {
133 .name = "mpu1_clkdm",
134 .pwrdm = { .name = "cpu1_pwrdm" },
135 .clkstctrl_reg = OMAP4430_CM_PDA_CPU1_CLKSTCTRL,
136 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
137 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
138 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
139};
140
141static struct clockdomain l3_emif_44xx_clkdm = {
142 .name = "l3_emif_clkdm",
143 .pwrdm = { .name = "core_pwrdm" },
144 .clkstctrl_reg = OMAP4430_CM_MEMIF_CLKSTCTRL,
145 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
146 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
147 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
148};
149
150static struct clockdomain l4_ao_44xx_clkdm = {
151 .name = "l4_ao_clkdm",
152 .pwrdm = { .name = "always_on_core_pwrdm" },
153 .clkstctrl_reg = OMAP4430_CM_ALWON_CLKSTCTRL,
154 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
155 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
156 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
157};
158
159static struct clockdomain ducati_44xx_clkdm = {
160 .name = "ducati_clkdm",
161 .pwrdm = { .name = "core_pwrdm" },
162 .clkstctrl_reg = OMAP4430_CM_DUCATI_CLKSTCTRL,
163 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
164 .flags = CLKDM_CAN_HWSUP_SWSUP,
165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
166};
167
168static struct clockdomain l3_2_44xx_clkdm = {
169 .name = "l3_2_clkdm",
170 .pwrdm = { .name = "core_pwrdm" },
171 .clkstctrl_reg = OMAP4430_CM_L3_2_CLKSTCTRL,
172 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
173 .flags = CLKDM_CAN_HWSUP,
174 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
175};
176
177static struct clockdomain l3_1_44xx_clkdm = {
178 .name = "l3_1_clkdm",
179 .pwrdm = { .name = "core_pwrdm" },
180 .clkstctrl_reg = OMAP4430_CM_L3_1_CLKSTCTRL,
181 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
182 .flags = CLKDM_CAN_HWSUP,
183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
184};
185
186static struct clockdomain l3_d2d_44xx_clkdm = {
187 .name = "l3_d2d_clkdm",
188 .pwrdm = { .name = "core_pwrdm" },
189 .clkstctrl_reg = OMAP4430_CM_D2D_CLKSTCTRL,
190 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
191 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
192 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
193};
194
195static struct clockdomain iss_44xx_clkdm = {
196 .name = "iss_clkdm",
197 .pwrdm = { .name = "cam_pwrdm" },
198 .clkstctrl_reg = OMAP4430_CM_CAM_CLKSTCTRL,
199 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
200 .flags = CLKDM_CAN_HWSUP_SWSUP,
201 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
202};
203
204static struct clockdomain l3_dss_44xx_clkdm = {
205 .name = "l3_dss_clkdm",
206 .pwrdm = { .name = "dss_pwrdm" },
207 .clkstctrl_reg = OMAP4430_CM_DSS_CLKSTCTRL,
208 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
209 .flags = CLKDM_CAN_HWSUP_SWSUP,
210 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
211};
212
213static struct clockdomain l4_wkup_44xx_clkdm = {
214 .name = "l4_wkup_clkdm",
215 .pwrdm = { .name = "wkup_pwrdm" },
216 .clkstctrl_reg = OMAP4430_CM_WKUP_CLKSTCTRL,
217 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
218 .flags = CLKDM_CAN_HWSUP,
219 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
220};
221
222static struct clockdomain emu_sys_44xx_clkdm = {
223 .name = "emu_sys_clkdm",
224 .pwrdm = { .name = "emu_pwrdm" },
225 .clkstctrl_reg = OMAP4430_CM_EMU_CLKSTCTRL,
226 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
227 .flags = CLKDM_CAN_HWSUP,
228 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
229};
230
231static struct clockdomain l3_dma_44xx_clkdm = {
232 .name = "l3_dma_clkdm",
233 .pwrdm = { .name = "core_pwrdm" },
234 .clkstctrl_reg = OMAP4430_CM_SDMA_CLKSTCTRL,
235 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
236 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
237 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
238};
239
240#endif
241
242#endif