Andy Shevchenko | 3d588f8 | 2014-09-23 17:18:11 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Driver for the Synopsys DesignWare DMA Controller |
| 3 | * |
| 4 | * Copyright (C) 2007 Atmel Corporation |
| 5 | * Copyright (C) 2010-2011 ST Microelectronics |
Andy Shevchenko | 2a52f6e | 2014-09-23 17:18:15 +0300 | [diff] [blame] | 6 | * Copyright (C) 2014 Intel Corporation |
Andy Shevchenko | 3d588f8 | 2014-09-23 17:18:11 +0300 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | #ifndef _DMA_DW_H |
| 13 | #define _DMA_DW_H |
| 14 | |
Andy Shevchenko | 2a52f6e | 2014-09-23 17:18:15 +0300 | [diff] [blame] | 15 | #include <linux/clk.h> |
| 16 | #include <linux/device.h> |
Andy Shevchenko | 3d588f8 | 2014-09-23 17:18:11 +0300 | [diff] [blame] | 17 | #include <linux/dmaengine.h> |
| 18 | |
Andy Shevchenko | 2a52f6e | 2014-09-23 17:18:15 +0300 | [diff] [blame] | 19 | #include <linux/platform_data/dma-dw.h> |
| 20 | |
| 21 | struct dw_dma; |
| 22 | |
| 23 | /** |
| 24 | * struct dw_dma_chip - representation of DesignWare DMA controller hardware |
| 25 | * @dev: struct device of the DMA controller |
| 26 | * @irq: irq line |
| 27 | * @regs: memory mapped I/O space |
| 28 | * @clk: hclk clock |
| 29 | * @dw: struct dw_dma that is filed by dw_dma_probe() |
Andy Shevchenko | 3a14c66 | 2016-04-27 14:15:40 +0300 | [diff] [blame] | 30 | * @pdata: pointer to platform data |
Andy Shevchenko | 2a52f6e | 2014-09-23 17:18:15 +0300 | [diff] [blame] | 31 | */ |
| 32 | struct dw_dma_chip { |
| 33 | struct device *dev; |
| 34 | int irq; |
| 35 | void __iomem *regs; |
| 36 | struct clk *clk; |
| 37 | struct dw_dma *dw; |
Andy Shevchenko | 3a14c66 | 2016-04-27 14:15:40 +0300 | [diff] [blame] | 38 | |
| 39 | const struct dw_dma_platform_data *pdata; |
Andy Shevchenko | 2a52f6e | 2014-09-23 17:18:15 +0300 | [diff] [blame] | 40 | }; |
| 41 | |
| 42 | /* Export to the platform drivers */ |
Andy Shevchenko | 19d8291 | 2016-08-17 19:20:23 +0300 | [diff] [blame^] | 43 | #if IS_ENABLED(CONFIG_DW_DMAC_CORE) |
Andy Shevchenko | 3a14c66 | 2016-04-27 14:15:40 +0300 | [diff] [blame] | 44 | int dw_dma_probe(struct dw_dma_chip *chip); |
Andy Shevchenko | 2a52f6e | 2014-09-23 17:18:15 +0300 | [diff] [blame] | 45 | int dw_dma_remove(struct dw_dma_chip *chip); |
Andy Shevchenko | 19d8291 | 2016-08-17 19:20:23 +0300 | [diff] [blame^] | 46 | #else |
| 47 | static inline int dw_dma_probe(struct dw_dma_chip *chip) { return -ENODEV; } |
| 48 | static inline int dw_dma_remove(struct dw_dma_chip *chip) { return 0; } |
| 49 | #endif /* CONFIG_DW_DMAC_CORE */ |
Andy Shevchenko | 2a52f6e | 2014-09-23 17:18:15 +0300 | [diff] [blame] | 50 | |
Andy Shevchenko | 3d588f8 | 2014-09-23 17:18:11 +0300 | [diff] [blame] | 51 | /* DMA API extensions */ |
| 52 | struct dw_desc; |
| 53 | |
| 54 | struct dw_cyclic_desc { |
| 55 | struct dw_desc **desc; |
| 56 | unsigned long periods; |
| 57 | void (*period_callback)(void *param); |
| 58 | void *period_callback_param; |
| 59 | }; |
| 60 | |
| 61 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, |
| 62 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, |
| 63 | enum dma_transfer_direction direction); |
| 64 | void dw_dma_cyclic_free(struct dma_chan *chan); |
| 65 | int dw_dma_cyclic_start(struct dma_chan *chan); |
| 66 | void dw_dma_cyclic_stop(struct dma_chan *chan); |
| 67 | |
| 68 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan); |
| 69 | |
| 70 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan); |
| 71 | |
| 72 | #endif /* _DMA_DW_H */ |