| Katsuhiro Suzuki | f37fe2f | 2018-01-19 18:25:29 +0900 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Socionext UniPhier AIO ALSA driver. |
| 4 | * |
| 5 | * Copyright (c) 2016-2018 Socionext Inc. |
| Katsuhiro Suzuki | f37fe2f | 2018-01-19 18:25:29 +0900 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef SND_UNIPHIER_AIO_REG_H__ |
| 9 | #define SND_UNIPHIER_AIO_REG_H__ |
| 10 | |
| 11 | #include <linux/bitops.h> |
| 12 | |
| Katsuhiro Suzuki | 7c3c20f | 2018-03-16 16:08:13 +0900 | [diff] [blame] | 13 | /* soc-glue */ |
| 14 | #define SG_AOUTEN 0x1c04 |
| 15 | |
| Katsuhiro Suzuki | f37fe2f | 2018-01-19 18:25:29 +0900 | [diff] [blame] | 16 | /* SW view */ |
| 17 | #define A2CHNMAPCTR0(n) (0x00000 + 0x40 * (n)) |
| 18 | #define A2RBNMAPCTR0(n) (0x01000 + 0x40 * (n)) |
| 19 | #define A2IPORTNMAPCTR0(n) (0x02000 + 0x40 * (n)) |
| 20 | #define A2IPORTNMAPCTR1(n) (0x02004 + 0x40 * (n)) |
| 21 | #define A2IIFNMAPCTR0(n) (0x03000 + 0x40 * (n)) |
| 22 | #define A2OPORTNMAPCTR0(n) (0x04000 + 0x40 * (n)) |
| 23 | #define A2OPORTNMAPCTR1(n) (0x04004 + 0x40 * (n)) |
| 24 | #define A2OPORTNMAPCTR2(n) (0x04008 + 0x40 * (n)) |
| 25 | #define A2OIFNMAPCTR0(n) (0x05000 + 0x40 * (n)) |
| 26 | #define A2ATNMAPCTR0(n) (0x06000 + 0x40 * (n)) |
| 27 | |
| 28 | #define MAPCTR0_EN 0x80000000 |
| 29 | |
| 30 | /* CTL */ |
| 31 | #define A2APLLCTR0 0x07000 |
| 32 | #define A2APLLCTR0_APLLXPOW_MASK GENMASK(3, 0) |
| 33 | #define A2APLLCTR0_APLLXPOW_PWOFF (0x0 << 0) |
| 34 | #define A2APLLCTR0_APLLXPOW_PWON (0xf << 0) |
| 35 | #define A2APLLCTR1 0x07004 |
| 36 | #define A2APLLCTR1_APLLX_MASK 0x00010101 |
| 37 | #define A2APLLCTR1_APLLX_36MHZ 0x00000000 |
| 38 | #define A2APLLCTR1_APLLX_33MHZ 0x00000001 |
| 39 | #define A2EXMCLKSEL0 0x07030 |
| 40 | #define A2EXMCLKSEL0_EXMCLK_MASK GENMASK(2, 0) |
| 41 | #define A2EXMCLKSEL0_EXMCLK_OUTPUT (0x0 << 0) |
| 42 | #define A2EXMCLKSEL0_EXMCLK_INPUT (0x7 << 0) |
| 43 | #define A2SSIFSW 0x07050 |
| 44 | #define A2CH22_2CTR 0x07054 |
| 45 | #define A2AIOINPUTSEL 0x070e0 |
| 46 | #define A2AIOINPUTSEL_RXSEL_PCMI1_MASK GENMASK(2, 0) |
| 47 | #define A2AIOINPUTSEL_RXSEL_PCMI1_HDMIRX1 (0x2 << 0) |
| 48 | #define A2AIOINPUTSEL_RXSEL_PCMI2_MASK GENMASK(6, 4) |
| 49 | #define A2AIOINPUTSEL_RXSEL_PCMI2_SIF (0x7 << 4) |
| 50 | #define A2AIOINPUTSEL_RXSEL_PCMI3_MASK GENMASK(10, 8) |
| 51 | #define A2AIOINPUTSEL_RXSEL_PCMI3_EVEA (0x1 << 8) |
| 52 | #define A2AIOINPUTSEL_RXSEL_IECI1_MASK GENMASK(14, 12) |
| 53 | #define A2AIOINPUTSEL_RXSEL_IECI1_HDMIRX1 (0x2 << 12) |
| 54 | #define A2AIOINPUTSEL_RXSEL_MASK (A2AIOINPUTSEL_RXSEL_PCMI1_MASK | \ |
| 55 | A2AIOINPUTSEL_RXSEL_PCMI2_MASK | \ |
| 56 | A2AIOINPUTSEL_RXSEL_PCMI3_MASK | \ |
| 57 | A2AIOINPUTSEL_RXSEL_IECI1_HDMIRX1) |
| 58 | |
| 59 | /* INTC */ |
| 60 | #define INTCHIM(m) (0x9028 + 0x80 * (m)) |
| 61 | #define INTRBIM(m) (0x9030 + 0x80 * (m)) |
| 62 | #define INTCHID(m) (0xa028 + 0x80 * (m)) |
| 63 | #define INTRBID(m) (0xa030 + 0x80 * (m)) |
| 64 | |
| 65 | /* AIN(PCMINN) */ |
| 66 | #define IPORTMXCTR1(n) (0x22000 + 0x400 * (n)) |
| 67 | #define IPORTMXCTR1_LRSEL_MASK GENMASK(11, 10) |
| 68 | #define IPORTMXCTR1_LRSEL_RIGHT (0x0 << 10) |
| 69 | #define IPORTMXCTR1_LRSEL_LEFT (0x1 << 10) |
| 70 | #define IPORTMXCTR1_LRSEL_I2S (0x2 << 10) |
| 71 | #define IPORTMXCTR1_OUTBITSEL_MASK (0x800003U << 8) |
| 72 | #define IPORTMXCTR1_OUTBITSEL_32 (0x800000U << 8) |
| 73 | #define IPORTMXCTR1_OUTBITSEL_24 (0x000000U << 8) |
| 74 | #define IPORTMXCTR1_OUTBITSEL_20 (0x000001U << 8) |
| 75 | #define IPORTMXCTR1_OUTBITSEL_16 (0x000002U << 8) |
| 76 | #define IPORTMXCTR1_CHSEL_MASK GENMASK(6, 4) |
| 77 | #define IPORTMXCTR1_CHSEL_ALL (0x0 << 4) |
| 78 | #define IPORTMXCTR1_CHSEL_D0_D2 (0x1 << 4) |
| 79 | #define IPORTMXCTR1_CHSEL_D0 (0x2 << 4) |
| 80 | #define IPORTMXCTR1_CHSEL_D1 (0x3 << 4) |
| 81 | #define IPORTMXCTR1_CHSEL_D2 (0x4 << 4) |
| 82 | #define IPORTMXCTR1_CHSEL_DMIX (0x5 << 4) |
| 83 | #define IPORTMXCTR1_FSSEL_MASK GENMASK(3, 0) |
| 84 | #define IPORTMXCTR1_FSSEL_48 (0x0 << 0) |
| 85 | #define IPORTMXCTR1_FSSEL_96 (0x1 << 0) |
| 86 | #define IPORTMXCTR1_FSSEL_192 (0x2 << 0) |
| 87 | #define IPORTMXCTR1_FSSEL_32 (0x3 << 0) |
| 88 | #define IPORTMXCTR1_FSSEL_44_1 (0x4 << 0) |
| 89 | #define IPORTMXCTR1_FSSEL_88_2 (0x5 << 0) |
| 90 | #define IPORTMXCTR1_FSSEL_176_4 (0x6 << 0) |
| 91 | #define IPORTMXCTR1_FSSEL_16 (0x8 << 0) |
| 92 | #define IPORTMXCTR1_FSSEL_22_05 (0x9 << 0) |
| 93 | #define IPORTMXCTR1_FSSEL_24 (0xa << 0) |
| 94 | #define IPORTMXCTR1_FSSEL_8 (0xb << 0) |
| 95 | #define IPORTMXCTR1_FSSEL_11_025 (0xc << 0) |
| 96 | #define IPORTMXCTR1_FSSEL_12 (0xd << 0) |
| 97 | #define IPORTMXCTR2(n) (0x22004 + 0x400 * (n)) |
| 98 | #define IPORTMXCTR2_ACLKSEL_MASK GENMASK(19, 16) |
| 99 | #define IPORTMXCTR2_ACLKSEL_A1 (0x0 << 16) |
| 100 | #define IPORTMXCTR2_ACLKSEL_F1 (0x1 << 16) |
| 101 | #define IPORTMXCTR2_ACLKSEL_A2 (0x2 << 16) |
| 102 | #define IPORTMXCTR2_ACLKSEL_F2 (0x3 << 16) |
| 103 | #define IPORTMXCTR2_ACLKSEL_A2PLL (0x4 << 16) |
| 104 | #define IPORTMXCTR2_ACLKSEL_RX1 (0x5 << 16) |
| 105 | #define IPORTMXCTR2_ACLKSEL_RX2 (0x6 << 16) |
| 106 | #define IPORTMXCTR2_MSSEL_MASK BIT(15) |
| 107 | #define IPORTMXCTR2_MSSEL_SLAVE (0x0 << 15) |
| 108 | #define IPORTMXCTR2_MSSEL_MASTER (0x1 << 15) |
| 109 | #define IPORTMXCTR2_EXTLSIFSSEL_MASK BIT(14) |
| 110 | #define IPORTMXCTR2_EXTLSIFSSEL_36 (0x0 << 14) |
| 111 | #define IPORTMXCTR2_EXTLSIFSSEL_24 (0x1 << 14) |
| 112 | #define IPORTMXCTR2_DACCKSEL_MASK GENMASK(9, 8) |
| 113 | #define IPORTMXCTR2_DACCKSEL_1_2 (0x0 << 8) |
| 114 | #define IPORTMXCTR2_DACCKSEL_1_3 (0x1 << 8) |
| 115 | #define IPORTMXCTR2_DACCKSEL_1_1 (0x2 << 8) |
| 116 | #define IPORTMXCTR2_DACCKSEL_2_3 (0x3 << 8) |
| 117 | #define IPORTMXCTR2_REQEN_MASK BIT(0) |
| 118 | #define IPORTMXCTR2_REQEN_DISABLE (0x0 << 0) |
| 119 | #define IPORTMXCTR2_REQEN_ENABLE (0x1 << 0) |
| 120 | #define IPORTMXCNTCTR(n) (0x22010 + 0x400 * (n)) |
| 121 | #define IPORTMXCOUNTER(n) (0x22014 + 0x400 * (n)) |
| 122 | #define IPORTMXCNTMONI(n) (0x22018 + 0x400 * (n)) |
| 123 | #define IPORTMXACLKSEL0EX(n) (0x22020 + 0x400 * (n)) |
| 124 | #define IPORTMXACLKSEL0EX_ACLKSEL0EX_MASK GENMASK(3, 0) |
| 125 | #define IPORTMXACLKSEL0EX_ACLKSEL0EX_INTERNAL (0x0 << 0) |
| 126 | #define IPORTMXACLKSEL0EX_ACLKSEL0EX_EXTERNAL (0xf << 0) |
| 127 | #define IPORTMXEXNOE(n) (0x22070 + 0x400 * (n)) |
| 128 | #define IPORTMXEXNOE_PCMINOE_MASK BIT(0) |
| 129 | #define IPORTMXEXNOE_PCMINOE_OUTPUT (0x0 << 0) |
| 130 | #define IPORTMXEXNOE_PCMINOE_INPUT (0x1 << 0) |
| 131 | #define IPORTMXMASK(n) (0x22078 + 0x400 * (n)) |
| 132 | #define IPORTMXMASK_IUXCKMSK_MASK GENMASK(18, 16) |
| 133 | #define IPORTMXMASK_IUXCKMSK_ON (0x0 << 16) |
| 134 | #define IPORTMXMASK_IUXCKMSK_OFF (0x7 << 16) |
| 135 | #define IPORTMXMASK_XCKMSK_MASK GENMASK(2, 0) |
| 136 | #define IPORTMXMASK_XCKMSK_ON (0x0 << 0) |
| 137 | #define IPORTMXMASK_XCKMSK_OFF (0x7 << 0) |
| 138 | #define IPORTMXRSTCTR(n) (0x2207c + 0x400 * (n)) |
| 139 | #define IPORTMXRSTCTR_RSTPI_MASK BIT(7) |
| 140 | #define IPORTMXRSTCTR_RSTPI_RELEASE (0x0 << 7) |
| 141 | #define IPORTMXRSTCTR_RSTPI_RESET (0x1 << 7) |
| 142 | |
| 143 | /* AIN(PBinMX) */ |
| 144 | #define PBINMXCTR(n) (0x20200 + 0x40 * (n)) |
| 145 | #define PBINMXCTR_NCONNECT_MASK BIT(15) |
| 146 | #define PBINMXCTR_NCONNECT_CONNECT (0x0 << 15) |
| 147 | #define PBINMXCTR_NCONNECT_DISCONNECT (0x1 << 15) |
| 148 | #define PBINMXCTR_INOUTSEL_MASK BIT(14) |
| 149 | #define PBINMXCTR_INOUTSEL_IN (0x0 << 14) |
| 150 | #define PBINMXCTR_INOUTSEL_OUT (0x1 << 14) |
| 151 | #define PBINMXCTR_PBINSEL_SHIFT (8) |
| 152 | #define PBINMXCTR_ENDIAN_MASK GENMASK(5, 4) |
| 153 | #define PBINMXCTR_ENDIAN_3210 (0x0 << 4) |
| 154 | #define PBINMXCTR_ENDIAN_0123 (0x1 << 4) |
| 155 | #define PBINMXCTR_ENDIAN_1032 (0x2 << 4) |
| 156 | #define PBINMXCTR_ENDIAN_2301 (0x3 << 4) |
| 157 | #define PBINMXCTR_MEMFMT_MASK GENMASK(3, 0) |
| 158 | #define PBINMXCTR_MEMFMT_D0 (0x0 << 0) |
| 159 | #define PBINMXCTR_MEMFMT_5_1CH_DMIX (0x1 << 0) |
| 160 | #define PBINMXCTR_MEMFMT_6CH (0x2 << 0) |
| 161 | #define PBINMXCTR_MEMFMT_4CH (0x3 << 0) |
| 162 | #define PBINMXCTR_MEMFMT_DMIX (0x4 << 0) |
| 163 | #define PBINMXCTR_MEMFMT_1CH (0x5 << 0) |
| 164 | #define PBINMXCTR_MEMFMT_16LR (0x6 << 0) |
| 165 | #define PBINMXCTR_MEMFMT_7_1CH (0x7 << 0) |
| 166 | #define PBINMXCTR_MEMFMT_7_1CH_DMIX (0x8 << 0) |
| 167 | #define PBINMXCTR_MEMFMT_STREAM (0xf << 0) |
| 168 | #define PBINMXPAUSECTR0(n) (0x20204 + 0x40 * (n)) |
| 169 | #define PBINMXPAUSECTR1(n) (0x20208 + 0x40 * (n)) |
| 170 | |
| 171 | /* AOUT */ |
| Katsuhiro Suzuki | 5a748de | 2018-05-08 12:16:39 +0900 | [diff] [blame] | 172 | #define AOUTFADECTR0 0x40020 |
| Katsuhiro Suzuki | f37fe2f | 2018-01-19 18:25:29 +0900 | [diff] [blame] | 173 | #define AOUTENCTR0 0x40040 |
| 174 | #define AOUTENCTR1 0x40044 |
| 175 | #define AOUTENCTR2 0x40048 |
| 176 | #define AOUTRSTCTR0 0x40060 |
| 177 | #define AOUTRSTCTR1 0x40064 |
| 178 | #define AOUTRSTCTR2 0x40068 |
| 179 | #define AOUTSRCRSTCTR0 0x400c0 |
| 180 | #define AOUTSRCRSTCTR1 0x400c4 |
| 181 | #define AOUTSRCRSTCTR2 0x400c8 |
| 182 | |
| Katsuhiro Suzuki | 5a748de | 2018-05-08 12:16:39 +0900 | [diff] [blame] | 183 | /* AOUT PCMOUT has 5 slots, slot0-3: D0-3, slot4: DMIX */ |
| 184 | #define OPORT_SLOT_MAX 5 |
| 185 | |
| Katsuhiro Suzuki | f37fe2f | 2018-01-19 18:25:29 +0900 | [diff] [blame] | 186 | /* AOUT(PCMOUTN) */ |
| 187 | #define OPORTMXCTR1(n) (0x42000 + 0x400 * (n)) |
| 188 | #define OPORTMXCTR1_I2SLRSEL_MASK (0x11 << 10) |
| 189 | #define OPORTMXCTR1_I2SLRSEL_RIGHT (0x00 << 10) |
| 190 | #define OPORTMXCTR1_I2SLRSEL_LEFT (0x01 << 10) |
| 191 | #define OPORTMXCTR1_I2SLRSEL_I2S (0x11 << 10) |
| 192 | #define OPORTMXCTR1_OUTBITSEL_MASK (0x800003U << 8) |
| 193 | #define OPORTMXCTR1_OUTBITSEL_32 (0x800000U << 8) |
| 194 | #define OPORTMXCTR1_OUTBITSEL_24 (0x000000U << 8) |
| 195 | #define OPORTMXCTR1_OUTBITSEL_20 (0x000001U << 8) |
| 196 | #define OPORTMXCTR1_OUTBITSEL_16 (0x000002U << 8) |
| 197 | #define OPORTMXCTR1_FSSEL_MASK GENMASK(3, 0) |
| 198 | #define OPORTMXCTR1_FSSEL_48 (0x0 << 0) |
| 199 | #define OPORTMXCTR1_FSSEL_96 (0x1 << 0) |
| 200 | #define OPORTMXCTR1_FSSEL_192 (0x2 << 0) |
| 201 | #define OPORTMXCTR1_FSSEL_32 (0x3 << 0) |
| 202 | #define OPORTMXCTR1_FSSEL_44_1 (0x4 << 0) |
| 203 | #define OPORTMXCTR1_FSSEL_88_2 (0x5 << 0) |
| 204 | #define OPORTMXCTR1_FSSEL_176_4 (0x6 << 0) |
| 205 | #define OPORTMXCTR1_FSSEL_16 (0x8 << 0) |
| 206 | #define OPORTMXCTR1_FSSEL_22_05 (0x9 << 0) |
| 207 | #define OPORTMXCTR1_FSSEL_24 (0xa << 0) |
| 208 | #define OPORTMXCTR1_FSSEL_8 (0xb << 0) |
| 209 | #define OPORTMXCTR1_FSSEL_11_025 (0xc << 0) |
| 210 | #define OPORTMXCTR1_FSSEL_12 (0xd << 0) |
| 211 | #define OPORTMXCTR2(n) (0x42004 + 0x400 * (n)) |
| 212 | #define OPORTMXCTR2_ACLKSEL_MASK GENMASK(19, 16) |
| 213 | #define OPORTMXCTR2_ACLKSEL_A1 (0x0 << 16) |
| 214 | #define OPORTMXCTR2_ACLKSEL_F1 (0x1 << 16) |
| 215 | #define OPORTMXCTR2_ACLKSEL_A2 (0x2 << 16) |
| 216 | #define OPORTMXCTR2_ACLKSEL_F2 (0x3 << 16) |
| 217 | #define OPORTMXCTR2_ACLKSEL_A2PLL (0x4 << 16) |
| 218 | #define OPORTMXCTR2_ACLKSEL_RX1 (0x5 << 16) |
| 219 | #define OPORTMXCTR2_ACLKSEL_RX2 (0x6 << 16) |
| 220 | #define OPORTMXCTR2_MSSEL_MASK BIT(15) |
| 221 | #define OPORTMXCTR2_MSSEL_SLAVE (0x0 << 15) |
| 222 | #define OPORTMXCTR2_MSSEL_MASTER (0x1 << 15) |
| 223 | #define OPORTMXCTR2_EXTLSIFSSEL_MASK BIT(14) |
| 224 | #define OPORTMXCTR2_EXTLSIFSSEL_36 (0x0 << 14) |
| 225 | #define OPORTMXCTR2_EXTLSIFSSEL_24 (0x1 << 14) |
| 226 | #define OPORTMXCTR2_DACCKSEL_MASK GENMASK(9, 8) |
| 227 | #define OPORTMXCTR2_DACCKSEL_1_2 (0x0 << 8) |
| 228 | #define OPORTMXCTR2_DACCKSEL_1_3 (0x1 << 8) |
| 229 | #define OPORTMXCTR2_DACCKSEL_1_1 (0x2 << 8) |
| 230 | #define OPORTMXCTR2_DACCKSEL_2_3 (0x3 << 8) |
| 231 | #define OPORTMXCTR3(n) (0x42008 + 0x400 * (n)) |
| 232 | #define OPORTMXCTR3_IECTHUR_MASK BIT(19) |
| 233 | #define OPORTMXCTR3_IECTHUR_IECOUT (0x0 << 19) |
| 234 | #define OPORTMXCTR3_IECTHUR_IECIN (0x1 << 19) |
| 235 | #define OPORTMXCTR3_SRCSEL_MASK GENMASK(18, 16) |
| 236 | #define OPORTMXCTR3_SRCSEL_PCM (0x0 << 16) |
| 237 | #define OPORTMXCTR3_SRCSEL_STREAM (0x1 << 16) |
| 238 | #define OPORTMXCTR3_SRCSEL_CDDTS (0x2 << 16) |
| 239 | #define OPORTMXCTR3_VALID_MASK BIT(12) |
| 240 | #define OPORTMXCTR3_VALID_PCM (0x0 << 12) |
| 241 | #define OPORTMXCTR3_VALID_STREAM (0x1 << 12) |
| 242 | #define OPORTMXCTR3_PMSEL_MASK BIT(3) |
| 243 | #define OPORTMXCTR3_PMSEL_MUTE (0x0 << 3) |
| 244 | #define OPORTMXCTR3_PMSEL_PAUSE (0x1 << 3) |
| 245 | #define OPORTMXCTR3_PMSW_MASK BIT(2) |
| 246 | #define OPORTMXCTR3_PMSW_MUTE_OFF (0x0 << 2) |
| 247 | #define OPORTMXCTR3_PMSW_MUTE_ON (0x1 << 2) |
| 248 | #define OPORTMXSRC1CTR(n) (0x4200c + 0x400 * (n)) |
| 249 | #define OPORTMXSRC1CTR_FSIIPNUM_SHIFT (24) |
| 250 | #define OPORTMXSRC1CTR_THMODE_MASK BIT(23) |
| 251 | #define OPORTMXSRC1CTR_THMODE_SRC (0x0 << 23) |
| 252 | #define OPORTMXSRC1CTR_THMODE_BYPASS (0x1 << 23) |
| 253 | #define OPORTMXSRC1CTR_LOCK_MASK BIT(16) |
| 254 | #define OPORTMXSRC1CTR_LOCK_UNLOCK (0x0 << 16) |
| 255 | #define OPORTMXSRC1CTR_LOCK_LOCK (0x1 << 16) |
| 256 | #define OPORTMXSRC1CTR_SRCPATH_MASK BIT(15) |
| 257 | #define OPORTMXSRC1CTR_SRCPATH_BYPASS (0x0 << 15) |
| 258 | #define OPORTMXSRC1CTR_SRCPATH_CALC (0x1 << 15) |
| 259 | #define OPORTMXSRC1CTR_SYNC_MASK BIT(14) |
| 260 | #define OPORTMXSRC1CTR_SYNC_ASYNC (0x0 << 14) |
| 261 | #define OPORTMXSRC1CTR_SYNC_SYNC (0x1 << 14) |
| 262 | #define OPORTMXSRC1CTR_FSOCK_MASK GENMASK(11, 10) |
| 263 | #define OPORTMXSRC1CTR_FSOCK_44_1 (0x0 << 10) |
| 264 | #define OPORTMXSRC1CTR_FSOCK_48 (0x1 << 10) |
| 265 | #define OPORTMXSRC1CTR_FSOCK_32 (0x2 << 10) |
| 266 | #define OPORTMXSRC1CTR_FSICK_MASK GENMASK(9, 8) |
| 267 | #define OPORTMXSRC1CTR_FSICK_44_1 (0x0 << 8) |
| 268 | #define OPORTMXSRC1CTR_FSICK_48 (0x1 << 8) |
| 269 | #define OPORTMXSRC1CTR_FSICK_32 (0x2 << 8) |
| 270 | #define OPORTMXSRC1CTR_FSIIPSEL_MASK GENMASK(5, 4) |
| 271 | #define OPORTMXSRC1CTR_FSIIPSEL_INNER (0x0 << 4) |
| 272 | #define OPORTMXSRC1CTR_FSIIPSEL_OUTER (0x1 << 4) |
| 273 | #define OPORTMXSRC1CTR_FSISEL_MASK GENMASK(3, 0) |
| 274 | #define OPORTMXSRC1CTR_FSISEL_ACLK (0x0 << 0) |
| 275 | #define OPORTMXSRC1CTR_FSISEL_DD (0x1 << 0) |
| 276 | #define OPORTMXDSDMUTEDAT(n) (0x42020 + 0x400 * (n)) |
| 277 | #define OPORTMXDXDFREQMODE(n) (0x42024 + 0x400 * (n)) |
| 278 | #define OPORTMXDSDSEL(n) (0x42028 + 0x400 * (n)) |
| 279 | #define OPORTMXDSDPORT(n) (0x4202c + 0x400 * (n)) |
| 280 | #define OPORTMXACLKSEL0EX(n) (0x42030 + 0x400 * (n)) |
| 281 | #define OPORTMXPATH(n) (0x42040 + 0x400 * (n)) |
| 282 | #define OPORTMXSYNC(n) (0x42044 + 0x400 * (n)) |
| 283 | #define OPORTMXREPET(n) (0x42050 + 0x400 * (n)) |
| 284 | #define OPORTMXREPET_STRLENGTH_AC3 SBF_(IEC61937_FRM_STR_AC3, 16) |
| 285 | #define OPORTMXREPET_STRLENGTH_MPA SBF_(IEC61937_FRM_STR_MPA, 16) |
| 286 | #define OPORTMXREPET_STRLENGTH_MP3 SBF_(IEC61937_FRM_STR_MP3, 16) |
| 287 | #define OPORTMXREPET_STRLENGTH_DTS1 SBF_(IEC61937_FRM_STR_DTS1, 16) |
| 288 | #define OPORTMXREPET_STRLENGTH_DTS2 SBF_(IEC61937_FRM_STR_DTS2, 16) |
| 289 | #define OPORTMXREPET_STRLENGTH_DTS3 SBF_(IEC61937_FRM_STR_DTS3, 16) |
| 290 | #define OPORTMXREPET_STRLENGTH_AAC SBF_(IEC61937_FRM_STR_AAC, 16) |
| 291 | #define OPORTMXREPET_PMLENGTH_AC3 SBF_(IEC61937_FRM_PAU_AC3, 0) |
| 292 | #define OPORTMXREPET_PMLENGTH_MPA SBF_(IEC61937_FRM_PAU_MPA, 0) |
| 293 | #define OPORTMXREPET_PMLENGTH_MP3 SBF_(IEC61937_FRM_PAU_MP3, 0) |
| 294 | #define OPORTMXREPET_PMLENGTH_DTS1 SBF_(IEC61937_FRM_PAU_DTS1, 0) |
| 295 | #define OPORTMXREPET_PMLENGTH_DTS2 SBF_(IEC61937_FRM_PAU_DTS2, 0) |
| 296 | #define OPORTMXREPET_PMLENGTH_DTS3 SBF_(IEC61937_FRM_PAU_DTS3, 0) |
| 297 | #define OPORTMXREPET_PMLENGTH_AAC SBF_(IEC61937_FRM_PAU_AAC, 0) |
| 298 | #define OPORTMXPAUDAT(n) (0x42054 + 0x400 * (n)) |
| 299 | #define OPORTMXPAUDAT_PAUSEPC_CMN (IEC61937_PC_PAUSE << 16) |
| 300 | #define OPORTMXPAUDAT_PAUSEPD_AC3 (IEC61937_FRM_PAU_AC3 * 4) |
| 301 | #define OPORTMXPAUDAT_PAUSEPD_MPA (IEC61937_FRM_PAU_MPA * 4) |
| 302 | #define OPORTMXPAUDAT_PAUSEPD_MP3 (IEC61937_FRM_PAU_MP3 * 4) |
| 303 | #define OPORTMXPAUDAT_PAUSEPD_DTS1 (IEC61937_FRM_PAU_DTS1 * 4) |
| 304 | #define OPORTMXPAUDAT_PAUSEPD_DTS2 (IEC61937_FRM_PAU_DTS2 * 4) |
| 305 | #define OPORTMXPAUDAT_PAUSEPD_DTS3 (IEC61937_FRM_PAU_DTS3 * 4) |
| 306 | #define OPORTMXPAUDAT_PAUSEPD_AAC (IEC61937_FRM_PAU_AAC * 4) |
| 307 | #define OPORTMXRATE_I(n) (0x420e4 + 0x400 * (n)) |
| 308 | #define OPORTMXRATE_I_EQU_MASK BIT(31) |
| 309 | #define OPORTMXRATE_I_EQU_NOTEQUAL (0x0 << 31) |
| 310 | #define OPORTMXRATE_I_EQU_EQUAL (0x1 << 31) |
| 311 | #define OPORTMXRATE_I_SRCBPMD_MASK BIT(29) |
| 312 | #define OPORTMXRATE_I_SRCBPMD_BYPASS (0x0 << 29) |
| 313 | #define OPORTMXRATE_I_SRCBPMD_SRC (0x1 << 29) |
| 314 | #define OPORTMXRATE_I_LRCKSTP_MASK BIT(24) |
| 315 | #define OPORTMXRATE_I_LRCKSTP_START (0x0 << 24) |
| 316 | #define OPORTMXRATE_I_LRCKSTP_STOP (0x1 << 24) |
| 317 | #define OPORTMXRATE_I_ACLKSRC_MASK GENMASK(15, 12) |
| 318 | #define OPORTMXRATE_I_ACLKSRC_APLL (0x0 << 12) |
| 319 | #define OPORTMXRATE_I_ACLKSRC_USB (0x1 << 12) |
| 320 | #define OPORTMXRATE_I_ACLKSRC_HSC (0x3 << 12) |
| 321 | /* if OPORTMXRATE_I_ACLKSRC_APLL */ |
| 322 | #define OPORTMXRATE_I_ACLKSEL_MASK GENMASK(11, 8) |
| 323 | #define OPORTMXRATE_I_ACLKSEL_APLLA1 (0x0 << 8) |
| 324 | #define OPORTMXRATE_I_ACLKSEL_APLLF1 (0x1 << 8) |
| 325 | #define OPORTMXRATE_I_ACLKSEL_APLLA2 (0x2 << 8) |
| 326 | #define OPORTMXRATE_I_ACLKSEL_APLLF2 (0x3 << 8) |
| 327 | #define OPORTMXRATE_I_ACLKSEL_APLL (0x4 << 8) |
| 328 | #define OPORTMXRATE_I_ACLKSEL_HDMI1 (0x5 << 8) |
| 329 | #define OPORTMXRATE_I_ACLKSEL_HDMI2 (0x6 << 8) |
| 330 | #define OPORTMXRATE_I_ACLKSEL_AI1ADCCK (0xc << 8) |
| 331 | #define OPORTMXRATE_I_ACLKSEL_AI2ADCCK (0xd << 8) |
| 332 | #define OPORTMXRATE_I_ACLKSEL_AI3ADCCK (0xe << 8) |
| 333 | #define OPORTMXRATE_I_MCKSEL_MASK GENMASK(7, 4) |
| 334 | #define OPORTMXRATE_I_MCKSEL_36 (0x0 << 4) |
| 335 | #define OPORTMXRATE_I_MCKSEL_33 (0x1 << 4) |
| 336 | #define OPORTMXRATE_I_MCKSEL_HSC27 (0xb << 4) |
| 337 | #define OPORTMXRATE_I_FSSEL_MASK GENMASK(3, 0) |
| 338 | #define OPORTMXRATE_I_FSSEL_48 (0x0 << 0) |
| 339 | #define OPORTMXRATE_I_FSSEL_96 (0x1 << 0) |
| 340 | #define OPORTMXRATE_I_FSSEL_192 (0x2 << 0) |
| 341 | #define OPORTMXRATE_I_FSSEL_32 (0x3 << 0) |
| 342 | #define OPORTMXRATE_I_FSSEL_44_1 (0x4 << 0) |
| 343 | #define OPORTMXRATE_I_FSSEL_88_2 (0x5 << 0) |
| 344 | #define OPORTMXRATE_I_FSSEL_176_4 (0x6 << 0) |
| 345 | #define OPORTMXRATE_I_FSSEL_16 (0x8 << 0) |
| 346 | #define OPORTMXRATE_I_FSSEL_22_05 (0x9 << 0) |
| 347 | #define OPORTMXRATE_I_FSSEL_24 (0xa << 0) |
| 348 | #define OPORTMXRATE_I_FSSEL_8 (0xb << 0) |
| 349 | #define OPORTMXRATE_I_FSSEL_11_025 (0xc << 0) |
| 350 | #define OPORTMXRATE_I_FSSEL_12 (0xd << 0) |
| 351 | #define OPORTMXEXNOE(n) (0x420f0 + 0x400 * (n)) |
| 352 | #define OPORTMXMASK(n) (0x420f8 + 0x400 * (n)) |
| 353 | #define OPORTMXMASK_IUDXMSK_MASK GENMASK(28, 24) |
| 354 | #define OPORTMXMASK_IUDXMSK_ON (0x00 << 24) |
| 355 | #define OPORTMXMASK_IUDXMSK_OFF (0x1f << 24) |
| 356 | #define OPORTMXMASK_IUXCKMSK_MASK GENMASK(18, 16) |
| 357 | #define OPORTMXMASK_IUXCKMSK_ON (0x0 << 16) |
| 358 | #define OPORTMXMASK_IUXCKMSK_OFF (0x7 << 16) |
| 359 | #define OPORTMXMASK_DXMSK_MASK GENMASK(12, 8) |
| 360 | #define OPORTMXMASK_DXMSK_ON (0x00 << 8) |
| 361 | #define OPORTMXMASK_DXMSK_OFF (0x1f << 8) |
| 362 | #define OPORTMXMASK_XCKMSK_MASK GENMASK(2, 0) |
| 363 | #define OPORTMXMASK_XCKMSK_ON (0x0 << 0) |
| 364 | #define OPORTMXMASK_XCKMSK_OFF (0x7 << 0) |
| 365 | #define OPORTMXDEBUG(n) (0x420fc + 0x400 * (n)) |
| Katsuhiro Suzuki | 5a748de | 2018-05-08 12:16:39 +0900 | [diff] [blame] | 366 | #define OPORTMXTYVOLPARA1(n, m) (0x42100 + 0x400 * (n) + 0x20 * (m)) |
| 367 | #define OPORTMXTYVOLPARA1_SLOPEU_MASK GENMASK(31, 16) |
| 368 | #define OPORTMXTYVOLPARA2(n, m) (0x42104 + 0x400 * (n) + 0x20 * (m)) |
| 369 | #define OPORTMXTYVOLPARA2_FADE_MASK GENMASK(17, 16) |
| 370 | #define OPORTMXTYVOLPARA2_FADE_NOOP (0x0 << 16) |
| 371 | #define OPORTMXTYVOLPARA2_FADE_FADEOUT (0x1 << 16) |
| 372 | #define OPORTMXTYVOLPARA2_FADE_FADEIN (0x2 << 16) |
| 373 | #define OPORTMXTYVOLPARA2_TARGET_MASK GENMASK(15, 0) |
| 374 | #define OPORTMXTYVOLGAINSTATUS(n, m) (0x42108 + 0x400 * (n) + 0x20 * (m)) |
| 375 | #define OPORTMXTYVOLGAINSTATUS_CUR_MASK GENMASK(15, 0) |
| 376 | #define OPORTMXTYSLOTCTR(n, m) (0x42114 + 0x400 * (n) + 0x20 * (m)) |
| Katsuhiro Suzuki | 8fc9983 | 2018-07-27 11:37:28 +0900 | [diff] [blame] | 377 | #define OPORTMXTYSLOTCTR_MODE BIT(15) |
| Katsuhiro Suzuki | 5a748de | 2018-05-08 12:16:39 +0900 | [diff] [blame] | 378 | #define OPORTMXTYSLOTCTR_SLOTSEL_MASK GENMASK(11, 8) |
| 379 | #define OPORTMXTYSLOTCTR_SLOTSEL_SLOT0 (0x8 << 8) |
| 380 | #define OPORTMXTYSLOTCTR_SLOTSEL_SLOT1 (0x9 << 8) |
| 381 | #define OPORTMXTYSLOTCTR_SLOTSEL_SLOT2 (0xa << 8) |
| 382 | #define OPORTMXTYSLOTCTR_SLOTSEL_SLOT3 (0xb << 8) |
| 383 | #define OPORTMXTYSLOTCTR_SLOTSEL_SLOT4 (0xc << 8) |
| 384 | #define OPORTMXT0SLOTCTR_MUTEOFF_MASK BIT(1) |
| 385 | #define OPORTMXT0SLOTCTR_MUTEOFF_MUTE (0x0 << 1) |
| 386 | #define OPORTMXT0SLOTCTR_MUTEOFF_UNMUTE (0x1 << 1) |
| 387 | #define OPORTMXTYRSTCTR(n, m) (0x4211c + 0x400 * (n) + 0x20 * (m)) |
| 388 | #define OPORTMXT0RSTCTR_RST_MASK BIT(1) |
| 389 | #define OPORTMXT0RSTCTR_RST_OFF (0x0 << 1) |
| 390 | #define OPORTMXT0RSTCTR_RST_ON (0x1 << 1) |
| Katsuhiro Suzuki | f37fe2f | 2018-01-19 18:25:29 +0900 | [diff] [blame] | 391 | |
| 392 | #define SBF_(frame, shift) (((frame) * 2 - 1) << shift) |
| 393 | |
| 394 | /* AOUT(PBoutMX) */ |
| 395 | #define PBOUTMXCTR0(n) (0x40200 + 0x40 * (n)) |
| 396 | #define PBOUTMXCTR0_ENDIAN_MASK GENMASK(5, 4) |
| 397 | #define PBOUTMXCTR0_ENDIAN_3210 (0x0 << 4) |
| 398 | #define PBOUTMXCTR0_ENDIAN_0123 (0x1 << 4) |
| 399 | #define PBOUTMXCTR0_ENDIAN_1032 (0x2 << 4) |
| 400 | #define PBOUTMXCTR0_ENDIAN_2301 (0x3 << 4) |
| 401 | #define PBOUTMXCTR0_MEMFMT_MASK GENMASK(3, 0) |
| 402 | #define PBOUTMXCTR0_MEMFMT_10CH (0x0 << 0) |
| 403 | #define PBOUTMXCTR0_MEMFMT_8CH (0x1 << 0) |
| 404 | #define PBOUTMXCTR0_MEMFMT_6CH (0x2 << 0) |
| 405 | #define PBOUTMXCTR0_MEMFMT_4CH (0x3 << 0) |
| 406 | #define PBOUTMXCTR0_MEMFMT_2CH (0x4 << 0) |
| 407 | #define PBOUTMXCTR0_MEMFMT_STREAM (0x5 << 0) |
| 408 | #define PBOUTMXCTR0_MEMFMT_1CH (0x6 << 0) |
| 409 | #define PBOUTMXCTR1(n) (0x40204 + 0x40 * (n)) |
| 410 | #define PBOUTMXINTCTR(n) (0x40208 + 0x40 * (n)) |
| 411 | |
| 412 | /* A2D(subsystem) */ |
| 413 | #define CDA2D_STRT0 0x10000 |
| 414 | #define CDA2D_STRT0_STOP_MASK BIT(31) |
| 415 | #define CDA2D_STRT0_STOP_START (0x0 << 31) |
| 416 | #define CDA2D_STRT0_STOP_STOP (0x1 << 31) |
| 417 | #define CDA2D_STAT0 0x10020 |
| 418 | #define CDA2D_TEST 0x100a0 |
| 419 | #define CDA2D_TEST_DDR_MODE_MASK GENMASK(3, 2) |
| 420 | #define CDA2D_TEST_DDR_MODE_EXTON0 (0x0 << 2) |
| 421 | #define CDA2D_TEST_DDR_MODE_EXTOFF1 (0x3 << 2) |
| 422 | #define CDA2D_STRTADRSLOAD 0x100b0 |
| 423 | |
| 424 | #define CDA2D_CHMXCTRL1(n) (0x12000 + 0x80 * (n)) |
| 425 | #define CDA2D_CHMXCTRL1_INDSIZE_MASK BIT(0) |
| 426 | #define CDA2D_CHMXCTRL1_INDSIZE_FINITE (0x0 << 0) |
| 427 | #define CDA2D_CHMXCTRL1_INDSIZE_INFINITE (0x1 << 0) |
| 428 | #define CDA2D_CHMXCTRL2(n) (0x12004 + 0x80 * (n)) |
| 429 | #define CDA2D_CHMXSRCAMODE(n) (0x12020 + 0x80 * (n)) |
| 430 | #define CDA2D_CHMXDSTAMODE(n) (0x12024 + 0x80 * (n)) |
| 431 | #define CDA2D_CHMXAMODE_ENDIAN_MASK GENMASK(17, 16) |
| 432 | #define CDA2D_CHMXAMODE_ENDIAN_3210 (0x0 << 16) |
| 433 | #define CDA2D_CHMXAMODE_ENDIAN_0123 (0x1 << 16) |
| 434 | #define CDA2D_CHMXAMODE_ENDIAN_1032 (0x2 << 16) |
| 435 | #define CDA2D_CHMXAMODE_ENDIAN_2301 (0x3 << 16) |
| 436 | #define CDA2D_CHMXAMODE_RSSEL_SHIFT (8) |
| 437 | #define CDA2D_CHMXAMODE_AUPDT_MASK GENMASK(5, 4) |
| 438 | #define CDA2D_CHMXAMODE_AUPDT_INC (0x0 << 4) |
| 439 | #define CDA2D_CHMXAMODE_AUPDT_FIX (0x2 << 4) |
| 440 | #define CDA2D_CHMXAMODE_TYPE_MASK GENMASK(3, 2) |
| 441 | #define CDA2D_CHMXAMODE_TYPE_NORMAL (0x0 << 2) |
| 442 | #define CDA2D_CHMXAMODE_TYPE_RING (0x1 << 2) |
| 443 | #define CDA2D_CHMXSRCSTRTADRS(n) (0x12030 + 0x80 * (n)) |
| 444 | #define CDA2D_CHMXSRCSTRTADRSU(n) (0x12034 + 0x80 * (n)) |
| 445 | #define CDA2D_CHMXDSTSTRTADRS(n) (0x12038 + 0x80 * (n)) |
| 446 | #define CDA2D_CHMXDSTSTRTADRSU(n) (0x1203c + 0x80 * (n)) |
| 447 | |
| 448 | /* A2D(ring buffer) */ |
| 449 | #define CDA2D_RBFLUSH0 0x10040 |
| 450 | #define CDA2D_RBADRSLOAD 0x100b4 |
| 451 | #define CDA2D_RDPTRLOAD 0x100b8 |
| 452 | #define CDA2D_RDPTRLOAD_LSFLAG_LOAD (0x0 << 31) |
| 453 | #define CDA2D_RDPTRLOAD_LSFLAG_STORE (0x1 << 31) |
| 454 | #define CDA2D_WRPTRLOAD 0x100bc |
| 455 | #define CDA2D_WRPTRLOAD_LSFLAG_LOAD (0x0 << 31) |
| 456 | #define CDA2D_WRPTRLOAD_LSFLAG_STORE (0x1 << 31) |
| 457 | |
| 458 | #define CDA2D_RBMXBGNADRS(n) (0x14000 + 0x80 * (n)) |
| 459 | #define CDA2D_RBMXBGNADRSU(n) (0x14004 + 0x80 * (n)) |
| 460 | #define CDA2D_RBMXENDADRS(n) (0x14008 + 0x80 * (n)) |
| 461 | #define CDA2D_RBMXENDADRSU(n) (0x1400c + 0x80 * (n)) |
| 462 | #define CDA2D_RBMXBTH(n) (0x14038 + 0x80 * (n)) |
| 463 | #define CDA2D_RBMXRTH(n) (0x1403c + 0x80 * (n)) |
| 464 | #define CDA2D_RBMXRDPTR(n) (0x14020 + 0x80 * (n)) |
| 465 | #define CDA2D_RBMXRDPTRU(n) (0x14024 + 0x80 * (n)) |
| 466 | #define CDA2D_RBMXWRPTR(n) (0x14028 + 0x80 * (n)) |
| 467 | #define CDA2D_RBMXWRPTRU(n) (0x1402c + 0x80 * (n)) |
| 468 | #define CDA2D_RBMXPTRU_PTRU_MASK GENMASK(1, 0) |
| 469 | #define CDA2D_RBMXCNFG(n) (0x14030 + 0x80 * (n)) |
| 470 | #define CDA2D_RBMXIR(n) (0x14014 + 0x80 * (n)) |
| 471 | #define CDA2D_RBMXIE(n) (0x14018 + 0x80 * (n)) |
| 472 | #define CDA2D_RBMXID(n) (0x1401c + 0x80 * (n)) |
| 473 | #define CDA2D_RBMXIX_SPACE BIT(3) |
| 474 | #define CDA2D_RBMXIX_REMAIN BIT(4) |
| 475 | |
| 476 | #endif /* SND_UNIPHIER_AIO_REG_H__ */ |