Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 1 | # |
| 2 | # DMA engine configuration |
| 3 | # |
| 4 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 5 | menuconfig DMADEVICES |
Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 6 | bool "DMA Engine support" |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 7 | depends on HAS_DMA |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 8 | help |
Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 9 | DMA engines can do asynchronous data transfers without |
| 10 | involving the host CPU. Currently, this framework can be |
| 11 | used to offload memory copies in the network stack and |
Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 12 | RAID operations in the MD driver. This menu only presents |
| 13 | DMA Device drivers supported by the configured arch, it may |
| 14 | be empty in some cases. |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 15 | |
Linus Walleij | 6c664a8 | 2010-02-09 22:34:54 +0100 | [diff] [blame] | 16 | config DMADEVICES_DEBUG |
| 17 | bool "DMA Engine debugging" |
| 18 | depends on DMADEVICES != n |
| 19 | help |
| 20 | This is an option for use by developers; most people should |
| 21 | say N here. This enables DMA engine core and driver debugging. |
| 22 | |
| 23 | config DMADEVICES_VDEBUG |
| 24 | bool "DMA Engine verbose debugging" |
| 25 | depends on DMADEVICES_DEBUG != n |
| 26 | help |
| 27 | This is an option for use by developers; most people should |
| 28 | say N here. This enables deeper (more verbose) debugging of |
| 29 | the DMA engine core and drivers. |
| 30 | |
| 31 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 32 | if DMADEVICES |
Chris Leech | db21733 | 2006-06-17 21:24:58 -0700 | [diff] [blame] | 33 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 34 | comment "DMA Devices" |
| 35 | |
Siva Yerramreddy | 95b4ecb | 2014-07-11 14:04:21 -0700 | [diff] [blame] | 36 | config INTEL_MIC_X100_DMA |
| 37 | tristate "Intel MIC X100 DMA Driver" |
| 38 | depends on 64BIT && X86 && INTEL_MIC_BUS |
Sudeep Dutt | ce05b68 | 2014-07-14 14:23:52 -0700 | [diff] [blame] | 39 | select DMA_ENGINE |
Siva Yerramreddy | 95b4ecb | 2014-07-11 14:04:21 -0700 | [diff] [blame] | 40 | help |
| 41 | This enables DMA support for the Intel Many Integrated Core |
| 42 | (MIC) family of PCIe form factor coprocessor X100 devices that |
| 43 | run a 64 bit Linux OS. This driver will be used by both MIC |
| 44 | host and card drivers. |
| 45 | |
| 46 | If you are building host kernel with a MIC device or a card |
| 47 | kernel for a MIC device, then say M (recommended) or Y, else |
| 48 | say N. If unsure say N. |
| 49 | |
| 50 | More information about the Intel MIC family as well as the Linux |
| 51 | OS and tools for MIC to use with this driver are available from |
| 52 | <http://software.intel.com/en-us/mic-developer>. |
| 53 | |
Vinod Koul | b3c567e | 2010-07-21 13:28:10 +0530 | [diff] [blame] | 54 | config INTEL_MID_DMAC |
| 55 | tristate "Intel MID DMA support for Peripheral DMA controllers" |
| 56 | depends on PCI && X86 |
| 57 | select DMA_ENGINE |
| 58 | default n |
| 59 | help |
| 60 | Enable support for the Intel(R) MID DMA engine present |
| 61 | in Intel MID chipsets. |
| 62 | |
| 63 | Say Y here if you have such a chipset. |
| 64 | |
| 65 | If unsure, say N. |
| 66 | |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 67 | config ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Dan Williams | 138f4c3 | 2009-09-08 17:42:51 -0700 | [diff] [blame] | 68 | bool |
| 69 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 70 | config AMBA_PL08X |
| 71 | bool "ARM PrimeCell PL080 or PL081 support" |
Kees Cook | c6a0aec | 2012-10-23 13:01:54 -0700 | [diff] [blame] | 72 | depends on ARM_AMBA |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 73 | select DMA_ENGINE |
Russell King | 083be28 | 2012-05-26 14:09:53 +0100 | [diff] [blame] | 74 | select DMA_VIRTUAL_CHANNELS |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 75 | help |
| 76 | Platform has a PL08x DMAC device |
| 77 | which can provide DMA engine support |
| 78 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 79 | config INTEL_IOATDMA |
| 80 | tristate "Intel I/OAT DMA support" |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 81 | depends on PCI && X86 |
| 82 | select DMA_ENGINE |
Dan Williams | 3cc377b | 2013-12-09 10:33:16 -0800 | [diff] [blame] | 83 | select DMA_ENGINE_RAID |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 84 | select DCA |
| 85 | help |
| 86 | Enable support for the Intel(R) I/OAT DMA engine present |
| 87 | in recent Intel Xeon chipsets. |
| 88 | |
| 89 | Say Y here if you have such a chipset. |
| 90 | |
| 91 | If unsure, say N. |
Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 92 | |
| 93 | config INTEL_IOP_ADMA |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 94 | tristate "Intel IOP ADMA support" |
| 95 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 96 | select DMA_ENGINE |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 97 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 98 | help |
| 99 | Enable support for the Intel(R) IOP Series RAID engines. |
Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 100 | |
Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 101 | source "drivers/dma/dw/Kconfig" |
Hein Tibosch | d5ea7b5 | 2012-10-25 13:38:05 -0700 | [diff] [blame] | 102 | |
Nicolas Ferre | dc78baa | 2009-07-03 19:24:33 +0200 | [diff] [blame] | 103 | config AT_HDMAC |
| 104 | tristate "Atmel AHB DMA support" |
Nicolas Ferre | f898fed | 2012-03-15 11:31:58 +0100 | [diff] [blame] | 105 | depends on ARCH_AT91 |
Nicolas Ferre | dc78baa | 2009-07-03 19:24:33 +0200 | [diff] [blame] | 106 | select DMA_ENGINE |
| 107 | help |
Nicolas Ferre | f898fed | 2012-03-15 11:31:58 +0100 | [diff] [blame] | 108 | Support the Atmel AHB DMA controller. |
Nicolas Ferre | dc78baa | 2009-07-03 19:24:33 +0200 | [diff] [blame] | 109 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 110 | config FSL_DMA |
Hongbo Zhang | 8de7a7d | 2013-09-26 17:33:43 +0800 | [diff] [blame] | 111 | tristate "Freescale Elo series DMA support" |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 112 | depends on FSL_SOC |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 113 | select DMA_ENGINE |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 114 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 115 | ---help--- |
Hongbo Zhang | 8de7a7d | 2013-09-26 17:33:43 +0800 | [diff] [blame] | 116 | Enable support for the Freescale Elo series DMA controllers. |
| 117 | The Elo is the DMA controller on some mpc82xx and mpc83xx parts, the |
| 118 | EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on |
| 119 | some Txxx and Bxxx parts. |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 120 | |
Piotr Ziecik | 0fb6f73 | 2010-02-05 03:42:52 +0000 | [diff] [blame] | 121 | config MPC512X_DMA |
| 122 | tristate "Freescale MPC512x built-in DMA engine support" |
Ilya Yanok | ba2eea2 | 2010-10-27 01:52:57 +0200 | [diff] [blame] | 123 | depends on PPC_MPC512x || PPC_MPC831x |
Piotr Ziecik | 0fb6f73 | 2010-02-05 03:42:52 +0000 | [diff] [blame] | 124 | select DMA_ENGINE |
| 125 | ---help--- |
| 126 | Enable support for the Freescale MPC512x built-in DMA engine. |
| 127 | |
Philippe De Muyter | 9a32299 | 2012-10-12 17:52:45 +0200 | [diff] [blame] | 128 | source "drivers/dma/bestcomm/Kconfig" |
| 129 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 130 | config MV_XOR |
| 131 | bool "Marvell XOR engine support" |
| 132 | depends on PLAT_ORION |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 133 | select DMA_ENGINE |
Dan Williams | 3cc377b | 2013-12-09 10:33:16 -0800 | [diff] [blame] | 134 | select DMA_ENGINE_RAID |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 135 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 136 | ---help--- |
| 137 | Enable support for the Marvell XOR engine. |
| 138 | |
Guennadi Liakhovetski | 5296b56 | 2009-01-19 15:36:21 -0700 | [diff] [blame] | 139 | config MX3_IPU |
| 140 | bool "MX3x Image Processing Unit support" |
Sascha Hauer | 8e2d41f | 2011-08-24 08:41:09 +0200 | [diff] [blame] | 141 | depends on ARCH_MXC |
Guennadi Liakhovetski | 5296b56 | 2009-01-19 15:36:21 -0700 | [diff] [blame] | 142 | select DMA_ENGINE |
| 143 | default y |
| 144 | help |
| 145 | If you plan to use the Image Processing unit in the i.MX3x, say |
| 146 | Y here. If unsure, select Y. |
| 147 | |
| 148 | config MX3_IPU_IRQS |
| 149 | int "Number of dynamically mapped interrupts for IPU" |
| 150 | depends on MX3_IPU |
| 151 | range 2 137 |
| 152 | default 4 |
| 153 | help |
| 154 | Out of 137 interrupt sources on i.MX31 IPU only very few are used. |
| 155 | To avoid bloating the irq_desc[] array we allocate a sufficient |
| 156 | number of IRQ slots and map them dynamically to specific sources. |
| 157 | |
Atsushi Nemoto | ea76f0b | 2009-04-23 00:40:30 +0900 | [diff] [blame] | 158 | config TXX9_DMAC |
| 159 | tristate "Toshiba TXx9 SoC DMA support" |
| 160 | depends on MACH_TX49XX || MACH_TX39XX |
| 161 | select DMA_ENGINE |
| 162 | help |
| 163 | Support the TXx9 SoC internal DMA controller. This can be |
| 164 | integrated in chips such as the Toshiba TX4927/38/39. |
| 165 | |
Laxman Dewangan | ec8a158 | 2012-06-06 10:55:27 +0530 | [diff] [blame] | 166 | config TEGRA20_APB_DMA |
| 167 | bool "NVIDIA Tegra20 APB DMA support" |
| 168 | depends on ARCH_TEGRA |
| 169 | select DMA_ENGINE |
| 170 | help |
| 171 | Support for the NVIDIA Tegra20 APB DMA controller driver. The |
| 172 | DMA controller is having multiple DMA channel which can be |
| 173 | configured for different peripherals like audio, UART, SPI, |
| 174 | I2C etc which is in APB bus. |
| 175 | This DMA controller transfers data from memory to peripheral fifo |
| 176 | or vice versa. It does not support memory to memory data transfer. |
| 177 | |
Heiko Stuebner | ddeccb8 | 2013-10-08 06:42:10 +0900 | [diff] [blame] | 178 | config S3C24XX_DMAC |
| 179 | tristate "Samsung S3C24XX DMA support" |
| 180 | depends on ARCH_S3C24XX && !S3C24XX_DMA |
| 181 | select DMA_ENGINE |
| 182 | select DMA_VIRTUAL_CHANNELS |
| 183 | help |
| 184 | Support for the Samsung S3C24XX DMA controller driver. The |
| 185 | DMA controller is having multiple DMA channels which can be |
| 186 | configured for different peripherals like audio, UART, SPI. |
| 187 | The DMA controller can transfer data from memory to peripheral, |
| 188 | periphal to memory, periphal to periphal and memory to memory. |
| 189 | |
Shimoda, Yoshihiro | 189b4ee | 2013-04-23 20:00:06 +0900 | [diff] [blame] | 190 | source "drivers/dma/sh/Kconfig" |
Nobuhiro Iwamatsu | d8902ad | 2009-09-07 03:26:23 +0000 | [diff] [blame] | 191 | |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 192 | config COH901318 |
| 193 | bool "ST-Ericsson COH901318 DMA support" |
| 194 | select DMA_ENGINE |
| 195 | depends on ARCH_U300 |
| 196 | help |
| 197 | Enable support for ST-Ericsson COH 901 318 DMA. |
| 198 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 199 | config STE_DMA40 |
| 200 | bool "ST-Ericsson DMA40 support" |
| 201 | depends on ARCH_U8500 |
| 202 | select DMA_ENGINE |
| 203 | help |
| 204 | Support for ST-Ericsson DMA40 controller |
| 205 | |
Anatolij Gustschin | 12458ea | 2009-12-11 21:24:44 -0700 | [diff] [blame] | 206 | config AMCC_PPC440SPE_ADMA |
| 207 | tristate "AMCC PPC440SPe ADMA support" |
| 208 | depends on 440SPe || 440SP |
| 209 | select DMA_ENGINE |
Dan Williams | 3cc377b | 2013-12-09 10:33:16 -0800 | [diff] [blame] | 210 | select DMA_ENGINE_RAID |
Anatolij Gustschin | 12458ea | 2009-12-11 21:24:44 -0700 | [diff] [blame] | 211 | select ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 212 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Anatolij Gustschin | 12458ea | 2009-12-11 21:24:44 -0700 | [diff] [blame] | 213 | help |
| 214 | Enable support for the AMCC PPC440SPe RAID engines. |
| 215 | |
Richard Röjfors | de5d445 | 2010-03-25 19:44:21 +0100 | [diff] [blame] | 216 | config TIMB_DMA |
| 217 | tristate "Timberdale FPGA DMA support" |
Jean Delvare | 2dda47d | 2014-04-03 11:32:06 +0200 | [diff] [blame] | 218 | depends on MFD_TIMBERDALE |
Richard Röjfors | de5d445 | 2010-03-25 19:44:21 +0100 | [diff] [blame] | 219 | select DMA_ENGINE |
| 220 | help |
| 221 | Enable support for the Timberdale FPGA DMA engine. |
| 222 | |
Rongjun Ying | ca21a14 | 2011-10-27 19:22:39 -0700 | [diff] [blame] | 223 | config SIRF_DMA |
Barry Song | f7d935d | 2012-11-01 22:54:43 +0800 | [diff] [blame] | 224 | tristate "CSR SiRFprimaII/SiRFmarco DMA support" |
| 225 | depends on ARCH_SIRF |
Rongjun Ying | ca21a14 | 2011-10-27 19:22:39 -0700 | [diff] [blame] | 226 | select DMA_ENGINE |
| 227 | help |
| 228 | Enable support for the CSR SiRFprimaII DMA engine. |
| 229 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 230 | config TI_EDMA |
Guenter Roeck | 7644804 | 2013-08-22 14:03:24 -0700 | [diff] [blame] | 231 | bool "TI EDMA support" |
Santosh Shilimkar | e7ed8b4 | 2013-09-30 11:04:42 -0400 | [diff] [blame] | 232 | depends on ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 233 | select DMA_ENGINE |
| 234 | select DMA_VIRTUAL_CHANNELS |
Josh Boyer | c2b9e97 | 2013-09-04 09:32:03 -0400 | [diff] [blame] | 235 | select TI_PRIV_EDMA |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 236 | default n |
| 237 | help |
| 238 | Enable support for the TI EDMA controller. This DMA |
| 239 | engine is found on TI DaVinci and AM33xx parts. |
| 240 | |
Anatolij Gustschin | 12458ea | 2009-12-11 21:24:44 -0700 | [diff] [blame] | 241 | config ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
| 242 | bool |
| 243 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 244 | config PL330_DMA |
| 245 | tristate "DMA API Driver for PL330" |
| 246 | select DMA_ENGINE |
Boojin Kim | 1b9bb71 | 2011-09-02 09:44:30 +0900 | [diff] [blame] | 247 | depends on ARM_AMBA |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 248 | help |
| 249 | Select if your platform has one or more PL330 DMACs. |
| 250 | You need to provide platform specific settings via |
| 251 | platform_data for a dma-pl330 device. |
| 252 | |
Yong Wang | 0c42bd0 | 2010-07-30 16:23:03 +0800 | [diff] [blame] | 253 | config PCH_DMA |
Tomoya MORINAGA | ca7fe2d | 2011-11-17 16:14:23 +0900 | [diff] [blame] | 254 | tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA" |
Jean Delvare | 4828b49 | 2014-05-16 16:17:37 +0200 | [diff] [blame] | 255 | depends on PCI && (X86_32 || COMPILE_TEST) |
Yong Wang | 0c42bd0 | 2010-07-30 16:23:03 +0800 | [diff] [blame] | 256 | select DMA_ENGINE |
| 257 | help |
Tomoya MORINAGA | 2cdf245 | 2011-01-05 17:43:52 +0900 | [diff] [blame] | 258 | Enable support for Intel EG20T PCH DMA engine. |
| 259 | |
Tomoya MORINAGA | e79e72b | 2011-11-17 16:14:22 +0900 | [diff] [blame] | 260 | This driver also can be used for LAPIS Semiconductor IOH(Input/ |
Tomoya MORINAGA | ca7fe2d | 2011-11-17 16:14:23 +0900 | [diff] [blame] | 261 | Output Hub), ML7213, ML7223 and ML7831. |
| 262 | ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is |
| 263 | for MP(Media Phone) use and ML7831 IOH is for general purpose use. |
| 264 | ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series. |
| 265 | ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH. |
Yong Wang | 0c42bd0 | 2010-07-30 16:23:03 +0800 | [diff] [blame] | 266 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 267 | config IMX_SDMA |
| 268 | tristate "i.MX SDMA support" |
Sascha Hauer | 8e2d41f | 2011-08-24 08:41:09 +0200 | [diff] [blame] | 269 | depends on ARCH_MXC |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 270 | select DMA_ENGINE |
| 271 | help |
| 272 | Support the i.MX SDMA engine. This engine is integrated into |
Sascha Hauer | 8e2d41f | 2011-08-24 08:41:09 +0200 | [diff] [blame] | 273 | Freescale i.MX25/31/35/51/53 chips. |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 274 | |
Sascha Hauer | 1f1846c | 2010-10-06 10:25:55 +0200 | [diff] [blame] | 275 | config IMX_DMA |
| 276 | tristate "i.MX DMA support" |
Vinod Koul | 5b2e02e | 2012-03-27 13:53:00 +0530 | [diff] [blame] | 277 | depends on ARCH_MXC |
Sascha Hauer | 1f1846c | 2010-10-06 10:25:55 +0200 | [diff] [blame] | 278 | select DMA_ENGINE |
| 279 | help |
| 280 | Support the i.MX DMA engine. This engine is integrated into |
| 281 | Freescale i.MX1/21/27 chips. |
| 282 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 283 | config MXS_DMA |
| 284 | bool "MXS DMA support" |
Huang Shijie | f5c5584 | 2012-06-06 21:22:59 -0400 | [diff] [blame] | 285 | depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 286 | select STMP_DEVICE |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 287 | select DMA_ENGINE |
| 288 | help |
| 289 | Support the MXS DMA engine. This engine including APBH-DMA |
Fabio Estevam | 654fa24 | 2014-05-26 18:08:25 -0300 | [diff] [blame] | 290 | and APBX-DMA is integrated into Freescale i.MX23/28/MX6Q/MX6DL chips. |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 291 | |
Mika Westerberg | 760ee1c | 2011-05-29 13:10:02 +0300 | [diff] [blame] | 292 | config EP93XX_DMA |
| 293 | bool "Cirrus Logic EP93xx DMA support" |
| 294 | depends on ARCH_EP93XX |
| 295 | select DMA_ENGINE |
| 296 | help |
| 297 | Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller. |
| 298 | |
Russell King | 6365bea | 2012-01-09 21:44:07 +0000 | [diff] [blame] | 299 | config DMA_SA11X0 |
| 300 | tristate "SA-11x0 DMA support" |
| 301 | depends on ARCH_SA1100 |
| 302 | select DMA_ENGINE |
Russell King | 50437bf | 2012-04-13 12:07:23 +0100 | [diff] [blame] | 303 | select DMA_VIRTUAL_CHANNELS |
Russell King | 6365bea | 2012-01-09 21:44:07 +0000 | [diff] [blame] | 304 | help |
| 305 | Support the DMA engine found on Intel StrongARM SA-1100 and |
| 306 | SA-1110 SoCs. This DMA engine can only be used with on-chip |
| 307 | devices. |
| 308 | |
Zhangfei Gao | c6da0ba | 2012-06-15 11:04:08 +0800 | [diff] [blame] | 309 | config MMP_TDMA |
| 310 | bool "MMP Two-Channel DMA support" |
Vinod Koul | 49d57b5 | 2012-06-22 10:29:53 +0530 | [diff] [blame] | 311 | depends on ARCH_MMP |
Zhangfei Gao | c6da0ba | 2012-06-15 11:04:08 +0800 | [diff] [blame] | 312 | select DMA_ENGINE |
Qiao Zhou | b9f10a1 | 2013-12-05 09:36:21 +0800 | [diff] [blame] | 313 | select MMP_SRAM |
Zhangfei Gao | c6da0ba | 2012-06-15 11:04:08 +0800 | [diff] [blame] | 314 | help |
| 315 | Support the MMP Two-Channel DMA engine. |
| 316 | This engine used for MMP Audio DMA and pxa910 SQU. |
Qiao Zhou | b9f10a1 | 2013-12-05 09:36:21 +0800 | [diff] [blame] | 317 | It needs sram driver under mach-mmp. |
Zhangfei Gao | c6da0ba | 2012-06-15 11:04:08 +0800 | [diff] [blame] | 318 | |
| 319 | Say Y here if you enabled MMP ADMA, otherwise say N. |
| 320 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 321 | config DMA_OMAP |
| 322 | tristate "OMAP DMA support" |
| 323 | depends on ARCH_OMAP |
| 324 | select DMA_ENGINE |
| 325 | select DMA_VIRTUAL_CHANNELS |
| 326 | |
Florian Meier | 96286b5 | 2014-01-06 20:18:24 +0100 | [diff] [blame] | 327 | config DMA_BCM2835 |
| 328 | tristate "BCM2835 DMA engine support" |
Paul Bolle | dd1ed37 | 2014-02-09 15:39:25 +0100 | [diff] [blame] | 329 | depends on ARCH_BCM2835 |
Florian Meier | 96286b5 | 2014-01-06 20:18:24 +0100 | [diff] [blame] | 330 | select DMA_ENGINE |
| 331 | select DMA_VIRTUAL_CHANNELS |
| 332 | |
Sebastian Andrzej Siewior | 9b3452d | 2013-06-20 12:13:04 +0200 | [diff] [blame] | 333 | config TI_CPPI41 |
| 334 | tristate "AM33xx CPPI41 DMA support" |
| 335 | depends on ARCH_OMAP |
| 336 | select DMA_ENGINE |
| 337 | help |
| 338 | The Communications Port Programming Interface (CPPI) 4.1 DMA engine |
| 339 | is currently used by the USB driver on AM335x platforms. |
| 340 | |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 341 | config MMP_PDMA |
| 342 | bool "MMP PDMA support" |
| 343 | depends on (ARCH_MMP || ARCH_PXA) |
| 344 | select DMA_ENGINE |
| 345 | help |
Masanari Iida | 8c88126 | 2013-09-29 20:54:15 +0900 | [diff] [blame] | 346 | Support the MMP PDMA engine for PXA and MMP platform. |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 347 | |
Lars-Peter Clausen | 7c169a4 | 2013-05-30 18:25:02 +0200 | [diff] [blame] | 348 | config DMA_JZ4740 |
| 349 | tristate "JZ4740 DMA support" |
| 350 | depends on MACH_JZ4740 |
| 351 | select DMA_ENGINE |
| 352 | select DMA_VIRTUAL_CHANNELS |
| 353 | |
Zhangfei Gao | 8e6152b | 2013-08-27 10:20:10 +0800 | [diff] [blame] | 354 | config K3_DMA |
| 355 | tristate "Hisilicon K3 DMA support" |
| 356 | depends on ARCH_HI3xxx |
| 357 | select DMA_ENGINE |
| 358 | select DMA_VIRTUAL_CHANNELS |
| 359 | help |
| 360 | Support the DMA engine for Hisilicon K3 platform |
| 361 | devices. |
| 362 | |
Jonas Jensen | 5f9e685 | 2014-01-17 09:46:05 +0100 | [diff] [blame] | 363 | config MOXART_DMA |
| 364 | tristate "MOXART DMA support" |
| 365 | depends on ARCH_MOXART |
| 366 | select DMA_ENGINE |
Rob Herring | e803d98 | 2014-02-01 16:35:43 -0600 | [diff] [blame] | 367 | select DMA_OF |
Jonas Jensen | 5f9e685 | 2014-01-17 09:46:05 +0100 | [diff] [blame] | 368 | select DMA_VIRTUAL_CHANNELS |
| 369 | help |
| 370 | Enable support for the MOXA ART SoC DMA controller. |
Jingchang Lu | d6be34f | 2014-02-18 10:17:12 +0800 | [diff] [blame] | 371 | |
| 372 | config FSL_EDMA |
| 373 | tristate "Freescale eDMA engine support" |
| 374 | depends on OF |
| 375 | select DMA_ENGINE |
| 376 | select DMA_VIRTUAL_CHANNELS |
| 377 | help |
| 378 | Support the Freescale eDMA engine with programmable channel |
| 379 | multiplexing capability for DMA request sources(slot). |
| 380 | This module can be found on Freescale Vybrid and LS-1 SoCs. |
Jonas Jensen | 5f9e685 | 2014-01-17 09:46:05 +0100 | [diff] [blame] | 381 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 382 | config XILINX_VDMA |
| 383 | tristate "Xilinx AXI VDMA Engine" |
| 384 | depends on (ARCH_ZYNQ || MICROBLAZE) |
| 385 | select DMA_ENGINE |
| 386 | help |
| 387 | Enable support for Xilinx AXI VDMA Soft IP. |
| 388 | |
| 389 | This engine provides high-bandwidth direct memory access |
| 390 | between memory and AXI4-Stream video type target |
| 391 | peripherals including peripherals which support AXI4- |
| 392 | Stream Video Protocol. It has two stream interfaces/ |
| 393 | channels, Memory Mapped to Stream (MM2S) and Stream to |
| 394 | Memory Mapped (S2MM) for the data transfers. |
| 395 | |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 396 | config DMA_SUN6I |
| 397 | tristate "Allwinner A31 SoCs DMA support" |
| 398 | depends on MACH_SUN6I || COMPILE_TEST |
Maxime Ripard | a0bbe99 | 2014-08-07 19:00:44 +0200 | [diff] [blame] | 399 | depends on RESET_CONTROLLER |
Maxime Ripard | 5558593 | 2014-07-17 21:46:16 +0200 | [diff] [blame] | 400 | select DMA_ENGINE |
| 401 | select DMA_VIRTUAL_CHANNELS |
| 402 | help |
| 403 | Support for the DMA engine for Allwinner A31 SoCs. |
| 404 | |
Guennadi Liakhovetski | b45b262 | 2014-07-19 12:48:51 +0200 | [diff] [blame] | 405 | config NBPFAXI_DMA |
| 406 | tristate "Renesas Type-AXI NBPF DMA support" |
| 407 | select DMA_ENGINE |
Guennadi Liakhovetski | cfc6abc | 2014-08-06 16:35:41 +0200 | [diff] [blame] | 408 | depends on ARM || COMPILE_TEST |
Guennadi Liakhovetski | b45b262 | 2014-07-19 12:48:51 +0200 | [diff] [blame] | 409 | help |
| 410 | Support for "Type-AXI" NBPF DMA IPs from Renesas |
| 411 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 412 | config DMA_ENGINE |
| 413 | bool |
| 414 | |
Russell King | 50437bf | 2012-04-13 12:07:23 +0100 | [diff] [blame] | 415 | config DMA_VIRTUAL_CHANNELS |
| 416 | tristate |
| 417 | |
Andy Shevchenko | 1b2e98b | 2013-04-09 14:05:43 +0300 | [diff] [blame] | 418 | config DMA_ACPI |
| 419 | def_bool y |
| 420 | depends on ACPI |
| 421 | |
Vinod Koul | 5fa422c | 2013-02-12 09:15:02 -0800 | [diff] [blame] | 422 | config DMA_OF |
| 423 | def_bool y |
| 424 | depends on OF |
Alexander Popov | 2795eed | 2014-07-30 15:58:51 +0400 | [diff] [blame] | 425 | select DMA_ENGINE |
Vinod Koul | 5fa422c | 2013-02-12 09:15:02 -0800 | [diff] [blame] | 426 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 427 | comment "DMA Clients" |
| 428 | depends on DMA_ENGINE |
| 429 | |
| 430 | config NET_DMA |
| 431 | bool "Network: TCP receive copy offload" |
| 432 | depends on DMA_ENGINE && NET |
Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 433 | default (INTEL_IOATDMA || FSL_DMA) |
Dan Williams | 7787380 | 2013-12-17 10:09:32 -0800 | [diff] [blame] | 434 | depends on BROKEN |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 435 | help |
| 436 | This enables the use of DMA engines in the network stack to |
| 437 | offload receive copy-to-user operations, freeing CPU cycles. |
Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 438 | |
| 439 | Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise |
| 440 | say N. |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 441 | |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 442 | config ASYNC_TX_DMA |
| 443 | bool "Async_tx: Offload support for the async_tx api" |
Dan Williams | 9a8de63 | 2009-09-08 15:06:10 -0700 | [diff] [blame] | 444 | depends on DMA_ENGINE |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 445 | help |
| 446 | This allows the async_tx api to take advantage of offload engines for |
| 447 | memcpy, memset, xor, and raid6 p+q operations. If your platform has |
| 448 | a dma engine that can perform raid operations and you have enabled |
| 449 | MD_RAID456 say Y. |
| 450 | |
| 451 | If unsure, say N. |
| 452 | |
Haavard Skinnemoen | 4a776f0 | 2008-07-08 11:58:45 -0700 | [diff] [blame] | 453 | config DMATEST |
| 454 | tristate "DMA Test client" |
| 455 | depends on DMA_ENGINE |
| 456 | help |
| 457 | Simple DMA test client. Say N unless you're debugging a |
| 458 | DMA Device driver. |
| 459 | |
Dan Williams | 3cc377b | 2013-12-09 10:33:16 -0800 | [diff] [blame] | 460 | config DMA_ENGINE_RAID |
| 461 | bool |
| 462 | |
Andy Gross | e7c0fe2 | 2014-03-29 18:53:16 +0530 | [diff] [blame] | 463 | config QCOM_BAM_DMA |
| 464 | tristate "QCOM BAM DMA support" |
| 465 | depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM) |
| 466 | select DMA_ENGINE |
| 467 | select DMA_VIRTUAL_CHANNELS |
| 468 | ---help--- |
| 469 | Enable support for the QCOM BAM DMA controller. This controller |
| 470 | provides DMA capabilities for a variety of on-chip devices. |
| 471 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 472 | endif |