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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 107ea34db4560e6db41a9da90128ccc5e60f6b21 / . / drivers / video / via / hw.c
blob: ae664fbd7e80b037ef51f0c59fcd0879a5b4ab41 [file] [log] [blame]
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]24static struct pll_map pll_value[] = {
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]25 {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M,
26 CX700_25_175M, VX855_25_175M},
27 {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M,
28 CX700_29_581M, VX855_29_581M},
29 {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M,
30 CX700_26_880M, VX855_26_880M},
31 {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M,
32 CX700_31_490M, VX855_31_490M},
33 {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M,
34 CX700_31_500M, VX855_31_500M},
35 {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M,
36 CX700_31_728M, VX855_31_728M},
37 {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M,
38 CX700_32_668M, VX855_32_668M},
39 {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M,
40 CX700_36_000M, VX855_36_000M},
41 {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M,
42 CX700_40_000M, VX855_40_000M},
43 {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M,
44 CX700_41_291M, VX855_41_291M},
45 {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M,
46 CX700_43_163M, VX855_43_163M},
47 {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M,
48 CX700_45_250M, VX855_45_250M},
49 {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M,
50 CX700_46_000M, VX855_46_000M},
51 {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M,
52 CX700_46_996M, VX855_46_996M},
53 {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M,
54 CX700_48_000M, VX855_48_000M},
55 {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M,
56 CX700_48_875M, VX855_48_875M},
57 {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M,
58 CX700_49_500M, VX855_49_500M},
59 {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M,
60 CX700_52_406M, VX855_52_406M},
61 {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M,
62 CX700_52_977M, VX855_52_977M},
63 {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M,
64 CX700_56_250M, VX855_56_250M},
65 {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M,
66 CX700_60_466M, VX855_60_466M},
67 {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M,
68 CX700_61_500M, VX855_61_500M},
69 {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M,
70 CX700_65_000M, VX855_65_000M},
71 {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M,
72 CX700_65_178M, VX855_65_178M},
73 {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M,
74 CX700_66_750M, VX855_66_750M},
75 {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M,
76 CX700_68_179M, VX855_68_179M},
77 {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M,
78 CX700_69_924M, VX855_69_924M},
79 {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M,
80 CX700_70_159M, VX855_70_159M},
81 {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M,
82 CX700_72_000M, VX855_72_000M},
83 {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M,
84 CX700_78_750M, VX855_78_750M},
85 {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M,
86 CX700_80_136M, VX855_80_136M},
87 {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M,
88 CX700_83_375M, VX855_83_375M},
89 {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M,
90 CX700_83_950M, VX855_83_950M},
91 {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M,
92 CX700_84_750M, VX855_84_750M},
93 {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M,
94 CX700_85_860M, VX855_85_860M},
95 {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M,
96 CX700_88_750M, VX855_88_750M},
97 {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M,
98 CX700_94_500M, VX855_94_500M},
99 {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M,
100 CX700_97_750M, VX855_97_750M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]101 {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]102 CX700_101_000M, VX855_101_000M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]103 {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]104 CX700_106_500M, VX855_106_500M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]105 {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]106 CX700_108_000M, VX855_108_000M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]107 {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]108 CX700_113_309M, VX855_113_309M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]109 {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]110 CX700_118_840M, VX855_118_840M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]111 {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]112 CX700_119_000M, VX855_119_000M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]113 {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]114 CX700_121_750M, 0},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]115 {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]116 CX700_125_104M, 0},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]117 {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]118 CX700_133_308M, 0},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]119 {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]120 CX700_135_000M, VX855_135_000M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]121 {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]122 CX700_136_700M, VX855_136_700M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]123 {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]124 CX700_138_400M, VX855_138_400M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]125 {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]126 CX700_146_760M, VX855_146_760M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]127 {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]128 CX700_153_920M, VX855_153_920M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]129 {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]130 CX700_156_000M, VX855_156_000M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]131 {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]132 CX700_157_500M, VX855_157_500M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]133 {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]134 CX700_162_000M, VX855_162_000M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]135 {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]136 CX700_187_000M, VX855_187_000M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]137 {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]138 CX700_193_295M, VX855_193_295M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]139 {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]140 CX700_202_500M, VX855_202_500M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]141 {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]142 CX700_204_000M, VX855_204_000M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]143 {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]144 CX700_218_500M, VX855_218_500M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]145 {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]146 CX700_234_000M, VX855_234_000M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]147 {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]148 CX700_267_250M, VX855_267_250M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]149 {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]150 CX700_297_500M, VX855_297_500M},
151 {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M,
152 CX700_74_481M, VX855_74_481M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]153 {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]154 CX700_172_798M, VX855_172_798M},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]155 {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]156 CX700_122_614M, VX855_122_614M},
157 {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M,
158 CX700_74_270M, 0},
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]159 {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]160 CX700_148_500M, VX855_148_500M}
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]161};
162
163static struct fifo_depth_select display_fifo_depth_reg = {
164 /* IGA1 FIFO Depth_Select */
165 {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
166 /* IGA2 FIFO Depth_Select */
167 {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
168 {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
169};
170
171static struct fifo_threshold_select fifo_threshold_select_reg = {
172 /* IGA1 FIFO Threshold Select */
173 {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
174 /* IGA2 FIFO Threshold Select */
175 {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
176};
177
178static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
179 /* IGA1 FIFO High Threshold Select */
180 {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
181 /* IGA2 FIFO High Threshold Select */
182 {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
183};
184
185static struct display_queue_expire_num display_queue_expire_num_reg = {
186 /* IGA1 Display Queue Expire Num */
187 {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
188 /* IGA2 Display Queue Expire Num */
189 {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
190};
191
192/* Definition Fetch Count Registers*/
193static struct fetch_count fetch_count_reg = {
194 /* IGA1 Fetch Count Register */
195 {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
196 /* IGA2 Fetch Count Register */
197 {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
198};
199
200static struct iga1_crtc_timing iga1_crtc_reg = {
201 /* IGA1 Horizontal Total */
202 {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
203 /* IGA1 Horizontal Addressable Video */
204 {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
205 /* IGA1 Horizontal Blank Start */
206 {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
207 /* IGA1 Horizontal Blank End */
208 {IGA1_HOR_BLANK_END_REG_NUM,
209 {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
210 /* IGA1 Horizontal Sync Start */
211 {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
212 /* IGA1 Horizontal Sync End */
213 {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
214 /* IGA1 Vertical Total */
215 {IGA1_VER_TOTAL_REG_NUM,
216 {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
217 /* IGA1 Vertical Addressable Video */
218 {IGA1_VER_ADDR_REG_NUM,
219 {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
220 /* IGA1 Vertical Blank Start */
221 {IGA1_VER_BLANK_START_REG_NUM,
222 {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
223 /* IGA1 Vertical Blank End */
224 {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
225 /* IGA1 Vertical Sync Start */
226 {IGA1_VER_SYNC_START_REG_NUM,
227 {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
228 /* IGA1 Vertical Sync End */
229 {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
230};
231
232static struct iga2_crtc_timing iga2_crtc_reg = {
233 /* IGA2 Horizontal Total */
234 {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
235 /* IGA2 Horizontal Addressable Video */
236 {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
237 /* IGA2 Horizontal Blank Start */
238 {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
239 /* IGA2 Horizontal Blank End */
240 {IGA2_HOR_BLANK_END_REG_NUM,
241 {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
242 /* IGA2 Horizontal Sync Start */
243 {IGA2_HOR_SYNC_START_REG_NUM,
244 {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
245 /* IGA2 Horizontal Sync End */
246 {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
247 /* IGA2 Vertical Total */
248 {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
249 /* IGA2 Vertical Addressable Video */
250 {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
251 /* IGA2 Vertical Blank Start */
252 {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
253 /* IGA2 Vertical Blank End */
254 {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
255 /* IGA2 Vertical Sync Start */
256 {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
257 /* IGA2 Vertical Sync End */
258 {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
259};
260
261static struct rgbLUT palLUT_table[] = {
262 /* {R,G,B} */
263 /* Index 0x00~0x03 */
264 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
265 0x2A,
266 0x2A},
267 /* Index 0x04~0x07 */
268 {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
269 0x2A,
270 0x2A},
271 /* Index 0x08~0x0B */
272 {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
273 0x3F,
274 0x3F},
275 /* Index 0x0C~0x0F */
276 {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
277 0x3F,
278 0x3F},
279 /* Index 0x10~0x13 */
280 {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
281 0x0B,
282 0x0B},
283 /* Index 0x14~0x17 */
284 {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
285 0x18,
286 0x18},
287 /* Index 0x18~0x1B */
288 {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
289 0x28,
290 0x28},
291 /* Index 0x1C~0x1F */
292 {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
293 0x3F,
294 0x3F},
295 /* Index 0x20~0x23 */
296 {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
297 0x00,
298 0x3F},
299 /* Index 0x24~0x27 */
300 {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
301 0x00,
302 0x10},
303 /* Index 0x28~0x2B */
304 {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
305 0x2F,
306 0x00},
307 /* Index 0x2C~0x2F */
308 {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
309 0x3F,
310 0x00},
311 /* Index 0x30~0x33 */
312 {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
313 0x3F,
314 0x2F},
315 /* Index 0x34~0x37 */
316 {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
317 0x10,
318 0x3F},
319 /* Index 0x38~0x3B */
320 {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
321 0x1F,
322 0x3F},
323 /* Index 0x3C~0x3F */
324 {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
325 0x1F,
326 0x27},
327 /* Index 0x40~0x43 */
328 {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
329 0x3F,
330 0x1F},
331 /* Index 0x44~0x47 */
332 {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
333 0x3F,
334 0x1F},
335 /* Index 0x48~0x4B */
336 {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
337 0x3F,
338 0x37},
339 /* Index 0x4C~0x4F */
340 {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
341 0x27,
342 0x3F},
343 /* Index 0x50~0x53 */
344 {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
345 0x2D,
346 0x3F},
347 /* Index 0x54~0x57 */
348 {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
349 0x2D,
350 0x31},
351 /* Index 0x58~0x5B */
352 {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
353 0x3A,
354 0x2D},
355 /* Index 0x5C~0x5F */
356 {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
357 0x3F,
358 0x2D},
359 /* Index 0x60~0x63 */
360 {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
361 0x3F,
362 0x3A},
363 /* Index 0x64~0x67 */
364 {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
365 0x31,
366 0x3F},
367 /* Index 0x68~0x6B */
368 {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
369 0x00,
370 0x1C},
371 /* Index 0x6C~0x6F */
372 {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
373 0x00,
374 0x07},
375 /* Index 0x70~0x73 */
376 {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
377 0x15,
378 0x00},
379 /* Index 0x74~0x77 */
380 {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
381 0x1C,
382 0x00},
383 /* Index 0x78~0x7B */
384 {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
385 0x1C,
386 0x15},
387 /* Index 0x7C~0x7F */
388 {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
389 0x07,
390 0x1C},
391 /* Index 0x80~0x83 */
392 {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
393 0x0E,
394 0x1C},
395 /* Index 0x84~0x87 */
396 {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
397 0x0E,
398 0x11},
399 /* Index 0x88~0x8B */
400 {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
401 0x18,
402 0x0E},
403 /* Index 0x8C~0x8F */
404 {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
405 0x1C,
406 0x0E},
407 /* Index 0x90~0x93 */
408 {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
409 0x1C,
410 0x18},
411 /* Index 0x94~0x97 */
412 {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
413 0x11,
414 0x1C},
415 /* Index 0x98~0x9B */
416 {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
417 0x14,
418 0x1C},
419 /* Index 0x9C~0x9F */
420 {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
421 0x14,
422 0x16},
423 /* Index 0xA0~0xA3 */
424 {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
425 0x1A,
426 0x14},
427 /* Index 0xA4~0xA7 */
428 {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
429 0x1C,
430 0x14},
431 /* Index 0xA8~0xAB */
432 {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
433 0x1C,
434 0x1A},
435 /* Index 0xAC~0xAF */
436 {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
437 0x16,
438 0x1C},
439 /* Index 0xB0~0xB3 */
440 {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
441 0x00,
442 0x10},
443 /* Index 0xB4~0xB7 */
444 {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
445 0x00,
446 0x04},
447 /* Index 0xB8~0xBB */
448 {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
449 0x0C,
450 0x00},
451 /* Index 0xBC~0xBF */
452 {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
453 0x10,
454 0x00},
455 /* Index 0xC0~0xC3 */
456 {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
457 0x10,
458 0x0C},
459 /* Index 0xC4~0xC7 */
460 {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
461 0x04,
462 0x10},
463 /* Index 0xC8~0xCB */
464 {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
465 0x08,
466 0x10},
467 /* Index 0xCC~0xCF */
468 {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
469 0x08,
470 0x0A},
471 /* Index 0xD0~0xD3 */
472 {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
473 0x0E,
474 0x08},
475 /* Index 0xD4~0xD7 */
476 {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
477 0x10,
478 0x08},
479 /* Index 0xD8~0xDB */
480 {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
481 0x10,
482 0x0E},
483 /* Index 0xDC~0xDF */
484 {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
485 0x0A,
486 0x10},
487 /* Index 0xE0~0xE3 */
488 {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
489 0x0B,
490 0x10},
491 /* Index 0xE4~0xE7 */
492 {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
493 0x0B,
494 0x0C},
495 /* Index 0xE8~0xEB */
496 {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
497 0x0F,
498 0x0B},
499 /* Index 0xEC~0xEF */
500 {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
501 0x10,
502 0x0B},
503 /* Index 0xF0~0xF3 */
504 {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
505 0x10,
506 0x0F},
507 /* Index 0xF4~0xF7 */
508 {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
509 0x0C,
510 0x10},
511 /* Index 0xF8~0xFB */
512 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
513 0x00,
514 0x00},
515 /* Index 0xFC~0xFF */
516 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
517 0x00,
518 0x00}
519};
520
521static void set_crt_output_path(int set_iga);
522static void dvi_patch_skew_dvp0(void);
523static void dvi_patch_skew_dvp1(void);
524static void dvi_patch_skew_dvp_low(void);
525static void set_dvi_output_path(int set_iga, int output_interface);
526static void set_lcd_output_path(int set_iga, int output_interface);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]527static void load_fix_bit_crtc_reg(void);
Harald Welte2d280f72009-09-22 16:47:37 -0700[diff] [blame]528static void init_gfx_chip_info(struct pci_dev *pdev,
529 const struct pci_device_id *pdi);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]530static void init_tmds_chip_info(void);
531static void init_lvds_chip_info(void);
532static void device_screen_off(void);
533static void device_screen_on(void);
534static void set_display_channel(void);
535static void device_off(void);
536static void device_on(void);
537static void enable_second_display_channel(void);
538static void disable_second_display_channel(void);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]539
540void viafb_write_reg(u8 index, u16 io_port, u8 data)
541{
542 outb(index, io_port);
543 outb(data, io_port + 1);
544 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, data); */
545}
546u8 viafb_read_reg(int io_port, u8 index)
547{
548 outb(index, io_port);
549 return inb(io_port + 1);
550}
551
552void viafb_lock_crt(void)
553{
554 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
555}
556
557void viafb_unlock_crt(void)
558{
559 viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
560 viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
561}
562
563void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask)
564{
565 u8 tmp;
566
567 outb(index, io_port);
568 tmp = inb(io_port + 1);
569 outb((data & mask) | (tmp & (~mask)), io_port + 1);
570 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, tmp); */
571}
572
573void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
574{
575 outb(index, LUT_INDEX_WRITE);
576 outb(r, LUT_DATA);
577 outb(g, LUT_DATA);
578 outb(b, LUT_DATA);
579}
580
581/*Set IGA path for each device*/
582void viafb_set_iga_path(void)
583{
584
585 if (viafb_SAMM_ON == 1) {
586 if (viafb_CRT_ON) {
587 if (viafb_primary_dev == CRT_Device)
588 viaparinfo->crt_setting_info->iga_path = IGA1;
589 else
590 viaparinfo->crt_setting_info->iga_path = IGA2;
591 }
592
593 if (viafb_DVI_ON) {
594 if (viafb_primary_dev == DVI_Device)
595 viaparinfo->tmds_setting_info->iga_path = IGA1;
596 else
597 viaparinfo->tmds_setting_info->iga_path = IGA2;
598 }
599
600 if (viafb_LCD_ON) {
601 if (viafb_primary_dev == LCD_Device) {
602 if (viafb_dual_fb &&
603 (viaparinfo->chip_info->gfx_chip_name ==
604 UNICHROME_CLE266)) {
605 viaparinfo->
606 lvds_setting_info->iga_path = IGA2;
607 viaparinfo->
608 crt_setting_info->iga_path = IGA1;
609 viaparinfo->
610 tmds_setting_info->iga_path = IGA1;
611 } else
612 viaparinfo->
613 lvds_setting_info->iga_path = IGA1;
614 } else {
615 viaparinfo->lvds_setting_info->iga_path = IGA2;
616 }
617 }
618 if (viafb_LCD2_ON) {
619 if (LCD2_Device == viafb_primary_dev)
620 viaparinfo->lvds_setting_info2->iga_path = IGA1;
621 else
622 viaparinfo->lvds_setting_info2->iga_path = IGA2;
623 }
624 } else {
625 viafb_SAMM_ON = 0;
626
627 if (viafb_CRT_ON && viafb_LCD_ON) {
628 viaparinfo->crt_setting_info->iga_path = IGA1;
629 viaparinfo->lvds_setting_info->iga_path = IGA2;
630 } else if (viafb_CRT_ON && viafb_DVI_ON) {
631 viaparinfo->crt_setting_info->iga_path = IGA1;
632 viaparinfo->tmds_setting_info->iga_path = IGA2;
633 } else if (viafb_LCD_ON && viafb_DVI_ON) {
634 viaparinfo->tmds_setting_info->iga_path = IGA1;
635 viaparinfo->lvds_setting_info->iga_path = IGA2;
636 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
637 viaparinfo->lvds_setting_info->iga_path = IGA2;
638 viaparinfo->lvds_setting_info2->iga_path = IGA2;
639 } else if (viafb_CRT_ON) {
640 viaparinfo->crt_setting_info->iga_path = IGA1;
641 } else if (viafb_LCD_ON) {
642 viaparinfo->lvds_setting_info->iga_path = IGA2;
643 } else if (viafb_DVI_ON) {
644 viaparinfo->tmds_setting_info->iga_path = IGA1;
645 }
646 }
647}
648
Florian Tobias Schandinat09cf1182009-09-22 16:47:14 -0700[diff] [blame]649void viafb_set_primary_address(u32 addr)
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]650{
Florian Tobias Schandinat09cf1182009-09-22 16:47:14 -0700[diff] [blame]651 DEBUG_MSG(KERN_DEBUG "viafb_set_primary_address(0x%08X)\n", addr);
652 viafb_write_reg(CR0D, VIACR, addr & 0xFF);
653 viafb_write_reg(CR0C, VIACR, (addr >> 8) & 0xFF);
654 viafb_write_reg(CR34, VIACR, (addr >> 16) & 0xFF);
655 viafb_write_reg_mask(CR48, VIACR, (addr >> 24) & 0x1F, 0x1F);
656}
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]657
Florian Tobias Schandinat09cf1182009-09-22 16:47:14 -0700[diff] [blame]658void viafb_set_secondary_address(u32 addr)
659{
660 DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_address(0x%08X)\n", addr);
661 /* secondary display supports only quadword aligned memory */
662 viafb_write_reg_mask(CR62, VIACR, (addr >> 2) & 0xFE, 0xFE);
663 viafb_write_reg(CR63, VIACR, (addr >> 10) & 0xFF);
664 viafb_write_reg(CR64, VIACR, (addr >> 18) & 0xFF);
665 viafb_write_reg_mask(CRA3, VIACR, (addr >> 26) & 0x07, 0x07);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]666}
667
Florian Tobias Schandinat2d6e8852009-09-22 16:47:29 -0700[diff] [blame]668void viafb_set_primary_pitch(u32 pitch)
669{
670 DEBUG_MSG(KERN_DEBUG "viafb_set_primary_pitch(0x%08X)\n", pitch);
671 /* spec does not say that first adapter skips 3 bits but old
672 * code did it and seems to be reasonable in analogy to 2nd adapter
673 */
674 pitch = pitch >> 3;
675 viafb_write_reg(0x13, VIACR, pitch & 0xFF);
676 viafb_write_reg_mask(0x35, VIACR, (pitch >> (8 - 5)) & 0xE0, 0xE0);
677}
678
679void viafb_set_secondary_pitch(u32 pitch)
680{
681 DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_pitch(0x%08X)\n", pitch);
682 pitch = pitch >> 3;
683 viafb_write_reg(0x66, VIACR, pitch & 0xFF);
684 viafb_write_reg_mask(0x67, VIACR, (pitch >> 8) & 0x03, 0x03);
685 viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80);
686}
687
Florian Tobias Schandinatdaacccd2010-03-10 15:21:35 -0800[diff] [blame]688void viafb_set_primary_color_depth(u8 depth)
689{
690 u8 value;
691
692 DEBUG_MSG(KERN_DEBUG "viafb_set_primary_color_depth(%d)\n", depth);
693 switch (depth) {
Florian Tobias Schandinat415559f2010-03-10 15:21:40 -0800[diff] [blame]694 case 8:
Florian Tobias Schandinatdaacccd2010-03-10 15:21:35 -0800[diff] [blame]695 value = 0x00;
696 break;
Florian Tobias Schandinate17cea32010-03-10 15:21:41 -0800[diff] [blame]697 case 15:
698 value = 0x04;
699 break;
Florian Tobias Schandinatdaacccd2010-03-10 15:21:35 -0800[diff] [blame]700 case 16:
701 value = 0x14;
702 break;
703 case 24:
704 value = 0x0C;
705 break;
Florian Tobias Schandinate17cea32010-03-10 15:21:41 -0800[diff] [blame]706 case 30:
707 value = 0x08;
708 break;
Florian Tobias Schandinatdaacccd2010-03-10 15:21:35 -0800[diff] [blame]709 default:
710 printk(KERN_WARNING "viafb_set_primary_color_depth: "
711 "Unsupported depth: %d\n", depth);
712 return;
713 }
714
715 viafb_write_reg_mask(0x15, VIASR, value, 0x1C);
716}
717
718void viafb_set_secondary_color_depth(u8 depth)
719{
720 u8 value;
721
722 DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_color_depth(%d)\n", depth);
723 switch (depth) {
Florian Tobias Schandinat415559f2010-03-10 15:21:40 -0800[diff] [blame]724 case 8:
Florian Tobias Schandinatdaacccd2010-03-10 15:21:35 -0800[diff] [blame]725 value = 0x00;
726 break;
727 case 16:
728 value = 0x40;
729 break;
730 case 24:
731 value = 0xC0;
732 break;
Florian Tobias Schandinate17cea32010-03-10 15:21:41 -0800[diff] [blame]733 case 30:
734 value = 0x80;
735 break;
Florian Tobias Schandinatdaacccd2010-03-10 15:21:35 -0800[diff] [blame]736 default:
737 printk(KERN_WARNING "viafb_set_secondary_color_depth: "
738 "Unsupported depth: %d\n", depth);
739 return;
740 }
741
742 viafb_write_reg_mask(0x67, VIACR, value, 0xC0);
743}
744
Florian Tobias Schandinat415559f2010-03-10 15:21:40 -0800[diff] [blame]745static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
746{
747 outb(0xFF, 0x3C6); /* bit mask of palette */
748 outb(index, 0x3C8);
749 outb(red, 0x3C9);
750 outb(green, 0x3C9);
751 outb(blue, 0x3C9);
752}
753
754void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
755{
756 viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
757 set_color_register(index, red, green, blue);
758}
759
760void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
761{
762 viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
763 set_color_register(index, red, green, blue);
764}
765
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]766void viafb_set_output_path(int device, int set_iga, int output_interface)
767{
768 switch (device) {
769 case DEVICE_CRT:
770 set_crt_output_path(set_iga);
771 break;
772 case DEVICE_DVI:
773 set_dvi_output_path(set_iga, output_interface);
774 break;
775 case DEVICE_LCD:
776 set_lcd_output_path(set_iga, output_interface);
777 break;
778 }
779}
780
781static void set_crt_output_path(int set_iga)
782{
783 viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
784
785 switch (set_iga) {
786 case IGA1:
787 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
788 break;
789 case IGA2:
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]790 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
791 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]792 break;
793 }
794}
795
796static void dvi_patch_skew_dvp0(void)
797{
798 /* Reset data driving first: */
799 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
800 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
801
802 switch (viaparinfo->chip_info->gfx_chip_name) {
803 case UNICHROME_P4M890:
804 {
805 if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
806 (viaparinfo->tmds_setting_info->v_active ==
807 1200))
808 viafb_write_reg_mask(CR96, VIACR, 0x03,
809 BIT0 + BIT1 + BIT2);
810 else
811 viafb_write_reg_mask(CR96, VIACR, 0x07,
812 BIT0 + BIT1 + BIT2);
813 break;
814 }
815
816 case UNICHROME_P4M900:
817 {
818 viafb_write_reg_mask(CR96, VIACR, 0x07,
819 BIT0 + BIT1 + BIT2 + BIT3);
820 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
821 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
822 break;
823 }
824
825 default:
826 {
827 break;
828 }
829 }
830}
831
832static void dvi_patch_skew_dvp1(void)
833{
834 switch (viaparinfo->chip_info->gfx_chip_name) {
835 case UNICHROME_CX700:
836 {
837 break;
838 }
839
840 default:
841 {
842 break;
843 }
844 }
845}
846
847static void dvi_patch_skew_dvp_low(void)
848{
849 switch (viaparinfo->chip_info->gfx_chip_name) {
850 case UNICHROME_K8M890:
851 {
852 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
853 break;
854 }
855
856 case UNICHROME_P4M900:
857 {
858 viafb_write_reg_mask(CR99, VIACR, 0x08,
859 BIT0 + BIT1 + BIT2 + BIT3);
860 break;
861 }
862
863 case UNICHROME_P4M890:
864 {
865 viafb_write_reg_mask(CR99, VIACR, 0x0F,
866 BIT0 + BIT1 + BIT2 + BIT3);
867 break;
868 }
869
870 default:
871 {
872 break;
873 }
874 }
875}
876
877static void set_dvi_output_path(int set_iga, int output_interface)
878{
879 switch (output_interface) {
880 case INTERFACE_DVP0:
881 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
882
883 if (set_iga == IGA1) {
884 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
885 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
886 BIT5 + BIT7);
887 } else {
888 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
889 viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
890 BIT5 + BIT7);
891 }
892
893 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
894
895 dvi_patch_skew_dvp0();
896 break;
897
898 case INTERFACE_DVP1:
899 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
900 if (set_iga == IGA1)
901 viafb_write_reg_mask(CR93, VIACR, 0x21,
902 BIT0 + BIT5 + BIT7);
903 else
904 viafb_write_reg_mask(CR93, VIACR, 0xA1,
905 BIT0 + BIT5 + BIT7);
906 } else {
907 if (set_iga == IGA1)
908 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
909 else
910 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
911 }
912
913 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
914 dvi_patch_skew_dvp1();
915 break;
916 case INTERFACE_DFP_HIGH:
917 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
918 if (set_iga == IGA1) {
919 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
920 viafb_write_reg_mask(CR97, VIACR, 0x03,
921 BIT0 + BIT1 + BIT4);
922 } else {
923 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
924 viafb_write_reg_mask(CR97, VIACR, 0x13,
925 BIT0 + BIT1 + BIT4);
926 }
927 }
928 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
929 break;
930
931 case INTERFACE_DFP_LOW:
932 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
933 break;
934
935 if (set_iga == IGA1) {
936 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
937 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
938 } else {
939 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
940 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
941 }
942
943 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
944 dvi_patch_skew_dvp_low();
945 break;
946
947 case INTERFACE_TMDS:
948 if (set_iga == IGA1)
949 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
950 else
951 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
952 break;
953 }
954
955 if (set_iga == IGA2) {
956 enable_second_display_channel();
957 /* Disable LCD Scaling */
958 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
959 }
960}
961
962static void set_lcd_output_path(int set_iga, int output_interface)
963{
964 DEBUG_MSG(KERN_INFO
965 "set_lcd_output_path, iga:%d,out_interface:%d\n",
966 set_iga, output_interface);
967 switch (set_iga) {
968 case IGA1:
969 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
970 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
971
972 disable_second_display_channel();
973 break;
974
975 case IGA2:
976 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
977 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
978
979 enable_second_display_channel();
980 break;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]981 }
982
983 switch (output_interface) {
984 case INTERFACE_DVP0:
985 if (set_iga == IGA1) {
986 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
987 } else {
988 viafb_write_reg(CR91, VIACR, 0x00);
989 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
990 }
991 break;
992
993 case INTERFACE_DVP1:
994 if (set_iga == IGA1)
995 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
996 else {
997 viafb_write_reg(CR91, VIACR, 0x00);
998 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
999 }
1000 break;
1001
1002 case INTERFACE_DFP_HIGH:
1003 if (set_iga == IGA1)
1004 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1005 else {
1006 viafb_write_reg(CR91, VIACR, 0x00);
1007 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1008 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
1009 }
1010 break;
1011
1012 case INTERFACE_DFP_LOW:
1013 if (set_iga == IGA1)
1014 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1015 else {
1016 viafb_write_reg(CR91, VIACR, 0x00);
1017 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1018 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
1019 }
1020
1021 break;
1022
1023 case INTERFACE_DFP:
1024 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
1025 || (UNICHROME_P4M890 ==
1026 viaparinfo->chip_info->gfx_chip_name))
1027 viafb_write_reg_mask(CR97, VIACR, 0x84,
1028 BIT7 + BIT2 + BIT1 + BIT0);
1029 if (set_iga == IGA1) {
1030 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1031 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1032 } else {
1033 viafb_write_reg(CR91, VIACR, 0x00);
1034 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1035 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1036 }
1037 break;
1038
1039 case INTERFACE_LVDS0:
1040 case INTERFACE_LVDS0LVDS1:
1041 if (set_iga == IGA1)
1042 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1043 else
1044 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1045
1046 break;
1047
1048 case INTERFACE_LVDS1:
1049 if (set_iga == IGA1)
1050 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1051 else
1052 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1053 break;
1054 }
1055}
1056
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1057static void load_fix_bit_crtc_reg(void)
1058{
1059 /* always set to 1 */
1060 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1061 /* line compare should set all bits = 1 (extend modes) */
1062 viafb_write_reg(CR18, VIACR, 0xff);
1063 /* line compare should set all bits = 1 (extend modes) */
1064 viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1065 /* line compare should set all bits = 1 (extend modes) */
1066 viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1067 /* line compare should set all bits = 1 (extend modes) */
1068 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1069 /* line compare should set all bits = 1 (extend modes) */
1070 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1071 /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1072 /* extend mode always set to e3h */
1073 viafb_write_reg(CR17, VIACR, 0xe3);
1074 /* extend mode always set to 0h */
1075 viafb_write_reg(CR08, VIACR, 0x00);
1076 /* extend mode always set to 0h */
1077 viafb_write_reg(CR14, VIACR, 0x00);
1078
1079 /* If K8M800, enable Prefetch Mode. */
1080 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1081 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1082 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1083 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1084 && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1085 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1086
1087}
1088
1089void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1090 struct io_register *reg,
1091 int io_type)
1092{
1093 int reg_mask;
1094 int bit_num = 0;
1095 int data;
1096 int i, j;
1097 int shift_next_reg;
1098 int start_index, end_index, cr_index;
1099 u16 get_bit;
1100
1101 for (i = 0; i < viafb_load_reg_num; i++) {
1102 reg_mask = 0;
1103 data = 0;
1104 start_index = reg[i].start_bit;
1105 end_index = reg[i].end_bit;
1106 cr_index = reg[i].io_addr;
1107
1108 shift_next_reg = bit_num;
1109 for (j = start_index; j <= end_index; j++) {
1110 /*if (bit_num==8) timing_value = timing_value >>8; */
1111 reg_mask = reg_mask | (BIT0 << j);
1112 get_bit = (timing_value & (BIT0 << bit_num));
1113 data =
1114 data | ((get_bit >> shift_next_reg) << start_index);
1115 bit_num++;
1116 }
1117 if (io_type == VIACR)
1118 viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1119 else
1120 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1121 }
1122
1123}
1124
1125/* Write Registers */
1126void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1127{
1128 int i;
1129 unsigned char RegTemp;
1130
1131 /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1132
1133 for (i = 0; i < ItemNum; i++) {
1134 outb(RegTable[i].index, RegTable[i].port);
1135 RegTemp = inb(RegTable[i].port + 1);
1136 RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value;
1137 outb(RegTemp, RegTable[i].port + 1);
1138 }
1139}
1140
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1141void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1142{
1143 int reg_value;
1144 int viafb_load_reg_num;
1145 struct io_register *reg = NULL;
1146
1147 switch (set_iga) {
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1148 case IGA1:
1149 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1150 viafb_load_reg_num = fetch_count_reg.
1151 iga1_fetch_count_reg.reg_num;
1152 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1153 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
Florian Tobias Schandinat4bbac052010-03-10 15:21:36 -0800[diff] [blame]1154 break;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1155 case IGA2:
1156 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1157 viafb_load_reg_num = fetch_count_reg.
1158 iga2_fetch_count_reg.reg_num;
1159 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1160 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1161 break;
1162 }
1163
1164}
1165
1166void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1167{
1168 int reg_value;
1169 int viafb_load_reg_num;
1170 struct io_register *reg = NULL;
1171 int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1172 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1173 int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1174 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1175
1176 if (set_iga == IGA1) {
1177 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1178 iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1179 iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1180 iga1_fifo_high_threshold =
1181 K800_IGA1_FIFO_HIGH_THRESHOLD;
1182 /* If resolution > 1280x1024, expire length = 64, else
1183 expire length = 128 */
1184 if ((hor_active > 1280) && (ver_active > 1024))
1185 iga1_display_queue_expire_num = 16;
1186 else
1187 iga1_display_queue_expire_num =
1188 K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1189
1190 }
1191
1192 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1193 iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1194 iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1195 iga1_fifo_high_threshold =
1196 P880_IGA1_FIFO_HIGH_THRESHOLD;
1197 iga1_display_queue_expire_num =
1198 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1199
1200 /* If resolution > 1280x1024, expire length = 64, else
1201 expire length = 128 */
1202 if ((hor_active > 1280) && (ver_active > 1024))
1203 iga1_display_queue_expire_num = 16;
1204 else
1205 iga1_display_queue_expire_num =
1206 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1207 }
1208
1209 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1210 iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1211 iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1212 iga1_fifo_high_threshold =
1213 CN700_IGA1_FIFO_HIGH_THRESHOLD;
1214
1215 /* If resolution > 1280x1024, expire length = 64,
1216 else expire length = 128 */
1217 if ((hor_active > 1280) && (ver_active > 1024))
1218 iga1_display_queue_expire_num = 16;
1219 else
1220 iga1_display_queue_expire_num =
1221 CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1222 }
1223
1224 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1225 iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1226 iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1227 iga1_fifo_high_threshold =
1228 CX700_IGA1_FIFO_HIGH_THRESHOLD;
1229 iga1_display_queue_expire_num =
1230 CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1231 }
1232
1233 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1234 iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1235 iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1236 iga1_fifo_high_threshold =
1237 K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1238 iga1_display_queue_expire_num =
1239 K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1240 }
1241
1242 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1243 iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1244 iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1245 iga1_fifo_high_threshold =
1246 P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1247 iga1_display_queue_expire_num =
1248 P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1249 }
1250
1251 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1252 iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1253 iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1254 iga1_fifo_high_threshold =
1255 P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1256 iga1_display_queue_expire_num =
1257 P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1258 }
1259
1260 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1261 iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1262 iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1263 iga1_fifo_high_threshold =
1264 VX800_IGA1_FIFO_HIGH_THRESHOLD;
1265 iga1_display_queue_expire_num =
1266 VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1267 }
1268
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]1269 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1270 iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1271 iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1272 iga1_fifo_high_threshold =
1273 VX855_IGA1_FIFO_HIGH_THRESHOLD;
1274 iga1_display_queue_expire_num =
1275 VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1276 }
1277
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1278 /* Set Display FIFO Depath Select */
1279 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1280 viafb_load_reg_num =
1281 display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1282 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1283 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1284
1285 /* Set Display FIFO Threshold Select */
1286 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1287 viafb_load_reg_num =
1288 fifo_threshold_select_reg.
1289 iga1_fifo_threshold_select_reg.reg_num;
1290 reg =
1291 fifo_threshold_select_reg.
1292 iga1_fifo_threshold_select_reg.reg;
1293 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1294
1295 /* Set FIFO High Threshold Select */
1296 reg_value =
1297 IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1298 viafb_load_reg_num =
1299 fifo_high_threshold_select_reg.
1300 iga1_fifo_high_threshold_select_reg.reg_num;
1301 reg =
1302 fifo_high_threshold_select_reg.
1303 iga1_fifo_high_threshold_select_reg.reg;
1304 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1305
1306 /* Set Display Queue Expire Num */
1307 reg_value =
1308 IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1309 (iga1_display_queue_expire_num);
1310 viafb_load_reg_num =
1311 display_queue_expire_num_reg.
1312 iga1_display_queue_expire_num_reg.reg_num;
1313 reg =
1314 display_queue_expire_num_reg.
1315 iga1_display_queue_expire_num_reg.reg;
1316 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1317
1318 } else {
1319 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1320 iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1321 iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1322 iga2_fifo_high_threshold =
1323 K800_IGA2_FIFO_HIGH_THRESHOLD;
1324
1325 /* If resolution > 1280x1024, expire length = 64,
1326 else expire length = 128 */
1327 if ((hor_active > 1280) && (ver_active > 1024))
1328 iga2_display_queue_expire_num = 16;
1329 else
1330 iga2_display_queue_expire_num =
1331 K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1332 }
1333
1334 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1335 iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1336 iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1337 iga2_fifo_high_threshold =
1338 P880_IGA2_FIFO_HIGH_THRESHOLD;
1339
1340 /* If resolution > 1280x1024, expire length = 64,
1341 else expire length = 128 */
1342 if ((hor_active > 1280) && (ver_active > 1024))
1343 iga2_display_queue_expire_num = 16;
1344 else
1345 iga2_display_queue_expire_num =
1346 P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1347 }
1348
1349 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1350 iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1351 iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1352 iga2_fifo_high_threshold =
1353 CN700_IGA2_FIFO_HIGH_THRESHOLD;
1354
1355 /* If resolution > 1280x1024, expire length = 64,
1356 else expire length = 128 */
1357 if ((hor_active > 1280) && (ver_active > 1024))
1358 iga2_display_queue_expire_num = 16;
1359 else
1360 iga2_display_queue_expire_num =
1361 CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1362 }
1363
1364 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1365 iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1366 iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1367 iga2_fifo_high_threshold =
1368 CX700_IGA2_FIFO_HIGH_THRESHOLD;
1369 iga2_display_queue_expire_num =
1370 CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1371 }
1372
1373 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1374 iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1375 iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1376 iga2_fifo_high_threshold =
1377 K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1378 iga2_display_queue_expire_num =
1379 K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1380 }
1381
1382 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1383 iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1384 iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1385 iga2_fifo_high_threshold =
1386 P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1387 iga2_display_queue_expire_num =
1388 P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1389 }
1390
1391 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1392 iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1393 iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1394 iga2_fifo_high_threshold =
1395 P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1396 iga2_display_queue_expire_num =
1397 P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1398 }
1399
1400 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1401 iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1402 iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1403 iga2_fifo_high_threshold =
1404 VX800_IGA2_FIFO_HIGH_THRESHOLD;
1405 iga2_display_queue_expire_num =
1406 VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1407 }
1408
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]1409 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1410 iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1411 iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1412 iga2_fifo_high_threshold =
1413 VX855_IGA2_FIFO_HIGH_THRESHOLD;
1414 iga2_display_queue_expire_num =
1415 VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1416 }
1417
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1418 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1419 /* Set Display FIFO Depath Select */
1420 reg_value =
1421 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1422 - 1;
1423 /* Patch LCD in IGA2 case */
1424 viafb_load_reg_num =
1425 display_fifo_depth_reg.
1426 iga2_fifo_depth_select_reg.reg_num;
1427 reg =
1428 display_fifo_depth_reg.
1429 iga2_fifo_depth_select_reg.reg;
1430 viafb_load_reg(reg_value,
1431 viafb_load_reg_num, reg, VIACR);
1432 } else {
1433
1434 /* Set Display FIFO Depath Select */
1435 reg_value =
1436 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1437 viafb_load_reg_num =
1438 display_fifo_depth_reg.
1439 iga2_fifo_depth_select_reg.reg_num;
1440 reg =
1441 display_fifo_depth_reg.
1442 iga2_fifo_depth_select_reg.reg;
1443 viafb_load_reg(reg_value,
1444 viafb_load_reg_num, reg, VIACR);
1445 }
1446
1447 /* Set Display FIFO Threshold Select */
1448 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1449 viafb_load_reg_num =
1450 fifo_threshold_select_reg.
1451 iga2_fifo_threshold_select_reg.reg_num;
1452 reg =
1453 fifo_threshold_select_reg.
1454 iga2_fifo_threshold_select_reg.reg;
1455 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1456
1457 /* Set FIFO High Threshold Select */
1458 reg_value =
1459 IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1460 viafb_load_reg_num =
1461 fifo_high_threshold_select_reg.
1462 iga2_fifo_high_threshold_select_reg.reg_num;
1463 reg =
1464 fifo_high_threshold_select_reg.
1465 iga2_fifo_high_threshold_select_reg.reg;
1466 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1467
1468 /* Set Display Queue Expire Num */
1469 reg_value =
1470 IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1471 (iga2_display_queue_expire_num);
1472 viafb_load_reg_num =
1473 display_queue_expire_num_reg.
1474 iga2_display_queue_expire_num_reg.reg_num;
1475 reg =
1476 display_queue_expire_num_reg.
1477 iga2_display_queue_expire_num_reg.reg;
1478 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1479
1480 }
1481
1482}
1483
1484u32 viafb_get_clk_value(int clk)
1485{
1486 int i;
1487
1488 for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
1489 if (clk == pll_value[i].clk) {
1490 switch (viaparinfo->chip_info->gfx_chip_name) {
1491 case UNICHROME_CLE266:
1492 case UNICHROME_K400:
1493 return pll_value[i].cle266_pll;
1494
1495 case UNICHROME_K800:
1496 case UNICHROME_PM800:
1497 case UNICHROME_CN700:
1498 return pll_value[i].k800_pll;
1499
1500 case UNICHROME_CX700:
1501 case UNICHROME_K8M890:
1502 case UNICHROME_P4M890:
1503 case UNICHROME_P4M900:
1504 case UNICHROME_VX800:
1505 return pll_value[i].cx700_pll;
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]1506 case UNICHROME_VX855:
1507 return pll_value[i].vx855_pll;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1508 }
1509 }
1510 }
1511
1512 DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
1513 return 0;
1514}
1515
1516/* Set VCLK*/
1517void viafb_set_vclock(u32 CLK, int set_iga)
1518{
1519 unsigned char RegTemp;
1520
1521 /* H.W. Reset : ON */
1522 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1523
Florian Tobias Schandinat4bbac052010-03-10 15:21:36 -0800[diff] [blame]1524 if (set_iga == IGA1) {
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1525 /* Change D,N FOR VCLK */
1526 switch (viaparinfo->chip_info->gfx_chip_name) {
1527 case UNICHROME_CLE266:
1528 case UNICHROME_K400:
1529 viafb_write_reg(SR46, VIASR, CLK / 0x100);
1530 viafb_write_reg(SR47, VIASR, CLK % 0x100);
1531 break;
1532
1533 case UNICHROME_K800:
1534 case UNICHROME_PM800:
1535 case UNICHROME_CN700:
1536 case UNICHROME_CX700:
1537 case UNICHROME_K8M890:
1538 case UNICHROME_P4M890:
1539 case UNICHROME_P4M900:
1540 case UNICHROME_VX800:
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]1541 case UNICHROME_VX855:
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1542 viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1543 DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1544 viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
1545 DEBUG_MSG(KERN_INFO "\nSR45=%x",
1546 (CLK & 0xFFFF) / 0x100);
1547 viafb_write_reg(SR46, VIASR, CLK % 0x100);
1548 DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1549 break;
1550 }
1551 }
1552
Florian Tobias Schandinat4bbac052010-03-10 15:21:36 -0800[diff] [blame]1553 if (set_iga == IGA2) {
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1554 /* Change D,N FOR LCK */
1555 switch (viaparinfo->chip_info->gfx_chip_name) {
1556 case UNICHROME_CLE266:
1557 case UNICHROME_K400:
1558 viafb_write_reg(SR44, VIASR, CLK / 0x100);
1559 viafb_write_reg(SR45, VIASR, CLK % 0x100);
1560 break;
1561
1562 case UNICHROME_K800:
1563 case UNICHROME_PM800:
1564 case UNICHROME_CN700:
1565 case UNICHROME_CX700:
1566 case UNICHROME_K8M890:
1567 case UNICHROME_P4M890:
1568 case UNICHROME_P4M900:
1569 case UNICHROME_VX800:
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]1570 case UNICHROME_VX855:
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1571 viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1572 viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1573 viafb_write_reg(SR4C, VIASR, CLK % 0x100);
1574 break;
1575 }
1576 }
1577
1578 /* H.W. Reset : OFF */
1579 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1580
1581 /* Reset PLL */
Florian Tobias Schandinat4bbac052010-03-10 15:21:36 -0800[diff] [blame]1582 if (set_iga == IGA1) {
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1583 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1584 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1585 }
1586
Florian Tobias Schandinat4bbac052010-03-10 15:21:36 -0800[diff] [blame]1587 if (set_iga == IGA2) {
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1588 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1589 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1590 }
1591
1592 /* Fire! */
1593 RegTemp = inb(VIARMisc);
1594 outb(RegTemp | (BIT2 + BIT3), VIAWMisc);
1595}
1596
1597void viafb_load_crtc_timing(struct display_timing device_timing,
1598 int set_iga)
1599{
1600 int i;
1601 int viafb_load_reg_num = 0;
1602 int reg_value = 0;
1603 struct io_register *reg = NULL;
1604
1605 viafb_unlock_crt();
1606
1607 for (i = 0; i < 12; i++) {
1608 if (set_iga == IGA1) {
1609 switch (i) {
1610 case H_TOTAL_INDEX:
1611 reg_value =
1612 IGA1_HOR_TOTAL_FORMULA(device_timing.
1613 hor_total);
1614 viafb_load_reg_num =
1615 iga1_crtc_reg.hor_total.reg_num;
1616 reg = iga1_crtc_reg.hor_total.reg;
1617 break;
1618 case H_ADDR_INDEX:
1619 reg_value =
1620 IGA1_HOR_ADDR_FORMULA(device_timing.
1621 hor_addr);
1622 viafb_load_reg_num =
1623 iga1_crtc_reg.hor_addr.reg_num;
1624 reg = iga1_crtc_reg.hor_addr.reg;
1625 break;
1626 case H_BLANK_START_INDEX:
1627 reg_value =
1628 IGA1_HOR_BLANK_START_FORMULA
1629 (device_timing.hor_blank_start);
1630 viafb_load_reg_num =
1631 iga1_crtc_reg.hor_blank_start.reg_num;
1632 reg = iga1_crtc_reg.hor_blank_start.reg;
1633 break;
1634 case H_BLANK_END_INDEX:
1635 reg_value =
1636 IGA1_HOR_BLANK_END_FORMULA
1637 (device_timing.hor_blank_start,
1638 device_timing.hor_blank_end);
1639 viafb_load_reg_num =
1640 iga1_crtc_reg.hor_blank_end.reg_num;
1641 reg = iga1_crtc_reg.hor_blank_end.reg;
1642 break;
1643 case H_SYNC_START_INDEX:
1644 reg_value =
1645 IGA1_HOR_SYNC_START_FORMULA
1646 (device_timing.hor_sync_start);
1647 viafb_load_reg_num =
1648 iga1_crtc_reg.hor_sync_start.reg_num;
1649 reg = iga1_crtc_reg.hor_sync_start.reg;
1650 break;
1651 case H_SYNC_END_INDEX:
1652 reg_value =
1653 IGA1_HOR_SYNC_END_FORMULA
1654 (device_timing.hor_sync_start,
1655 device_timing.hor_sync_end);
1656 viafb_load_reg_num =
1657 iga1_crtc_reg.hor_sync_end.reg_num;
1658 reg = iga1_crtc_reg.hor_sync_end.reg;
1659 break;
1660 case V_TOTAL_INDEX:
1661 reg_value =
1662 IGA1_VER_TOTAL_FORMULA(device_timing.
1663 ver_total);
1664 viafb_load_reg_num =
1665 iga1_crtc_reg.ver_total.reg_num;
1666 reg = iga1_crtc_reg.ver_total.reg;
1667 break;
1668 case V_ADDR_INDEX:
1669 reg_value =
1670 IGA1_VER_ADDR_FORMULA(device_timing.
1671 ver_addr);
1672 viafb_load_reg_num =
1673 iga1_crtc_reg.ver_addr.reg_num;
1674 reg = iga1_crtc_reg.ver_addr.reg;
1675 break;
1676 case V_BLANK_START_INDEX:
1677 reg_value =
1678 IGA1_VER_BLANK_START_FORMULA
1679 (device_timing.ver_blank_start);
1680 viafb_load_reg_num =
1681 iga1_crtc_reg.ver_blank_start.reg_num;
1682 reg = iga1_crtc_reg.ver_blank_start.reg;
1683 break;
1684 case V_BLANK_END_INDEX:
1685 reg_value =
1686 IGA1_VER_BLANK_END_FORMULA
1687 (device_timing.ver_blank_start,
1688 device_timing.ver_blank_end);
1689 viafb_load_reg_num =
1690 iga1_crtc_reg.ver_blank_end.reg_num;
1691 reg = iga1_crtc_reg.ver_blank_end.reg;
1692 break;
1693 case V_SYNC_START_INDEX:
1694 reg_value =
1695 IGA1_VER_SYNC_START_FORMULA
1696 (device_timing.ver_sync_start);
1697 viafb_load_reg_num =
1698 iga1_crtc_reg.ver_sync_start.reg_num;
1699 reg = iga1_crtc_reg.ver_sync_start.reg;
1700 break;
1701 case V_SYNC_END_INDEX:
1702 reg_value =
1703 IGA1_VER_SYNC_END_FORMULA
1704 (device_timing.ver_sync_start,
1705 device_timing.ver_sync_end);
1706 viafb_load_reg_num =
1707 iga1_crtc_reg.ver_sync_end.reg_num;
1708 reg = iga1_crtc_reg.ver_sync_end.reg;
1709 break;
1710
1711 }
1712 }
1713
1714 if (set_iga == IGA2) {
1715 switch (i) {
1716 case H_TOTAL_INDEX:
1717 reg_value =
1718 IGA2_HOR_TOTAL_FORMULA(device_timing.
1719 hor_total);
1720 viafb_load_reg_num =
1721 iga2_crtc_reg.hor_total.reg_num;
1722 reg = iga2_crtc_reg.hor_total.reg;
1723 break;
1724 case H_ADDR_INDEX:
1725 reg_value =
1726 IGA2_HOR_ADDR_FORMULA(device_timing.
1727 hor_addr);
1728 viafb_load_reg_num =
1729 iga2_crtc_reg.hor_addr.reg_num;
1730 reg = iga2_crtc_reg.hor_addr.reg;
1731 break;
1732 case H_BLANK_START_INDEX:
1733 reg_value =
1734 IGA2_HOR_BLANK_START_FORMULA
1735 (device_timing.hor_blank_start);
1736 viafb_load_reg_num =
1737 iga2_crtc_reg.hor_blank_start.reg_num;
1738 reg = iga2_crtc_reg.hor_blank_start.reg;
1739 break;
1740 case H_BLANK_END_INDEX:
1741 reg_value =
1742 IGA2_HOR_BLANK_END_FORMULA
1743 (device_timing.hor_blank_start,
1744 device_timing.hor_blank_end);
1745 viafb_load_reg_num =
1746 iga2_crtc_reg.hor_blank_end.reg_num;
1747 reg = iga2_crtc_reg.hor_blank_end.reg;
1748 break;
1749 case H_SYNC_START_INDEX:
1750 reg_value =
1751 IGA2_HOR_SYNC_START_FORMULA
1752 (device_timing.hor_sync_start);
1753 if (UNICHROME_CN700 <=
1754 viaparinfo->chip_info->gfx_chip_name)
1755 viafb_load_reg_num =
1756 iga2_crtc_reg.hor_sync_start.
1757 reg_num;
1758 else
1759 viafb_load_reg_num = 3;
1760 reg = iga2_crtc_reg.hor_sync_start.reg;
1761 break;
1762 case H_SYNC_END_INDEX:
1763 reg_value =
1764 IGA2_HOR_SYNC_END_FORMULA
1765 (device_timing.hor_sync_start,
1766 device_timing.hor_sync_end);
1767 viafb_load_reg_num =
1768 iga2_crtc_reg.hor_sync_end.reg_num;
1769 reg = iga2_crtc_reg.hor_sync_end.reg;
1770 break;
1771 case V_TOTAL_INDEX:
1772 reg_value =
1773 IGA2_VER_TOTAL_FORMULA(device_timing.
1774 ver_total);
1775 viafb_load_reg_num =
1776 iga2_crtc_reg.ver_total.reg_num;
1777 reg = iga2_crtc_reg.ver_total.reg;
1778 break;
1779 case V_ADDR_INDEX:
1780 reg_value =
1781 IGA2_VER_ADDR_FORMULA(device_timing.
1782 ver_addr);
1783 viafb_load_reg_num =
1784 iga2_crtc_reg.ver_addr.reg_num;
1785 reg = iga2_crtc_reg.ver_addr.reg;
1786 break;
1787 case V_BLANK_START_INDEX:
1788 reg_value =
1789 IGA2_VER_BLANK_START_FORMULA
1790 (device_timing.ver_blank_start);
1791 viafb_load_reg_num =
1792 iga2_crtc_reg.ver_blank_start.reg_num;
1793 reg = iga2_crtc_reg.ver_blank_start.reg;
1794 break;
1795 case V_BLANK_END_INDEX:
1796 reg_value =
1797 IGA2_VER_BLANK_END_FORMULA
1798 (device_timing.ver_blank_start,
1799 device_timing.ver_blank_end);
1800 viafb_load_reg_num =
1801 iga2_crtc_reg.ver_blank_end.reg_num;
1802 reg = iga2_crtc_reg.ver_blank_end.reg;
1803 break;
1804 case V_SYNC_START_INDEX:
1805 reg_value =
1806 IGA2_VER_SYNC_START_FORMULA
1807 (device_timing.ver_sync_start);
1808 viafb_load_reg_num =
1809 iga2_crtc_reg.ver_sync_start.reg_num;
1810 reg = iga2_crtc_reg.ver_sync_start.reg;
1811 break;
1812 case V_SYNC_END_INDEX:
1813 reg_value =
1814 IGA2_VER_SYNC_END_FORMULA
1815 (device_timing.ver_sync_start,
1816 device_timing.ver_sync_end);
1817 viafb_load_reg_num =
1818 iga2_crtc_reg.ver_sync_end.reg_num;
1819 reg = iga2_crtc_reg.ver_sync_end.reg;
1820 break;
1821
1822 }
1823 }
1824 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1825 }
1826
1827 viafb_lock_crt();
1828}
1829
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1830void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
Florian Tobias Schandinatdd73d6862010-03-10 15:21:28 -0800[diff] [blame]1831 struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1832{
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1833 struct display_timing crt_reg;
1834 int i;
1835 int index = 0;
1836 int h_addr, v_addr;
1837 u32 pll_D_N;
1838
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1839 for (i = 0; i < video_mode->mode_array; i++) {
1840 index = i;
1841
1842 if (crt_table[i].refresh_rate == viaparinfo->
1843 crt_setting_info->refresh_rate)
1844 break;
1845 }
1846
1847 crt_reg = crt_table[index].crtc;
1848
1849 /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1850 /* So we would delete border. */
Florian Tobias Schandinatdd73d6862010-03-10 15:21:28 -0800[diff] [blame]1851 if ((viafb_LCD_ON | viafb_DVI_ON)
1852 && video_mode->crtc[0].crtc.hor_addr == 640
1853 && video_mode->crtc[0].crtc.ver_addr == 480
1854 && viaparinfo->crt_setting_info->refresh_rate == 60) {
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1855 /* The border is 8 pixels. */
1856 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1857
1858 /* Blanking time should add left and right borders. */
1859 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1860 }
1861
1862 h_addr = crt_reg.hor_addr;
1863 v_addr = crt_reg.ver_addr;
1864
1865 /* update polarity for CRT timing */
1866 if (crt_table[index].h_sync_polarity == NEGATIVE) {
1867 if (crt_table[index].v_sync_polarity == NEGATIVE)
1868 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) |
1869 (BIT6 + BIT7), VIAWMisc);
1870 else
1871 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT6),
1872 VIAWMisc);
1873 } else {
1874 if (crt_table[index].v_sync_polarity == NEGATIVE)
1875 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT7),
1876 VIAWMisc);
1877 else
1878 outb((inb(VIARMisc) & (~(BIT6 + BIT7))), VIAWMisc);
1879 }
1880
1881 if (set_iga == IGA1) {
1882 viafb_unlock_crt();
1883 viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */
1884 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1885 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1886 }
1887
1888 switch (set_iga) {
1889 case IGA1:
1890 viafb_load_crtc_timing(crt_reg, IGA1);
1891 break;
1892 case IGA2:
1893 viafb_load_crtc_timing(crt_reg, IGA2);
1894 break;
1895 }
1896
1897 load_fix_bit_crtc_reg();
1898 viafb_lock_crt();
1899 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1900 viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1901
1902 /* load FIFO */
1903 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1904 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1905 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1906
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1907 pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1908 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1909 viafb_set_vclock(pll_D_N, set_iga);
1910
1911}
1912
Harald Welte2d280f72009-09-22 16:47:37 -0700[diff] [blame]1913void viafb_init_chip_info(struct pci_dev *pdev,
1914 const struct pci_device_id *pdi)
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1915{
Harald Welte2d280f72009-09-22 16:47:37 -0700[diff] [blame]1916 init_gfx_chip_info(pdev, pdi);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1917 init_tmds_chip_info();
1918 init_lvds_chip_info();
1919
1920 viaparinfo->crt_setting_info->iga_path = IGA1;
1921 viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1922
1923 /*Set IGA path for each device */
1924 viafb_set_iga_path();
1925
1926 viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1927 viaparinfo->lvds_setting_info->get_lcd_size_method =
1928 GET_LCD_SIZE_BY_USER_SETTING;
1929 viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1930 viaparinfo->lvds_setting_info2->display_method =
1931 viaparinfo->lvds_setting_info->display_method;
1932 viaparinfo->lvds_setting_info2->lcd_mode =
1933 viaparinfo->lvds_setting_info->lcd_mode;
1934}
1935
1936void viafb_update_device_setting(int hres, int vres,
1937 int bpp, int vmode_refresh, int flag)
1938{
1939 if (flag == 0) {
1940 viaparinfo->crt_setting_info->h_active = hres;
1941 viaparinfo->crt_setting_info->v_active = vres;
1942 viaparinfo->crt_setting_info->bpp = bpp;
1943 viaparinfo->crt_setting_info->refresh_rate =
1944 vmode_refresh;
1945
1946 viaparinfo->tmds_setting_info->h_active = hres;
1947 viaparinfo->tmds_setting_info->v_active = vres;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1948
1949 viaparinfo->lvds_setting_info->h_active = hres;
1950 viaparinfo->lvds_setting_info->v_active = vres;
1951 viaparinfo->lvds_setting_info->bpp = bpp;
1952 viaparinfo->lvds_setting_info->refresh_rate =
1953 vmode_refresh;
1954 viaparinfo->lvds_setting_info2->h_active = hres;
1955 viaparinfo->lvds_setting_info2->v_active = vres;
1956 viaparinfo->lvds_setting_info2->bpp = bpp;
1957 viaparinfo->lvds_setting_info2->refresh_rate =
1958 vmode_refresh;
1959 } else {
1960
1961 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1962 viaparinfo->tmds_setting_info->h_active = hres;
1963 viaparinfo->tmds_setting_info->v_active = vres;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1964 }
1965
1966 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1967 viaparinfo->lvds_setting_info->h_active = hres;
1968 viaparinfo->lvds_setting_info->v_active = vres;
1969 viaparinfo->lvds_setting_info->bpp = bpp;
1970 viaparinfo->lvds_setting_info->refresh_rate =
1971 vmode_refresh;
1972 }
1973 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1974 viaparinfo->lvds_setting_info2->h_active = hres;
1975 viaparinfo->lvds_setting_info2->v_active = vres;
1976 viaparinfo->lvds_setting_info2->bpp = bpp;
1977 viaparinfo->lvds_setting_info2->refresh_rate =
1978 vmode_refresh;
1979 }
1980 }
1981}
1982
Harald Welte2d280f72009-09-22 16:47:37 -0700[diff] [blame]1983static void init_gfx_chip_info(struct pci_dev *pdev,
1984 const struct pci_device_id *pdi)
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1985{
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1986 u8 tmp;
1987
Harald Welte2d280f72009-09-22 16:47:37 -0700[diff] [blame]1988 viaparinfo->chip_info->gfx_chip_name = pdi->driver_data;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]1989
1990 /* Check revision of CLE266 Chip */
1991 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1992 /* CR4F only define in CLE266.CX chip */
1993 tmp = viafb_read_reg(VIACR, CR4F);
1994 viafb_write_reg(CR4F, VIACR, 0x55);
1995 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1996 viaparinfo->chip_info->gfx_chip_revision =
1997 CLE266_REVISION_AX;
1998 else
1999 viaparinfo->chip_info->gfx_chip_revision =
2000 CLE266_REVISION_CX;
2001 /* restore orignal CR4F value */
2002 viafb_write_reg(CR4F, VIACR, tmp);
2003 }
2004
2005 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
2006 tmp = viafb_read_reg(VIASR, SR43);
2007 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
2008 if (tmp & 0x02) {
2009 viaparinfo->chip_info->gfx_chip_revision =
2010 CX700_REVISION_700M2;
2011 } else if (tmp & 0x40) {
2012 viaparinfo->chip_info->gfx_chip_revision =
2013 CX700_REVISION_700M;
2014 } else {
2015 viaparinfo->chip_info->gfx_chip_revision =
2016 CX700_REVISION_700;
2017 }
2018 }
Harald Welte107ea342009-05-20 01:36:03 +0800[diff] [blame^]2019
2020 /* Determine which 2D engine we have */
2021 switch (viaparinfo->chip_info->gfx_chip_name) {
2022 case UNICHROME_VX800:
2023 case UNICHROME_VX855:
2024 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
2025 break;
2026 case UNICHROME_K8M890:
2027 case UNICHROME_P4M900:
2028 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
2029 break;
2030 default:
2031 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
2032 break;
2033 }
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2034}
2035
2036static void init_tmds_chip_info(void)
2037{
2038 viafb_tmds_trasmitter_identify();
2039
2040 if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2041 output_interface) {
2042 switch (viaparinfo->chip_info->gfx_chip_name) {
2043 case UNICHROME_CX700:
2044 {
2045 /* we should check support by hardware layout.*/
2046 if ((viafb_display_hardware_layout ==
2047 HW_LAYOUT_DVI_ONLY)
2048 || (viafb_display_hardware_layout ==
2049 HW_LAYOUT_LCD_DVI)) {
2050 viaparinfo->chip_info->tmds_chip_info.
2051 output_interface = INTERFACE_TMDS;
2052 } else {
2053 viaparinfo->chip_info->tmds_chip_info.
2054 output_interface =
2055 INTERFACE_NONE;
2056 }
2057 break;
2058 }
2059 case UNICHROME_K8M890:
2060 case UNICHROME_P4M900:
2061 case UNICHROME_P4M890:
2062 /* TMDS on PCIE, we set DFPLOW as default. */
2063 viaparinfo->chip_info->tmds_chip_info.output_interface =
2064 INTERFACE_DFP_LOW;
2065 break;
2066 default:
2067 {
2068 /* set DVP1 default for DVI */
2069 viaparinfo->chip_info->tmds_chip_info
2070 .output_interface = INTERFACE_DVP1;
2071 }
2072 }
2073 }
2074
2075 DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2076 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
Florian Tobias Schandinatc5f06f52010-03-10 15:21:30 -0800[diff] [blame]2077 viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2078 &viaparinfo->shared->tmds_setting_info);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2079}
2080
2081static void init_lvds_chip_info(void)
2082{
2083 if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
2084 viaparinfo->lvds_setting_info->get_lcd_size_method =
2085 GET_LCD_SIZE_BY_VGA_BIOS;
2086 else
2087 viaparinfo->lvds_setting_info->get_lcd_size_method =
2088 GET_LCD_SIZE_BY_USER_SETTING;
2089
2090 viafb_lvds_trasmitter_identify();
2091 viafb_init_lcd_size();
2092 viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2093 viaparinfo->lvds_setting_info);
2094 if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2095 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2096 lvds_chip_info2, viaparinfo->lvds_setting_info2);
2097 }
2098 /*If CX700,two singel LCD, we need to reassign
2099 LCD interface to different LVDS port */
2100 if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2101 && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2102 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2103 lvds_chip_name) && (INTEGRATED_LVDS ==
2104 viaparinfo->chip_info->
2105 lvds_chip_info2.lvds_chip_name)) {
2106 viaparinfo->chip_info->lvds_chip_info.output_interface =
2107 INTERFACE_LVDS0;
2108 viaparinfo->chip_info->lvds_chip_info2.
2109 output_interface =
2110 INTERFACE_LVDS1;
2111 }
2112 }
2113
2114 DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2115 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2116 DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2117 viaparinfo->chip_info->lvds_chip_info.output_interface);
2118 DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2119 viaparinfo->chip_info->lvds_chip_info.output_interface);
2120}
2121
2122void viafb_init_dac(int set_iga)
2123{
2124 int i;
2125 u8 tmp;
2126
2127 if (set_iga == IGA1) {
2128 /* access Primary Display's LUT */
2129 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2130 /* turn off LCK */
2131 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2132 for (i = 0; i < 256; i++) {
2133 write_dac_reg(i, palLUT_table[i].red,
2134 palLUT_table[i].green,
2135 palLUT_table[i].blue);
2136 }
2137 /* turn on LCK */
2138 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2139 } else {
2140 tmp = viafb_read_reg(VIACR, CR6A);
2141 /* access Secondary Display's LUT */
2142 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2143 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2144 for (i = 0; i < 256; i++) {
2145 write_dac_reg(i, palLUT_table[i].red,
2146 palLUT_table[i].green,
2147 palLUT_table[i].blue);
2148 }
2149 /* set IGA1 DAC for default */
2150 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2151 viafb_write_reg(CR6A, VIACR, tmp);
2152 }
2153}
2154
2155static void device_screen_off(void)
2156{
2157 /* turn off CRT screen (IGA1) */
2158 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2159}
2160
2161static void device_screen_on(void)
2162{
2163 /* turn on CRT screen (IGA1) */
2164 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2165}
2166
2167static void set_display_channel(void)
2168{
2169 /*If viafb_LCD2_ON, on cx700, internal lvds's information
2170 is keeped on lvds_setting_info2 */
2171 if (viafb_LCD2_ON &&
2172 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2173 /* For dual channel LCD: */
2174 /* Set to Dual LVDS channel. */
2175 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2176 } else if (viafb_LCD_ON && viafb_DVI_ON) {
2177 /* For LCD+DFP: */
2178 /* Set to LVDS1 + TMDS channel. */
2179 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2180 } else if (viafb_DVI_ON) {
2181 /* Set to single TMDS channel. */
2182 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2183 } else if (viafb_LCD_ON) {
2184 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2185 /* For dual channel LCD: */
2186 /* Set to Dual LVDS channel. */
2187 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2188 } else {
2189 /* Set to LVDS0 + LVDS1 channel. */
2190 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2191 }
2192 }
2193}
2194
Florian Tobias Schandinatdd73d6862010-03-10 15:21:28 -0800[diff] [blame]2195int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2196 struct VideoModeTable *vmode_tbl1, int video_bpp1)
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2197{
2198 int i, j;
2199 int port;
2200 u8 value, index, mask;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2201 struct crt_mode_table *crt_timing;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2202 struct crt_mode_table *crt_timing1 = NULL;
2203
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2204 device_screen_off();
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2205 crt_timing = vmode_tbl->crtc;
2206
2207 if (viafb_SAMM_ON == 1) {
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2208 crt_timing1 = vmode_tbl1->crtc;
2209 }
2210
2211 inb(VIAStatus);
2212 outb(0x00, VIAAR);
2213
2214 /* Write Common Setting for Video Mode */
2215 switch (viaparinfo->chip_info->gfx_chip_name) {
2216 case UNICHROME_CLE266:
2217 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2218 break;
2219
2220 case UNICHROME_K400:
2221 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2222 break;
2223
2224 case UNICHROME_K800:
2225 case UNICHROME_PM800:
2226 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2227 break;
2228
2229 case UNICHROME_CN700:
2230 case UNICHROME_K8M890:
2231 case UNICHROME_P4M890:
2232 case UNICHROME_P4M900:
2233 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2234 break;
2235
2236 case UNICHROME_CX700:
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2237 case UNICHROME_VX800:
Florian Tobias Schandinat0e3ca332009-09-22 16:47:10 -0700[diff] [blame]2238 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2239 break;
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]2240
2241 case UNICHROME_VX855:
2242 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2243 break;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2244 }
2245
2246 device_off();
2247
2248 /* Fill VPIT Parameters */
2249 /* Write Misc Register */
2250 outb(VPIT.Misc, VIAWMisc);
2251
2252 /* Write Sequencer */
2253 for (i = 1; i <= StdSR; i++) {
2254 outb(i, VIASR);
2255 outb(VPIT.SR[i - 1], VIASR + 1);
2256 }
2257
Florian Tobias Schandinat415559f2010-03-10 15:21:40 -0800[diff] [blame]2258 viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2259 viafb_set_iga_path();
2260
2261 /* Write CRTC */
Florian Tobias Schandinatdd73d6862010-03-10 15:21:28 -0800[diff] [blame]2262 viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2263
2264 /* Write Graphic Controller */
2265 for (i = 0; i < StdGR; i++) {
2266 outb(i, VIAGR);
2267 outb(VPIT.GR[i], VIAGR + 1);
2268 }
2269
2270 /* Write Attribute Controller */
2271 for (i = 0; i < StdAR; i++) {
2272 inb(VIAStatus);
2273 outb(i, VIAAR);
2274 outb(VPIT.AR[i], VIAAR);
2275 }
2276
2277 inb(VIAStatus);
2278 outb(0x20, VIAAR);
2279
2280 /* Update Patch Register */
2281
Florian Tobias Schandinatdd73d6862010-03-10 15:21:28 -0800[diff] [blame]2282 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2283 || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2284 && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2285 && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2286 for (j = 0; j < res_patch_table[0].table_length; j++) {
2287 index = res_patch_table[0].io_reg_table[j].index;
2288 port = res_patch_table[0].io_reg_table[j].port;
2289 value = res_patch_table[0].io_reg_table[j].value;
2290 mask = res_patch_table[0].io_reg_table[j].mask;
2291 viafb_write_reg_mask(index, port, value, mask);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2292 }
2293 }
2294
Florian Tobias Schandinat2d6e8852009-09-22 16:47:29 -0700[diff] [blame]2295 viafb_set_primary_pitch(viafbinfo->fix.line_length);
2296 viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2297 : viafbinfo->fix.line_length);
Florian Tobias Schandinatdaacccd2010-03-10 15:21:35 -0800[diff] [blame]2298 viafb_set_primary_color_depth(viaparinfo->depth);
2299 viafb_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2300 : viaparinfo->depth);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2301 /* Update Refresh Rate Setting */
2302
2303 /* Clear On Screen */
2304
2305 /* CRT set mode */
2306 if (viafb_CRT_ON) {
2307 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2308 IGA2)) {
Florian Tobias Schandinatdd73d6862010-03-10 15:21:28 -0800[diff] [blame]2309 viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2310 video_bpp1 / 8,
2311 viaparinfo->crt_setting_info->iga_path);
2312 } else {
Florian Tobias Schandinatdd73d6862010-03-10 15:21:28 -0800[diff] [blame]2313 viafb_fill_crtc_timing(crt_timing, vmode_tbl,
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2314 video_bpp / 8,
2315 viaparinfo->crt_setting_info->iga_path);
2316 }
2317
2318 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2319
2320 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2321 to 8 alignment (1368),there is several pixels (2 pixels)
2322 on right side of screen. */
Florian Tobias Schandinatdd73d6862010-03-10 15:21:28 -0800[diff] [blame]2323 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2324 viafb_unlock_crt();
2325 viafb_write_reg(CR02, VIACR,
2326 viafb_read_reg(VIACR, CR02) - 1);
2327 viafb_lock_crt();
2328 }
2329 }
2330
2331 if (viafb_DVI_ON) {
2332 if (viafb_SAMM_ON &&
2333 (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
Florian Tobias Schandinatdd73d6862010-03-10 15:21:28 -0800[diff] [blame]2334 viafb_dvi_set_mode(viafb_get_mode
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2335 (viaparinfo->tmds_setting_info->h_active,
2336 viaparinfo->tmds_setting_info->
Florian Tobias Schandinat52159442009-08-06 15:07:34 -0700[diff] [blame]2337 v_active),
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2338 video_bpp1, viaparinfo->
2339 tmds_setting_info->iga_path);
2340 } else {
Florian Tobias Schandinatdd73d6862010-03-10 15:21:28 -0800[diff] [blame]2341 viafb_dvi_set_mode(viafb_get_mode
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2342 (viaparinfo->tmds_setting_info->h_active,
2343 viaparinfo->
Florian Tobias Schandinat52159442009-08-06 15:07:34 -0700[diff] [blame]2344 tmds_setting_info->v_active),
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2345 video_bpp, viaparinfo->
2346 tmds_setting_info->iga_path);
2347 }
2348 }
2349
2350 if (viafb_LCD_ON) {
2351 if (viafb_SAMM_ON &&
2352 (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2353 viaparinfo->lvds_setting_info->bpp = video_bpp1;
2354 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2355 lvds_setting_info,
2356 &viaparinfo->chip_info->lvds_chip_info);
2357 } else {
2358 /* IGA1 doesn't have LCD scaling, so set it center. */
2359 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2360 viaparinfo->lvds_setting_info->display_method =
2361 LCD_CENTERING;
2362 }
2363 viaparinfo->lvds_setting_info->bpp = video_bpp;
2364 viafb_lcd_set_mode(crt_timing, viaparinfo->
2365 lvds_setting_info,
2366 &viaparinfo->chip_info->lvds_chip_info);
2367 }
2368 }
2369 if (viafb_LCD2_ON) {
2370 if (viafb_SAMM_ON &&
2371 (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2372 viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2373 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2374 lvds_setting_info2,
2375 &viaparinfo->chip_info->lvds_chip_info2);
2376 } else {
2377 /* IGA1 doesn't have LCD scaling, so set it center. */
2378 if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2379 viaparinfo->lvds_setting_info2->display_method =
2380 LCD_CENTERING;
2381 }
2382 viaparinfo->lvds_setting_info2->bpp = video_bpp;
2383 viafb_lcd_set_mode(crt_timing, viaparinfo->
2384 lvds_setting_info2,
2385 &viaparinfo->chip_info->lvds_chip_info2);
2386 }
2387 }
2388
2389 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2390 && (viafb_LCD_ON || viafb_DVI_ON))
2391 set_display_channel();
2392
2393 /* If set mode normally, save resolution information for hot-plug . */
2394 if (!viafb_hotplug) {
Florian Tobias Schandinatdd73d6862010-03-10 15:21:28 -0800[diff] [blame]2395 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2396 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2397 viafb_hotplug_bpp = video_bpp;
2398 viafb_hotplug_refresh = viafb_refresh;
2399
2400 if (viafb_DVI_ON)
2401 viafb_DeviceStatus = DVI_Device;
2402 else
2403 viafb_DeviceStatus = CRT_Device;
2404 }
2405 device_on();
2406
2407 if (viafb_SAMM_ON == 1)
2408 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2409
2410 device_screen_on();
2411 return 1;
2412}
2413
2414int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2415{
2416 int i;
2417
2418 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2419 if ((hres == res_map_refresh_tbl[i].hres)
2420 && (vres == res_map_refresh_tbl[i].vres)
2421 && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2422 return res_map_refresh_tbl[i].pixclock;
2423 }
2424 return RES_640X480_60HZ_PIXCLOCK;
2425
2426}
2427
2428int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2429{
2430#define REFRESH_TOLERANCE 3
2431 int i, nearest = -1, diff = REFRESH_TOLERANCE;
2432 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2433 if ((hres == res_map_refresh_tbl[i].hres)
2434 && (vres == res_map_refresh_tbl[i].vres)
2435 && (diff > (abs(long_refresh -
2436 res_map_refresh_tbl[i].vmode_refresh)))) {
2437 diff = abs(long_refresh - res_map_refresh_tbl[i].
2438 vmode_refresh);
2439 nearest = i;
2440 }
2441 }
2442#undef REFRESH_TOLERANCE
2443 if (nearest > 0)
2444 return res_map_refresh_tbl[nearest].vmode_refresh;
2445 return 60;
2446}
2447
2448static void device_off(void)
2449{
2450 viafb_crt_disable();
2451 viafb_dvi_disable();
2452 viafb_lcd_disable();
2453}
2454
2455static void device_on(void)
2456{
2457 if (viafb_CRT_ON == 1)
2458 viafb_crt_enable();
2459 if (viafb_DVI_ON == 1)
2460 viafb_dvi_enable();
2461 if (viafb_LCD_ON == 1)
2462 viafb_lcd_enable();
2463}
2464
2465void viafb_crt_disable(void)
2466{
2467 viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2468}
2469
2470void viafb_crt_enable(void)
2471{
2472 viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2473}
2474
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2475static void enable_second_display_channel(void)
2476{
2477 /* to enable second display channel. */
2478 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2479 viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2480 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2481}
2482
2483static void disable_second_display_channel(void)
2484{
2485 /* to disable second display channel. */
2486 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2487 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2488 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2489}
2490
Harald Welteb72a5072009-05-19 15:50:58 +0800[diff] [blame]2491static u_int16_t via_function3[] = {
2492 CLE266_FUNCTION3, KM400_FUNCTION3, CN400_FUNCTION3, CN700_FUNCTION3,
2493 CX700_FUNCTION3, KM800_FUNCTION3, KM890_FUNCTION3, P4M890_FUNCTION3,
2494 P4M900_FUNCTION3, VX800_FUNCTION3, VX855_FUNCTION3,
2495};
2496
2497/* Get the BIOS-configured framebuffer size from PCI configuration space
2498 * of function 3 in the respective chipset */
Harald Welte2d280f72009-09-22 16:47:37 -0700[diff] [blame]2499int viafb_get_fb_size_from_pci(void)
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2500{
Harald Welteb72a5072009-05-19 15:50:58 +0800[diff] [blame]2501 int i;
2502 u_int8_t offset = 0;
2503 u_int32_t FBSize;
2504 u_int32_t VideoMemSize;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2505
Harald Welteb72a5072009-05-19 15:50:58 +0800[diff] [blame]2506 /* search for the "FUNCTION3" device in this chipset */
2507 for (i = 0; i < ARRAY_SIZE(via_function3); i++) {
2508 struct pci_dev *pdev;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2509
Harald Welteb72a5072009-05-19 15:50:58 +0800[diff] [blame]2510 pdev = pci_get_device(PCI_VENDOR_ID_VIA, via_function3[i],
2511 NULL);
2512 if (!pdev)
2513 continue;
2514
2515 DEBUG_MSG(KERN_INFO "Device ID = %x\n", pdev->device);
2516
2517 switch (pdev->device) {
2518 case CLE266_FUNCTION3:
2519 case KM400_FUNCTION3:
2520 offset = 0xE0;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2521 break;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2522 case CN400_FUNCTION3:
2523 case CN700_FUNCTION3:
2524 case CX700_FUNCTION3:
2525 case KM800_FUNCTION3:
2526 case KM890_FUNCTION3:
2527 case P4M890_FUNCTION3:
2528 case P4M900_FUNCTION3:
2529 case VX800_FUNCTION3:
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]2530 case VX855_FUNCTION3:
Harald Welteb72a5072009-05-19 15:50:58 +0800[diff] [blame]2531 /*case CN750_FUNCTION3: */
2532 offset = 0xA0;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2533 break;
2534 }
2535
Harald Welteb72a5072009-05-19 15:50:58 +0800[diff] [blame]2536 if (!offset)
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2537 break;
Harald Welteb72a5072009-05-19 15:50:58 +0800[diff] [blame]2538
2539 pci_read_config_dword(pdev, offset, &FBSize);
2540 pci_dev_put(pdev);
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2541 }
2542
Harald Welteb72a5072009-05-19 15:50:58 +0800[diff] [blame]2543 if (!offset) {
2544 printk(KERN_ERR "cannot determine framebuffer size\n");
2545 return -EIO;
2546 }
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2547
2548 FBSize = FBSize & 0x00007000;
2549 DEBUG_MSG(KERN_INFO "FB Size = %x\n", FBSize);
2550
2551 if (viaparinfo->chip_info->gfx_chip_name < UNICHROME_CX700) {
2552 switch (FBSize) {
2553 case 0x00004000:
2554 VideoMemSize = (16 << 20); /*16M */
2555 break;
2556
2557 case 0x00005000:
2558 VideoMemSize = (32 << 20); /*32M */
2559 break;
2560
2561 case 0x00006000:
2562 VideoMemSize = (64 << 20); /*64M */
2563 break;
2564
2565 default:
2566 VideoMemSize = (32 << 20); /*32M */
2567 break;
2568 }
2569 } else {
2570 switch (FBSize) {
2571 case 0x00001000:
2572 VideoMemSize = (8 << 20); /*8M */
2573 break;
2574
2575 case 0x00002000:
2576 VideoMemSize = (16 << 20); /*16M */
2577 break;
2578
2579 case 0x00003000:
2580 VideoMemSize = (32 << 20); /*32M */
2581 break;
2582
2583 case 0x00004000:
2584 VideoMemSize = (64 << 20); /*64M */
2585 break;
2586
2587 case 0x00005000:
2588 VideoMemSize = (128 << 20); /*128M */
2589 break;
2590
2591 case 0x00006000:
2592 VideoMemSize = (256 << 20); /*256M */
2593 break;
2594
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]2595 case 0x00007000: /* Only on VX855/875 */
2596 VideoMemSize = (512 << 20); /*512M */
2597 break;
2598
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2599 default:
2600 VideoMemSize = (32 << 20); /*32M */
2601 break;
2602 }
2603 }
2604
2605 return VideoMemSize;
2606}
2607
2608void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2609 *p_gfx_dpa_setting)
2610{
2611 switch (output_interface) {
2612 case INTERFACE_DVP0:
2613 {
2614 /* DVP0 Clock Polarity and Adjust: */
2615 viafb_write_reg_mask(CR96, VIACR,
2616 p_gfx_dpa_setting->DVP0, 0x0F);
2617
2618 /* DVP0 Clock and Data Pads Driving: */
2619 viafb_write_reg_mask(SR1E, VIASR,
2620 p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2621 viafb_write_reg_mask(SR2A, VIASR,
2622 p_gfx_dpa_setting->DVP0ClockDri_S1,
2623 BIT4);
2624 viafb_write_reg_mask(SR1B, VIASR,
2625 p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2626 viafb_write_reg_mask(SR2A, VIASR,
2627 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2628 break;
2629 }
2630
2631 case INTERFACE_DVP1:
2632 {
2633 /* DVP1 Clock Polarity and Adjust: */
2634 viafb_write_reg_mask(CR9B, VIACR,
2635 p_gfx_dpa_setting->DVP1, 0x0F);
2636
2637 /* DVP1 Clock and Data Pads Driving: */
2638 viafb_write_reg_mask(SR65, VIASR,
2639 p_gfx_dpa_setting->DVP1Driving, 0x0F);
2640 break;
2641 }
2642
2643 case INTERFACE_DFP_HIGH:
2644 {
2645 viafb_write_reg_mask(CR97, VIACR,
2646 p_gfx_dpa_setting->DFPHigh, 0x0F);
2647 break;
2648 }
2649
2650 case INTERFACE_DFP_LOW:
2651 {
2652 viafb_write_reg_mask(CR99, VIACR,
2653 p_gfx_dpa_setting->DFPLow, 0x0F);
2654 break;
2655 }
2656
2657 case INTERFACE_DFP:
2658 {
2659 viafb_write_reg_mask(CR97, VIACR,
2660 p_gfx_dpa_setting->DFPHigh, 0x0F);
2661 viafb_write_reg_mask(CR99, VIACR,
2662 p_gfx_dpa_setting->DFPLow, 0x0F);
2663 break;
2664 }
2665 }
2666}
2667
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2668/*According var's xres, yres fill var's other timing information*/
2669void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
Florian Tobias Schandinatdd73d6862010-03-10 15:21:28 -0800[diff] [blame]2670 struct VideoModeTable *vmode_tbl)
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2671{
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2672 struct crt_mode_table *crt_timing = NULL;
2673 struct display_timing crt_reg;
2674 int i = 0, index = 0;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2675 crt_timing = vmode_tbl->crtc;
2676 for (i = 0; i < vmode_tbl->mode_array; i++) {
2677 index = i;
2678 if (crt_timing[i].refresh_rate == refresh)
2679 break;
2680 }
2681
2682 crt_reg = crt_timing[index].crtc;
Joseph Chand61e0bf2008-10-15 22:03:23 -0700[diff] [blame]2683 var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2684 var->left_margin =
2685 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2686 var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2687 var->hsync_len = crt_reg.hor_sync_end;
2688 var->upper_margin =
2689 crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2690 var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2691 var->vsync_len = crt_reg.ver_sync_end;
2692}