Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1 | /* |
| 2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor |
| 3 | * |
| 4 | * Multi-channel Audio Serial Port Driver |
| 5 | * |
| 6 | * Author: Nirmal Pandey <n-pandey@ti.com>, |
| 7 | * Suresh Rajashekara <suresh.r@ti.com> |
| 8 | * Steve Chen <schen@.mvista.com> |
| 9 | * |
| 10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> |
| 11 | * Copyright: (C) 2009 Texas Instruments, India |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License version 2 as |
| 15 | * published by the Free Software Foundation. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/device.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 21 | #include <linux/slab.h> |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 22 | #include <linux/delay.h> |
| 23 | #include <linux/io.h> |
Peter Ujfalusi | ae726e9 | 2013-11-14 11:35:35 +0200 | [diff] [blame] | 24 | #include <linux/clk.h> |
Hebbar, Gururaja | 1088434 | 2012-08-08 20:40:32 +0530 | [diff] [blame] | 25 | #include <linux/pm_runtime.h> |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 26 | #include <linux/of.h> |
| 27 | #include <linux/of_platform.h> |
| 28 | #include <linux/of_device.h> |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 29 | |
| 30 | #include <sound/core.h> |
| 31 | #include <sound/pcm.h> |
| 32 | #include <sound/pcm_params.h> |
| 33 | #include <sound/initval.h> |
| 34 | #include <sound/soc.h> |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 35 | #include <sound/dmaengine_pcm.h> |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 36 | |
| 37 | #include "davinci-pcm.h" |
| 38 | #include "davinci-mcasp.h" |
| 39 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 40 | struct davinci_mcasp { |
Peter Ujfalusi | 21400a7 | 2013-11-14 11:35:26 +0200 | [diff] [blame] | 41 | struct davinci_pcm_dma_params dma_params[2]; |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 42 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
Peter Ujfalusi | 21400a7 | 2013-11-14 11:35:26 +0200 | [diff] [blame] | 43 | void __iomem *base; |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 44 | u32 fifo_base; |
Peter Ujfalusi | 21400a7 | 2013-11-14 11:35:26 +0200 | [diff] [blame] | 45 | struct device *dev; |
| 46 | |
| 47 | /* McASP specific data */ |
| 48 | int tdm_slots; |
| 49 | u8 op_mode; |
| 50 | u8 num_serializer; |
| 51 | u8 *serial_dir; |
| 52 | u8 version; |
| 53 | u16 bclk_lrclk_ratio; |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 54 | int streams; |
Peter Ujfalusi | 21400a7 | 2013-11-14 11:35:26 +0200 | [diff] [blame] | 55 | |
Jyri Sarha | ab8b14b | 2014-01-27 17:37:52 +0200 | [diff] [blame] | 56 | int sysclk_freq; |
| 57 | bool bclk_master; |
| 58 | |
Peter Ujfalusi | 21400a7 | 2013-11-14 11:35:26 +0200 | [diff] [blame] | 59 | /* McASP FIFO related */ |
| 60 | u8 txnumevt; |
| 61 | u8 rxnumevt; |
| 62 | |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 63 | bool dat_port; |
| 64 | |
Peter Ujfalusi | 21400a7 | 2013-11-14 11:35:26 +0200 | [diff] [blame] | 65 | #ifdef CONFIG_PM_SLEEP |
| 66 | struct { |
| 67 | u32 txfmtctl; |
| 68 | u32 rxfmtctl; |
| 69 | u32 txfmt; |
| 70 | u32 rxfmt; |
| 71 | u32 aclkxctl; |
| 72 | u32 aclkrctl; |
| 73 | u32 pdir; |
| 74 | } context; |
| 75 | #endif |
| 76 | }; |
| 77 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 78 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
| 79 | u32 val) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 80 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 81 | void __iomem *reg = mcasp->base + offset; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 82 | __raw_writel(__raw_readl(reg) | val, reg); |
| 83 | } |
| 84 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 85 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
| 86 | u32 val) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 87 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 88 | void __iomem *reg = mcasp->base + offset; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 89 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
| 90 | } |
| 91 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 92 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
| 93 | u32 val, u32 mask) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 94 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 95 | void __iomem *reg = mcasp->base + offset; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 96 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
| 97 | } |
| 98 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 99 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
| 100 | u32 val) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 101 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 102 | __raw_writel(val, mcasp->base + offset); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 103 | } |
| 104 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 105 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 106 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 107 | return (u32)__raw_readl(mcasp->base + offset); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 108 | } |
| 109 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 110 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 111 | { |
| 112 | int i = 0; |
| 113 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 114 | mcasp_set_bits(mcasp, ctl_reg, val); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 115 | |
| 116 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ |
| 117 | /* loop count is to avoid the lock-up */ |
| 118 | for (i = 0; i < 1000; i++) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 119 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 120 | break; |
| 121 | } |
| 122 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 123 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 124 | printk(KERN_ERR "GBLCTL write error\n"); |
| 125 | } |
| 126 | |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 127 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
| 128 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 129 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
| 130 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 131 | |
| 132 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; |
| 133 | } |
| 134 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 135 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 136 | { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 137 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
| 138 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 139 | |
| 140 | /* |
| 141 | * When ASYNC == 0 the transmit and receive sections operate |
| 142 | * synchronously from the transmit clock and frame sync. We need to make |
| 143 | * sure that the TX signlas are enabled when starting reception. |
| 144 | */ |
| 145 | if (mcasp_is_synchronous(mcasp)) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 146 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
| 147 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 148 | } |
| 149 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 150 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
| 151 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 152 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 153 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
| 154 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); |
| 155 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 156 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 157 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
| 158 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 159 | |
| 160 | if (mcasp_is_synchronous(mcasp)) |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 161 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 162 | } |
| 163 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 164 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 165 | { |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 166 | u8 offset = 0, i; |
| 167 | u32 cnt; |
| 168 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 169 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
| 170 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); |
| 171 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); |
| 172 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 173 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 174 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); |
| 175 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
| 176 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 177 | for (i = 0; i < mcasp->num_serializer; i++) { |
| 178 | if (mcasp->serial_dir[i] == TX_MODE) { |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 179 | offset = i; |
| 180 | break; |
| 181 | } |
| 182 | } |
| 183 | |
| 184 | /* wait for TX ready */ |
| 185 | cnt = 0; |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 186 | while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) & |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 187 | TXSTATE) && (cnt < 100000)) |
| 188 | cnt++; |
| 189 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 190 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 191 | } |
| 192 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 193 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 194 | { |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 195 | u32 reg; |
| 196 | |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 197 | mcasp->streams++; |
| 198 | |
Chaithrika U S | 539d3d8 | 2009-09-23 10:12:08 -0400 | [diff] [blame] | 199 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 200 | if (mcasp->txnumevt) { /* enable FIFO */ |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 201 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 202 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
| 203 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); |
Vaibhav Bedia | 0d62427 | 2012-08-08 20:40:31 +0530 | [diff] [blame] | 204 | } |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 205 | mcasp_start_tx(mcasp); |
Chaithrika U S | 539d3d8 | 2009-09-23 10:12:08 -0400 | [diff] [blame] | 206 | } else { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 207 | if (mcasp->rxnumevt) { /* enable FIFO */ |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 208 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 209 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
| 210 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); |
Vaibhav Bedia | 0d62427 | 2012-08-08 20:40:31 +0530 | [diff] [blame] | 211 | } |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 212 | mcasp_start_rx(mcasp); |
Chaithrika U S | 539d3d8 | 2009-09-23 10:12:08 -0400 | [diff] [blame] | 213 | } |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 214 | } |
| 215 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 216 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 217 | { |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 218 | /* |
| 219 | * In synchronous mode stop the TX clocks if no other stream is |
| 220 | * running |
| 221 | */ |
| 222 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 223 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 224 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 225 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
| 226 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 227 | } |
| 228 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 229 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 230 | { |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 231 | u32 val = 0; |
| 232 | |
| 233 | /* |
| 234 | * In synchronous mode keep TX clocks running if the capture stream is |
| 235 | * still running. |
| 236 | */ |
| 237 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) |
| 238 | val = TXHCLKRST | TXCLKRST | TXFSRST; |
| 239 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 240 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
| 241 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 242 | } |
| 243 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 244 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 245 | { |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 246 | u32 reg; |
| 247 | |
Peter Ujfalusi | 4dcb5a0 | 2013-11-14 11:35:33 +0200 | [diff] [blame] | 248 | mcasp->streams--; |
| 249 | |
Chaithrika U S | 539d3d8 | 2009-09-23 10:12:08 -0400 | [diff] [blame] | 250 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 251 | if (mcasp->txnumevt) { /* disable FIFO */ |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 252 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 253 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
Hebbar, Gururaja | e5ec69d | 2012-09-03 13:40:40 +0530 | [diff] [blame] | 254 | } |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 255 | mcasp_stop_tx(mcasp); |
Chaithrika U S | 539d3d8 | 2009-09-23 10:12:08 -0400 | [diff] [blame] | 256 | } else { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 257 | if (mcasp->rxnumevt) { /* disable FIFO */ |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 258 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 259 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); |
Hebbar, Gururaja | e5ec69d | 2012-09-03 13:40:40 +0530 | [diff] [blame] | 260 | } |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 261 | mcasp_stop_rx(mcasp); |
Chaithrika U S | 539d3d8 | 2009-09-23 10:12:08 -0400 | [diff] [blame] | 262 | } |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 263 | } |
| 264 | |
| 265 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
| 266 | unsigned int fmt) |
| 267 | { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 268 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
Peter Ujfalusi | 1d17a04 | 2014-01-30 15:21:30 +0200 | [diff] [blame] | 269 | int ret = 0; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 270 | |
Peter Ujfalusi | 1d17a04 | 2014-01-30 15:21:30 +0200 | [diff] [blame] | 271 | pm_runtime_get_sync(mcasp->dev); |
Daniel Mack | 5296cf2 | 2012-10-04 15:08:42 +0200 | [diff] [blame] | 272 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 273 | case SND_SOC_DAIFMT_DSP_B: |
| 274 | case SND_SOC_DAIFMT_AC97: |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 275 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
| 276 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); |
Daniel Mack | 5296cf2 | 2012-10-04 15:08:42 +0200 | [diff] [blame] | 277 | break; |
| 278 | default: |
| 279 | /* configure a full-word SYNC pulse (LRCLK) */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 280 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
| 281 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); |
Daniel Mack | 5296cf2 | 2012-10-04 15:08:42 +0200 | [diff] [blame] | 282 | |
| 283 | /* make 1st data bit occur one ACLK cycle after the frame sync */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 284 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1)); |
| 285 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1)); |
Daniel Mack | 5296cf2 | 2012-10-04 15:08:42 +0200 | [diff] [blame] | 286 | break; |
| 287 | } |
| 288 | |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 289 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 290 | case SND_SOC_DAIFMT_CBS_CFS: |
| 291 | /* codec is clock and frame slave */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 292 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
| 293 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 294 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 295 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
| 296 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 297 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 298 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
| 299 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); |
Jyri Sarha | ab8b14b | 2014-01-27 17:37:52 +0200 | [diff] [blame] | 300 | mcasp->bclk_master = 1; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 301 | break; |
Chaithrika U S | 517ee6c | 2009-08-11 16:59:12 -0400 | [diff] [blame] | 302 | case SND_SOC_DAIFMT_CBM_CFS: |
| 303 | /* codec is clock master and frame slave */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 304 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
| 305 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); |
Chaithrika U S | 517ee6c | 2009-08-11 16:59:12 -0400 | [diff] [blame] | 306 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 307 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
| 308 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); |
Chaithrika U S | 517ee6c | 2009-08-11 16:59:12 -0400 | [diff] [blame] | 309 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 310 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
| 311 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); |
Jyri Sarha | ab8b14b | 2014-01-27 17:37:52 +0200 | [diff] [blame] | 312 | mcasp->bclk_master = 0; |
Chaithrika U S | 517ee6c | 2009-08-11 16:59:12 -0400 | [diff] [blame] | 313 | break; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 314 | case SND_SOC_DAIFMT_CBM_CFM: |
| 315 | /* codec is clock and frame master */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 316 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
| 317 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 318 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 319 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
| 320 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 321 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 322 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
| 323 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); |
Jyri Sarha | ab8b14b | 2014-01-27 17:37:52 +0200 | [diff] [blame] | 324 | mcasp->bclk_master = 0; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 325 | break; |
| 326 | |
| 327 | default: |
Peter Ujfalusi | 1d17a04 | 2014-01-30 15:21:30 +0200 | [diff] [blame] | 328 | ret = -EINVAL; |
| 329 | goto out; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 330 | } |
| 331 | |
| 332 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 333 | case SND_SOC_DAIFMT_IB_NF: |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 334 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
| 335 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 336 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 337 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
| 338 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 339 | break; |
| 340 | |
| 341 | case SND_SOC_DAIFMT_NB_IF: |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 342 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
| 343 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 344 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 345 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
| 346 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 347 | break; |
| 348 | |
| 349 | case SND_SOC_DAIFMT_IB_IF: |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 350 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
| 351 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 352 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 353 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
| 354 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 355 | break; |
| 356 | |
| 357 | case SND_SOC_DAIFMT_NB_NF: |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 358 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
| 359 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 360 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 361 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
| 362 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 363 | break; |
| 364 | |
| 365 | default: |
Peter Ujfalusi | 1d17a04 | 2014-01-30 15:21:30 +0200 | [diff] [blame] | 366 | ret = -EINVAL; |
| 367 | break; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 368 | } |
Peter Ujfalusi | 1d17a04 | 2014-01-30 15:21:30 +0200 | [diff] [blame] | 369 | out: |
| 370 | pm_runtime_put_sync(mcasp->dev); |
| 371 | return ret; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 372 | } |
| 373 | |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 374 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) |
| 375 | { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 376 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 377 | |
| 378 | switch (div_id) { |
| 379 | case 0: /* MCLK divider */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 380 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 381 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 382 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 383 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
| 384 | break; |
| 385 | |
| 386 | case 1: /* BCLK divider */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 387 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 388 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 389 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 390 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
| 391 | break; |
| 392 | |
Daniel Mack | 1b3bc06 | 2012-12-05 18:20:38 +0100 | [diff] [blame] | 393 | case 2: /* BCLK/LRCLK ratio */ |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 394 | mcasp->bclk_lrclk_ratio = div; |
Daniel Mack | 1b3bc06 | 2012-12-05 18:20:38 +0100 | [diff] [blame] | 395 | break; |
| 396 | |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 397 | default: |
| 398 | return -EINVAL; |
| 399 | } |
| 400 | |
| 401 | return 0; |
| 402 | } |
| 403 | |
Daniel Mack | 5b66aa2 | 2012-10-04 15:08:41 +0200 | [diff] [blame] | 404 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
| 405 | unsigned int freq, int dir) |
| 406 | { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 407 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
Daniel Mack | 5b66aa2 | 2012-10-04 15:08:41 +0200 | [diff] [blame] | 408 | |
| 409 | if (dir == SND_SOC_CLOCK_OUT) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 410 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
| 411 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); |
| 412 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); |
Daniel Mack | 5b66aa2 | 2012-10-04 15:08:41 +0200 | [diff] [blame] | 413 | } else { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 414 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
| 415 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); |
| 416 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); |
Daniel Mack | 5b66aa2 | 2012-10-04 15:08:41 +0200 | [diff] [blame] | 417 | } |
| 418 | |
Jyri Sarha | ab8b14b | 2014-01-27 17:37:52 +0200 | [diff] [blame] | 419 | mcasp->sysclk_freq = freq; |
| 420 | |
Daniel Mack | 5b66aa2 | 2012-10-04 15:08:41 +0200 | [diff] [blame] | 421 | return 0; |
| 422 | } |
| 423 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 424 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 425 | int word_length) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 426 | { |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 427 | u32 fmt; |
Daniel Mack | 7967189 | 2013-05-16 15:25:01 +0200 | [diff] [blame] | 428 | u32 tx_rotate = (word_length / 4) & 0x7; |
| 429 | u32 rx_rotate = (32 - word_length) / 4; |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 430 | u32 mask = (1ULL << word_length) - 1; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 431 | |
Daniel Mack | 1b3bc06 | 2012-12-05 18:20:38 +0100 | [diff] [blame] | 432 | /* |
| 433 | * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv() |
| 434 | * callback, take it into account here. That allows us to for example |
| 435 | * send 32 bits per channel to the codec, while only 16 of them carry |
| 436 | * audio payload. |
Michal Bachraty | d486fea | 2013-04-19 15:28:44 +0200 | [diff] [blame] | 437 | * The clock ratio is given for a full period of data (for I2S format |
| 438 | * both left and right channels), so it has to be divided by number of |
| 439 | * tdm-slots (for I2S - divided by 2). |
Daniel Mack | 1b3bc06 | 2012-12-05 18:20:38 +0100 | [diff] [blame] | 440 | */ |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 441 | if (mcasp->bclk_lrclk_ratio) |
| 442 | word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots; |
Daniel Mack | 1b3bc06 | 2012-12-05 18:20:38 +0100 | [diff] [blame] | 443 | |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 444 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
| 445 | fmt = (word_length >> 1) - 1; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 446 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 447 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 448 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
| 449 | RXSSZ(0x0F)); |
| 450 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), |
| 451 | TXSSZ(0x0F)); |
| 452 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), |
| 453 | TXROT(7)); |
| 454 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), |
| 455 | RXROT(7)); |
| 456 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); |
Yegor Yefremov | f5023af | 2013-04-04 16:13:20 +0200 | [diff] [blame] | 457 | } |
| 458 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 459 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
Chaithrika U S | 0c31cf3 | 2009-09-15 18:13:29 -0400 | [diff] [blame] | 460 | |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 461 | return 0; |
| 462 | } |
| 463 | |
Peter Ujfalusi | 662ffae | 2014-01-30 15:15:22 +0200 | [diff] [blame] | 464 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 465 | int channels) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 466 | { |
| 467 | int i; |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 468 | u8 tx_ser = 0; |
| 469 | u8 rx_ser = 0; |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 470 | u8 ser; |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 471 | u8 slots = mcasp->tdm_slots; |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 472 | u8 max_active_serializers = (channels + slots - 1) / slots; |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 473 | u32 reg; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 474 | /* Default configuration */ |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 475 | if (mcasp->version != MCASP_VERSION_4) |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 476 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 477 | |
| 478 | /* All PINS as McASP */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 479 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 480 | |
| 481 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 482 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
| 483 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 484 | } else { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 485 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
| 486 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 487 | } |
| 488 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 489 | for (i = 0; i < mcasp->num_serializer; i++) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 490 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
| 491 | mcasp->serial_dir[i]); |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 492 | if (mcasp->serial_dir[i] == TX_MODE && |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 493 | tx_ser < max_active_serializers) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 494 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 495 | tx_ser++; |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 496 | } else if (mcasp->serial_dir[i] == RX_MODE && |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 497 | rx_ser < max_active_serializers) { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 498 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 499 | rx_ser++; |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 500 | } else { |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 501 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
| 502 | SRMOD_INACTIVE, SRMOD_MASK); |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 503 | } |
| 504 | } |
| 505 | |
Daniel Mack | ecf327c | 2013-03-08 14:19:38 +0100 | [diff] [blame] | 506 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 507 | ser = tx_ser; |
| 508 | else |
| 509 | ser = rx_ser; |
| 510 | |
| 511 | if (ser < max_active_serializers) { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 512 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
Daniel Mack | ecf327c | 2013-03-08 14:19:38 +0100 | [diff] [blame] | 513 | "enabled in mcasp (%d)\n", channels, ser * slots); |
| 514 | return -EINVAL; |
| 515 | } |
| 516 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 517 | if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 518 | if (mcasp->txnumevt * tx_ser > 64) |
| 519 | mcasp->txnumevt = 1; |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 520 | |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 521 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 522 | mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK); |
| 523 | mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8), |
| 524 | NUMEVT_MASK); |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 525 | } |
| 526 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 527 | if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) { |
| 528 | if (mcasp->rxnumevt * rx_ser > 64) |
| 529 | mcasp->rxnumevt = 1; |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 530 | |
| 531 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 532 | mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK); |
| 533 | mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8), |
| 534 | NUMEVT_MASK); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 535 | } |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 536 | |
| 537 | return 0; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 538 | } |
| 539 | |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 540 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 541 | { |
| 542 | int i, active_slots; |
| 543 | u32 mask = 0; |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 544 | u32 busel = 0; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 545 | |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 546 | if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) { |
| 547 | dev_err(mcasp->dev, "tdm slot %d not supported\n", |
| 548 | mcasp->tdm_slots); |
| 549 | return -EINVAL; |
| 550 | } |
| 551 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 552 | active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 553 | for (i = 0; i < active_slots; i++) |
| 554 | mask |= (1 << i); |
| 555 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 556 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 557 | |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 558 | if (!mcasp->dat_port) |
| 559 | busel = TXSEL; |
| 560 | |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 561 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); |
| 562 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); |
| 563 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, |
| 564 | FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF)); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 565 | |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 566 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); |
| 567 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); |
| 568 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, |
| 569 | FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF)); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 570 | |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 571 | return 0; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 572 | } |
| 573 | |
| 574 | /* S/PDIF */ |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 575 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 576 | { |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 577 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
| 578 | and LSB first */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 579 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 580 | |
| 581 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 582 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 583 | |
| 584 | /* Set the TX tdm : for all the slots */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 585 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 586 | |
| 587 | /* Set the TX clock controls : div = 1 and internal */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 588 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 589 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 590 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 591 | |
| 592 | /* Only 44100 and 48000 are valid, both have the same setting */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 593 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 594 | |
| 595 | /* Enable the DIT */ |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 596 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 597 | |
| 598 | return 0; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 599 | } |
| 600 | |
| 601 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, |
| 602 | struct snd_pcm_hw_params *params, |
| 603 | struct snd_soc_dai *cpu_dai) |
| 604 | { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 605 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 606 | struct davinci_pcm_dma_params *dma_params = |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 607 | &mcasp->dma_params[substream->stream]; |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 608 | struct snd_dmaengine_dai_dma_data *dma_data = |
| 609 | &mcasp->dma_data[substream->stream]; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 610 | int word_length; |
Chaithrika U S | 4fa9c1a | 2009-09-30 17:32:27 -0400 | [diff] [blame] | 611 | u8 fifo_level; |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 612 | u8 slots = mcasp->tdm_slots; |
Michal Bachraty | 7c21a78 | 2013-04-19 15:28:03 +0200 | [diff] [blame] | 613 | u8 active_serializers; |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 614 | int channels; |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 615 | int ret; |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 616 | struct snd_interval *pcm_channels = hw_param_interval(params, |
| 617 | SNDRV_PCM_HW_PARAM_CHANNELS); |
Jyri Sarha | ab8b14b | 2014-01-27 17:37:52 +0200 | [diff] [blame] | 618 | |
| 619 | /* If mcasp is BCLK master we need to set BCLK divider */ |
| 620 | if (mcasp->bclk_master) { |
| 621 | unsigned int bclk_freq = snd_soc_params_to_bclk(params); |
| 622 | if (mcasp->sysclk_freq % bclk_freq != 0) { |
| 623 | dev_err(mcasp->dev, "Can't produce requred BCLK\n"); |
| 624 | return -EINVAL; |
| 625 | } |
| 626 | davinci_mcasp_set_clkdiv( |
| 627 | cpu_dai, 1, mcasp->sysclk_freq / bclk_freq); |
| 628 | } |
| 629 | |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 630 | channels = pcm_channels->min; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 631 | |
Michal Bachraty | 7c21a78 | 2013-04-19 15:28:03 +0200 | [diff] [blame] | 632 | active_serializers = (channels + slots - 1) / slots; |
| 633 | |
Peter Ujfalusi | 0f7d9a6 | 2014-01-30 15:15:24 +0200 | [diff] [blame^] | 634 | ret = mcasp_common_hw_param(mcasp, substream->stream, channels); |
| 635 | if (ret) |
| 636 | return ret; |
| 637 | |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 638 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 639 | fifo_level = mcasp->txnumevt * active_serializers; |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 640 | else |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 641 | fifo_level = mcasp->rxnumevt * active_serializers; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 642 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 643 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 644 | ret = mcasp_dit_hw_param(mcasp); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 645 | else |
Peter Ujfalusi | 2c56c4c | 2014-01-30 15:15:23 +0200 | [diff] [blame] | 646 | ret = mcasp_i2s_hw_param(mcasp, substream->stream); |
| 647 | |
| 648 | if (ret) |
| 649 | return ret; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 650 | |
| 651 | switch (params_format(params)) { |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 652 | case SNDRV_PCM_FORMAT_U8: |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 653 | case SNDRV_PCM_FORMAT_S8: |
| 654 | dma_params->data_type = 1; |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 655 | word_length = 8; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 656 | break; |
| 657 | |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 658 | case SNDRV_PCM_FORMAT_U16_LE: |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 659 | case SNDRV_PCM_FORMAT_S16_LE: |
| 660 | dma_params->data_type = 2; |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 661 | word_length = 16; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 662 | break; |
| 663 | |
Daniel Mack | 21eb24d | 2012-10-09 09:35:16 +0200 | [diff] [blame] | 664 | case SNDRV_PCM_FORMAT_U24_3LE: |
| 665 | case SNDRV_PCM_FORMAT_S24_3LE: |
Daniel Mack | 21eb24d | 2012-10-09 09:35:16 +0200 | [diff] [blame] | 666 | dma_params->data_type = 3; |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 667 | word_length = 24; |
Daniel Mack | 21eb24d | 2012-10-09 09:35:16 +0200 | [diff] [blame] | 668 | break; |
| 669 | |
Daniel Mack | 6b7fa01 | 2012-10-09 11:56:40 +0200 | [diff] [blame] | 670 | case SNDRV_PCM_FORMAT_U24_LE: |
| 671 | case SNDRV_PCM_FORMAT_S24_LE: |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 672 | case SNDRV_PCM_FORMAT_U32_LE: |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 673 | case SNDRV_PCM_FORMAT_S32_LE: |
| 674 | dma_params->data_type = 4; |
Daniel Mack | ba764b3 | 2012-12-05 18:20:37 +0100 | [diff] [blame] | 675 | word_length = 32; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 676 | break; |
| 677 | |
| 678 | default: |
| 679 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); |
| 680 | return -EINVAL; |
| 681 | } |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 682 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 683 | if (mcasp->version == MCASP_VERSION_2 && !fifo_level) |
Chaithrika U S | 4fa9c1a | 2009-09-30 17:32:27 -0400 | [diff] [blame] | 684 | dma_params->acnt = 4; |
| 685 | else |
Chaithrika U S | 6a99fb5 | 2009-08-11 16:58:52 -0400 | [diff] [blame] | 686 | dma_params->acnt = dma_params->data_type; |
| 687 | |
Chaithrika U S | 4fa9c1a | 2009-09-30 17:32:27 -0400 | [diff] [blame] | 688 | dma_params->fifo_level = fifo_level; |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 689 | dma_data->maxburst = fifo_level; |
| 690 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 691 | davinci_config_channel_size(mcasp, word_length); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 692 | |
| 693 | return 0; |
| 694 | } |
| 695 | |
| 696 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, |
| 697 | int cmd, struct snd_soc_dai *cpu_dai) |
| 698 | { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 699 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 700 | int ret = 0; |
| 701 | |
| 702 | switch (cmd) { |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 703 | case SNDRV_PCM_TRIGGER_RESUME: |
Chaithrika U S | e473b84 | 2010-01-20 17:06:33 +0530 | [diff] [blame] | 704 | case SNDRV_PCM_TRIGGER_START: |
| 705 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 706 | davinci_mcasp_start(mcasp, substream->stream); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 707 | break; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 708 | case SNDRV_PCM_TRIGGER_SUSPEND: |
Chaithrika U S | a47979b | 2009-12-03 18:56:56 +0530 | [diff] [blame] | 709 | case SNDRV_PCM_TRIGGER_STOP: |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 710 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 711 | davinci_mcasp_stop(mcasp, substream->stream); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 712 | break; |
| 713 | |
| 714 | default: |
| 715 | ret = -EINVAL; |
| 716 | } |
| 717 | |
| 718 | return ret; |
| 719 | } |
| 720 | |
Chris Paulson-Ellis | bedad0c | 2010-11-16 12:27:09 +0000 | [diff] [blame] | 721 | static int davinci_mcasp_startup(struct snd_pcm_substream *substream, |
| 722 | struct snd_soc_dai *dai) |
| 723 | { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 724 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
Chris Paulson-Ellis | bedad0c | 2010-11-16 12:27:09 +0000 | [diff] [blame] | 725 | |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 726 | if (mcasp->version == MCASP_VERSION_4) |
| 727 | snd_soc_dai_set_dma_data(dai, substream, |
| 728 | &mcasp->dma_data[substream->stream]); |
| 729 | else |
| 730 | snd_soc_dai_set_dma_data(dai, substream, mcasp->dma_params); |
| 731 | |
Chris Paulson-Ellis | bedad0c | 2010-11-16 12:27:09 +0000 | [diff] [blame] | 732 | return 0; |
| 733 | } |
| 734 | |
Lars-Peter Clausen | 85e7652 | 2011-11-23 11:40:40 +0100 | [diff] [blame] | 735 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
Chris Paulson-Ellis | bedad0c | 2010-11-16 12:27:09 +0000 | [diff] [blame] | 736 | .startup = davinci_mcasp_startup, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 737 | .trigger = davinci_mcasp_trigger, |
| 738 | .hw_params = davinci_mcasp_hw_params, |
| 739 | .set_fmt = davinci_mcasp_set_dai_fmt, |
Daniel Mack | 4ed8c9b | 2012-10-04 15:08:39 +0200 | [diff] [blame] | 740 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
Daniel Mack | 5b66aa2 | 2012-10-04 15:08:41 +0200 | [diff] [blame] | 741 | .set_sysclk = davinci_mcasp_set_sysclk, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 742 | }; |
| 743 | |
Peter Ujfalusi | ed29cd5 | 2013-11-14 11:35:22 +0200 | [diff] [blame] | 744 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
| 745 | |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 746 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
| 747 | SNDRV_PCM_FMTBIT_U8 | \ |
| 748 | SNDRV_PCM_FMTBIT_S16_LE | \ |
| 749 | SNDRV_PCM_FMTBIT_U16_LE | \ |
Daniel Mack | 21eb24d | 2012-10-09 09:35:16 +0200 | [diff] [blame] | 750 | SNDRV_PCM_FMTBIT_S24_LE | \ |
| 751 | SNDRV_PCM_FMTBIT_U24_LE | \ |
| 752 | SNDRV_PCM_FMTBIT_S24_3LE | \ |
| 753 | SNDRV_PCM_FMTBIT_U24_3LE | \ |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 754 | SNDRV_PCM_FMTBIT_S32_LE | \ |
| 755 | SNDRV_PCM_FMTBIT_U32_LE) |
| 756 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 757 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 758 | { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 759 | .name = "davinci-mcasp.0", |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 760 | .playback = { |
| 761 | .channels_min = 2, |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 762 | .channels_max = 32 * 16, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 763 | .rates = DAVINCI_MCASP_RATES, |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 764 | .formats = DAVINCI_MCASP_PCM_FMTS, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 765 | }, |
| 766 | .capture = { |
| 767 | .channels_min = 2, |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 768 | .channels_max = 32 * 16, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 769 | .rates = DAVINCI_MCASP_RATES, |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 770 | .formats = DAVINCI_MCASP_PCM_FMTS, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 771 | }, |
| 772 | .ops = &davinci_mcasp_dai_ops, |
| 773 | |
| 774 | }, |
| 775 | { |
Peter Ujfalusi | 58e48d9 | 2013-11-14 11:35:24 +0200 | [diff] [blame] | 776 | .name = "davinci-mcasp.1", |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 777 | .playback = { |
| 778 | .channels_min = 1, |
| 779 | .channels_max = 384, |
| 780 | .rates = DAVINCI_MCASP_RATES, |
Ben Gardiner | 0a9d138 | 2011-08-26 12:02:44 -0400 | [diff] [blame] | 781 | .formats = DAVINCI_MCASP_PCM_FMTS, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 782 | }, |
| 783 | .ops = &davinci_mcasp_dai_ops, |
| 784 | }, |
| 785 | |
| 786 | }; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 787 | |
Kuninori Morimoto | eeef0ed | 2013-03-21 03:31:19 -0700 | [diff] [blame] | 788 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
| 789 | .name = "davinci-mcasp", |
| 790 | }; |
| 791 | |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 792 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
| 793 | static struct snd_platform_data dm646x_mcasp_pdata = { |
| 794 | .tx_dma_offset = 0x400, |
| 795 | .rx_dma_offset = 0x400, |
| 796 | .asp_chan_q = EVENTQ_0, |
| 797 | .version = MCASP_VERSION_1, |
| 798 | }; |
| 799 | |
| 800 | static struct snd_platform_data da830_mcasp_pdata = { |
| 801 | .tx_dma_offset = 0x2000, |
| 802 | .rx_dma_offset = 0x2000, |
| 803 | .asp_chan_q = EVENTQ_0, |
| 804 | .version = MCASP_VERSION_2, |
| 805 | }; |
| 806 | |
Peter Ujfalusi | b14899d | 2013-11-14 11:35:37 +0200 | [diff] [blame] | 807 | static struct snd_platform_data am33xx_mcasp_pdata = { |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 808 | .tx_dma_offset = 0, |
| 809 | .rx_dma_offset = 0, |
| 810 | .asp_chan_q = EVENTQ_0, |
| 811 | .version = MCASP_VERSION_3, |
| 812 | }; |
| 813 | |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 814 | static struct snd_platform_data dra7_mcasp_pdata = { |
| 815 | .tx_dma_offset = 0x200, |
| 816 | .rx_dma_offset = 0x284, |
| 817 | .asp_chan_q = EVENTQ_0, |
| 818 | .version = MCASP_VERSION_4, |
| 819 | }; |
| 820 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 821 | static const struct of_device_id mcasp_dt_ids[] = { |
| 822 | { |
| 823 | .compatible = "ti,dm646x-mcasp-audio", |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 824 | .data = &dm646x_mcasp_pdata, |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 825 | }, |
| 826 | { |
| 827 | .compatible = "ti,da830-mcasp-audio", |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 828 | .data = &da830_mcasp_pdata, |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 829 | }, |
Hebbar, Gururaja | e5ec69d | 2012-09-03 13:40:40 +0530 | [diff] [blame] | 830 | { |
Jyri Sarha | 3af9e03 | 2013-10-18 18:37:44 +0300 | [diff] [blame] | 831 | .compatible = "ti,am33xx-mcasp-audio", |
Peter Ujfalusi | b14899d | 2013-11-14 11:35:37 +0200 | [diff] [blame] | 832 | .data = &am33xx_mcasp_pdata, |
Hebbar, Gururaja | e5ec69d | 2012-09-03 13:40:40 +0530 | [diff] [blame] | 833 | }, |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 834 | { |
| 835 | .compatible = "ti,dra7-mcasp-audio", |
| 836 | .data = &dra7_mcasp_pdata, |
| 837 | }, |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 838 | { /* sentinel */ } |
| 839 | }; |
| 840 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); |
| 841 | |
Peter Ujfalusi | ae726e9 | 2013-11-14 11:35:35 +0200 | [diff] [blame] | 842 | static int mcasp_reparent_fck(struct platform_device *pdev) |
| 843 | { |
| 844 | struct device_node *node = pdev->dev.of_node; |
| 845 | struct clk *gfclk, *parent_clk; |
| 846 | const char *parent_name; |
| 847 | int ret; |
| 848 | |
| 849 | if (!node) |
| 850 | return 0; |
| 851 | |
| 852 | parent_name = of_get_property(node, "fck_parent", NULL); |
| 853 | if (!parent_name) |
| 854 | return 0; |
| 855 | |
| 856 | gfclk = clk_get(&pdev->dev, "fck"); |
| 857 | if (IS_ERR(gfclk)) { |
| 858 | dev_err(&pdev->dev, "failed to get fck\n"); |
| 859 | return PTR_ERR(gfclk); |
| 860 | } |
| 861 | |
| 862 | parent_clk = clk_get(NULL, parent_name); |
| 863 | if (IS_ERR(parent_clk)) { |
| 864 | dev_err(&pdev->dev, "failed to get parent clock\n"); |
| 865 | ret = PTR_ERR(parent_clk); |
| 866 | goto err1; |
| 867 | } |
| 868 | |
| 869 | ret = clk_set_parent(gfclk, parent_clk); |
| 870 | if (ret) { |
| 871 | dev_err(&pdev->dev, "failed to reparent fck\n"); |
| 872 | goto err2; |
| 873 | } |
| 874 | |
| 875 | err2: |
| 876 | clk_put(parent_clk); |
| 877 | err1: |
| 878 | clk_put(gfclk); |
| 879 | return ret; |
| 880 | } |
| 881 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 882 | static struct snd_platform_data *davinci_mcasp_set_pdata_from_of( |
| 883 | struct platform_device *pdev) |
| 884 | { |
| 885 | struct device_node *np = pdev->dev.of_node; |
| 886 | struct snd_platform_data *pdata = NULL; |
| 887 | const struct of_device_id *match = |
Sachin Kamat | ea421eb | 2013-05-22 16:53:37 +0530 | [diff] [blame] | 888 | of_match_device(mcasp_dt_ids, &pdev->dev); |
Jyri Sarha | 4023fe6 | 2013-10-18 18:37:43 +0300 | [diff] [blame] | 889 | struct of_phandle_args dma_spec; |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 890 | |
| 891 | const u32 *of_serial_dir32; |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 892 | u32 val; |
| 893 | int i, ret = 0; |
| 894 | |
| 895 | if (pdev->dev.platform_data) { |
| 896 | pdata = pdev->dev.platform_data; |
| 897 | return pdata; |
| 898 | } else if (match) { |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 899 | pdata = (struct snd_platform_data *) match->data; |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 900 | } else { |
| 901 | /* control shouldn't reach here. something is wrong */ |
| 902 | ret = -EINVAL; |
| 903 | goto nodata; |
| 904 | } |
| 905 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 906 | ret = of_property_read_u32(np, "op-mode", &val); |
| 907 | if (ret >= 0) |
| 908 | pdata->op_mode = val; |
| 909 | |
| 910 | ret = of_property_read_u32(np, "tdm-slots", &val); |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 911 | if (ret >= 0) { |
| 912 | if (val < 2 || val > 32) { |
| 913 | dev_err(&pdev->dev, |
| 914 | "tdm-slots must be in rage [2-32]\n"); |
| 915 | ret = -EINVAL; |
| 916 | goto nodata; |
| 917 | } |
| 918 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 919 | pdata->tdm_slots = val; |
Michal Bachraty | 2952b27 | 2013-02-28 16:07:08 +0100 | [diff] [blame] | 920 | } |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 921 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 922 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
| 923 | val /= sizeof(u32); |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 924 | if (of_serial_dir32) { |
Peter Ujfalusi | 1427e66 | 2013-10-18 18:37:46 +0300 | [diff] [blame] | 925 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
| 926 | (sizeof(*of_serial_dir) * val), |
| 927 | GFP_KERNEL); |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 928 | if (!of_serial_dir) { |
| 929 | ret = -ENOMEM; |
| 930 | goto nodata; |
| 931 | } |
| 932 | |
Peter Ujfalusi | 1427e66 | 2013-10-18 18:37:46 +0300 | [diff] [blame] | 933 | for (i = 0; i < val; i++) |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 934 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
| 935 | |
Peter Ujfalusi | 1427e66 | 2013-10-18 18:37:46 +0300 | [diff] [blame] | 936 | pdata->num_serializer = val; |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 937 | pdata->serial_dir = of_serial_dir; |
| 938 | } |
| 939 | |
Jyri Sarha | 4023fe6 | 2013-10-18 18:37:43 +0300 | [diff] [blame] | 940 | ret = of_property_match_string(np, "dma-names", "tx"); |
| 941 | if (ret < 0) |
| 942 | goto nodata; |
| 943 | |
| 944 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, |
| 945 | &dma_spec); |
| 946 | if (ret < 0) |
| 947 | goto nodata; |
| 948 | |
| 949 | pdata->tx_dma_channel = dma_spec.args[0]; |
| 950 | |
| 951 | ret = of_property_match_string(np, "dma-names", "rx"); |
| 952 | if (ret < 0) |
| 953 | goto nodata; |
| 954 | |
| 955 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, |
| 956 | &dma_spec); |
| 957 | if (ret < 0) |
| 958 | goto nodata; |
| 959 | |
| 960 | pdata->rx_dma_channel = dma_spec.args[0]; |
| 961 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 962 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
| 963 | if (ret >= 0) |
| 964 | pdata->txnumevt = val; |
| 965 | |
| 966 | ret = of_property_read_u32(np, "rx-num-evt", &val); |
| 967 | if (ret >= 0) |
| 968 | pdata->rxnumevt = val; |
| 969 | |
| 970 | ret = of_property_read_u32(np, "sram-size-playback", &val); |
| 971 | if (ret >= 0) |
| 972 | pdata->sram_size_playback = val; |
| 973 | |
| 974 | ret = of_property_read_u32(np, "sram-size-capture", &val); |
| 975 | if (ret >= 0) |
| 976 | pdata->sram_size_capture = val; |
| 977 | |
| 978 | return pdata; |
| 979 | |
| 980 | nodata: |
| 981 | if (ret < 0) { |
| 982 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", |
| 983 | ret); |
| 984 | pdata = NULL; |
| 985 | } |
| 986 | return pdata; |
| 987 | } |
| 988 | |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 989 | static int davinci_mcasp_probe(struct platform_device *pdev) |
| 990 | { |
| 991 | struct davinci_pcm_dma_params *dma_data; |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 992 | struct resource *mem, *ioarea, *res, *dat; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 993 | struct snd_platform_data *pdata; |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 994 | struct davinci_mcasp *mcasp; |
Julia Lawall | 96d31e2 | 2011-12-29 17:51:21 +0100 | [diff] [blame] | 995 | int ret; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 996 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 997 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
| 998 | dev_err(&pdev->dev, "No platform data supplied\n"); |
| 999 | return -EINVAL; |
| 1000 | } |
| 1001 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1002 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
Julia Lawall | 96d31e2 | 2011-12-29 17:51:21 +0100 | [diff] [blame] | 1003 | GFP_KERNEL); |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1004 | if (!mcasp) |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1005 | return -ENOMEM; |
| 1006 | |
Hebbar, Gururaja | 3e3b8c3 | 2012-08-27 18:56:42 +0530 | [diff] [blame] | 1007 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
| 1008 | if (!pdata) { |
| 1009 | dev_err(&pdev->dev, "no platform data\n"); |
| 1010 | return -EINVAL; |
| 1011 | } |
| 1012 | |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 1013 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1014 | if (!mem) { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1015 | dev_warn(mcasp->dev, |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 1016 | "\"mpu\" mem resource not found, using index 0\n"); |
| 1017 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1018 | if (!mem) { |
| 1019 | dev_err(&pdev->dev, "no mem resource?\n"); |
| 1020 | return -ENODEV; |
| 1021 | } |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1022 | } |
| 1023 | |
Julia Lawall | 96d31e2 | 2011-12-29 17:51:21 +0100 | [diff] [blame] | 1024 | ioarea = devm_request_mem_region(&pdev->dev, mem->start, |
Vaibhav Bedia | d852f446 | 2011-02-09 18:39:52 +0530 | [diff] [blame] | 1025 | resource_size(mem), pdev->name); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1026 | if (!ioarea) { |
| 1027 | dev_err(&pdev->dev, "Audio region already claimed\n"); |
Julia Lawall | 96d31e2 | 2011-12-29 17:51:21 +0100 | [diff] [blame] | 1028 | return -EBUSY; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1029 | } |
| 1030 | |
Hebbar, Gururaja | 1088434 | 2012-08-08 20:40:32 +0530 | [diff] [blame] | 1031 | pm_runtime_enable(&pdev->dev); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1032 | |
Hebbar, Gururaja | 1088434 | 2012-08-08 20:40:32 +0530 | [diff] [blame] | 1033 | ret = pm_runtime_get_sync(&pdev->dev); |
| 1034 | if (IS_ERR_VALUE(ret)) { |
| 1035 | dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); |
| 1036 | return ret; |
| 1037 | } |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1038 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1039 | mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
| 1040 | if (!mcasp->base) { |
Vaibhav Bedia | 4f82f02 | 2011-02-09 18:39:54 +0530 | [diff] [blame] | 1041 | dev_err(&pdev->dev, "ioremap failed\n"); |
| 1042 | ret = -ENOMEM; |
| 1043 | goto err_release_clk; |
| 1044 | } |
| 1045 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1046 | mcasp->op_mode = pdata->op_mode; |
| 1047 | mcasp->tdm_slots = pdata->tdm_slots; |
| 1048 | mcasp->num_serializer = pdata->num_serializer; |
| 1049 | mcasp->serial_dir = pdata->serial_dir; |
| 1050 | mcasp->version = pdata->version; |
| 1051 | mcasp->txnumevt = pdata->txnumevt; |
| 1052 | mcasp->rxnumevt = pdata->rxnumevt; |
Peter Ujfalusi | 487dce8 | 2013-11-14 11:35:31 +0200 | [diff] [blame] | 1053 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1054 | mcasp->dev = &pdev->dev; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1055 | |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 1056 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 1057 | if (dat) |
| 1058 | mcasp->dat_port = true; |
Jyri Sarha | 256ba18 | 2013-10-18 18:37:42 +0300 | [diff] [blame] | 1059 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1060 | dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; |
Sekhar Nori | 48519f0 | 2010-07-19 12:31:16 +0530 | [diff] [blame] | 1061 | dma_data->asp_chan_q = pdata->asp_chan_q; |
| 1062 | dma_data->ram_chan_q = pdata->ram_chan_q; |
Matt Porter | b8ec56d | 2012-10-17 16:08:03 +0200 | [diff] [blame] | 1063 | dma_data->sram_pool = pdata->sram_pool; |
Ben Gardiner | a0c8326 | 2011-05-18 09:27:45 -0400 | [diff] [blame] | 1064 | dma_data->sram_size = pdata->sram_size_playback; |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 1065 | if (dat) |
| 1066 | dma_data->dma_addr = dat->start; |
| 1067 | else |
| 1068 | dma_data->dma_addr = mem->start + pdata->tx_dma_offset; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1069 | |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1070 | /* Unconditional dmaengine stuff */ |
| 1071 | mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = dma_data->dma_addr; |
| 1072 | |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1073 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
Jyri Sarha | 4023fe6 | 2013-10-18 18:37:43 +0300 | [diff] [blame] | 1074 | if (res) |
| 1075 | dma_data->channel = res->start; |
| 1076 | else |
| 1077 | dma_data->channel = pdata->tx_dma_channel; |
Troy Kisky | 92e2a6f | 2009-09-11 14:29:03 -0700 | [diff] [blame] | 1078 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1079 | dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE]; |
Sekhar Nori | 48519f0 | 2010-07-19 12:31:16 +0530 | [diff] [blame] | 1080 | dma_data->asp_chan_q = pdata->asp_chan_q; |
| 1081 | dma_data->ram_chan_q = pdata->ram_chan_q; |
Matt Porter | b8ec56d | 2012-10-17 16:08:03 +0200 | [diff] [blame] | 1082 | dma_data->sram_pool = pdata->sram_pool; |
Ben Gardiner | a0c8326 | 2011-05-18 09:27:45 -0400 | [diff] [blame] | 1083 | dma_data->sram_size = pdata->sram_size_capture; |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 1084 | if (dat) |
| 1085 | dma_data->dma_addr = dat->start; |
| 1086 | else |
| 1087 | dma_data->dma_addr = mem->start + pdata->rx_dma_offset; |
| 1088 | |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1089 | /* Unconditional dmaengine stuff */ |
| 1090 | mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = dma_data->dma_addr; |
| 1091 | |
Peter Ujfalusi | cbc7956c | 2013-11-14 11:35:32 +0200 | [diff] [blame] | 1092 | if (mcasp->version < MCASP_VERSION_3) { |
| 1093 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; |
| 1094 | /* dma_data->dma_addr is pointing to the data port address */ |
| 1095 | mcasp->dat_port = true; |
| 1096 | } else { |
| 1097 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; |
| 1098 | } |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1099 | |
| 1100 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
Jyri Sarha | 4023fe6 | 2013-10-18 18:37:43 +0300 | [diff] [blame] | 1101 | if (res) |
| 1102 | dma_data->channel = res->start; |
| 1103 | else |
| 1104 | dma_data->channel = pdata->rx_dma_channel; |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1105 | |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1106 | /* Unconditional dmaengine stuff */ |
| 1107 | mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = "tx"; |
| 1108 | mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].filter_data = "rx"; |
| 1109 | |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1110 | dev_set_drvdata(&pdev->dev, mcasp); |
Peter Ujfalusi | ae726e9 | 2013-11-14 11:35:35 +0200 | [diff] [blame] | 1111 | |
| 1112 | mcasp_reparent_fck(pdev); |
| 1113 | |
Kuninori Morimoto | eeef0ed | 2013-03-21 03:31:19 -0700 | [diff] [blame] | 1114 | ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, |
| 1115 | &davinci_mcasp_dai[pdata->op_mode], 1); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1116 | |
| 1117 | if (ret != 0) |
Julia Lawall | 96d31e2 | 2011-12-29 17:51:21 +0100 | [diff] [blame] | 1118 | goto err_release_clk; |
Hebbar, Gururaja | f08095a | 2012-08-27 18:56:39 +0530 | [diff] [blame] | 1119 | |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1120 | if (mcasp->version != MCASP_VERSION_4) { |
| 1121 | ret = davinci_soc_platform_register(&pdev->dev); |
| 1122 | if (ret) { |
| 1123 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); |
| 1124 | goto err_unregister_component; |
| 1125 | } |
Hebbar, Gururaja | f08095a | 2012-08-27 18:56:39 +0530 | [diff] [blame] | 1126 | } |
| 1127 | |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1128 | return 0; |
| 1129 | |
Kuninori Morimoto | eeef0ed | 2013-03-21 03:31:19 -0700 | [diff] [blame] | 1130 | err_unregister_component: |
| 1131 | snd_soc_unregister_component(&pdev->dev); |
Vaibhav Bedia | eef6d7b | 2011-02-09 18:39:53 +0530 | [diff] [blame] | 1132 | err_release_clk: |
Hebbar, Gururaja | 1088434 | 2012-08-08 20:40:32 +0530 | [diff] [blame] | 1133 | pm_runtime_put_sync(&pdev->dev); |
| 1134 | pm_runtime_disable(&pdev->dev); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1135 | return ret; |
| 1136 | } |
| 1137 | |
| 1138 | static int davinci_mcasp_remove(struct platform_device *pdev) |
| 1139 | { |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1140 | struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1141 | |
Kuninori Morimoto | eeef0ed | 2013-03-21 03:31:19 -0700 | [diff] [blame] | 1142 | snd_soc_unregister_component(&pdev->dev); |
Peter Ujfalusi | 453c499 | 2013-11-14 11:35:34 +0200 | [diff] [blame] | 1143 | if (mcasp->version != MCASP_VERSION_4) |
| 1144 | davinci_soc_platform_unregister(&pdev->dev); |
Hebbar, Gururaja | 1088434 | 2012-08-08 20:40:32 +0530 | [diff] [blame] | 1145 | |
| 1146 | pm_runtime_put_sync(&pdev->dev); |
| 1147 | pm_runtime_disable(&pdev->dev); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1148 | |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1149 | return 0; |
| 1150 | } |
| 1151 | |
Daniel Mack | a85e419 | 2013-10-01 14:50:02 +0200 | [diff] [blame] | 1152 | #ifdef CONFIG_PM_SLEEP |
| 1153 | static int davinci_mcasp_suspend(struct device *dev) |
| 1154 | { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1155 | struct davinci_mcasp *mcasp = dev_get_drvdata(dev); |
Daniel Mack | a85e419 | 2013-10-01 14:50:02 +0200 | [diff] [blame] | 1156 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 1157 | mcasp->context.txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG); |
| 1158 | mcasp->context.rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
| 1159 | mcasp->context.txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG); |
| 1160 | mcasp->context.rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG); |
| 1161 | mcasp->context.aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); |
| 1162 | mcasp->context.aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG); |
| 1163 | mcasp->context.pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); |
Daniel Mack | a85e419 | 2013-10-01 14:50:02 +0200 | [diff] [blame] | 1164 | |
| 1165 | return 0; |
| 1166 | } |
| 1167 | |
| 1168 | static int davinci_mcasp_resume(struct device *dev) |
| 1169 | { |
Peter Ujfalusi | 70091a3 | 2013-11-14 11:35:29 +0200 | [diff] [blame] | 1170 | struct davinci_mcasp *mcasp = dev_get_drvdata(dev); |
Daniel Mack | a85e419 | 2013-10-01 14:50:02 +0200 | [diff] [blame] | 1171 | |
Peter Ujfalusi | f68205a | 2013-11-14 11:35:36 +0200 | [diff] [blame] | 1172 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl); |
| 1173 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl); |
| 1174 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt); |
| 1175 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt); |
| 1176 | mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl); |
| 1177 | mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl); |
| 1178 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir); |
Daniel Mack | a85e419 | 2013-10-01 14:50:02 +0200 | [diff] [blame] | 1179 | |
| 1180 | return 0; |
| 1181 | } |
| 1182 | #endif |
| 1183 | |
| 1184 | SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops, |
| 1185 | davinci_mcasp_suspend, |
| 1186 | davinci_mcasp_resume); |
| 1187 | |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1188 | static struct platform_driver davinci_mcasp_driver = { |
| 1189 | .probe = davinci_mcasp_probe, |
| 1190 | .remove = davinci_mcasp_remove, |
| 1191 | .driver = { |
| 1192 | .name = "davinci-mcasp", |
| 1193 | .owner = THIS_MODULE, |
Daniel Mack | a85e419 | 2013-10-01 14:50:02 +0200 | [diff] [blame] | 1194 | .pm = &davinci_mcasp_pm_ops, |
Sachin Kamat | ea421eb | 2013-05-22 16:53:37 +0530 | [diff] [blame] | 1195 | .of_match_table = mcasp_dt_ids, |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1196 | }, |
| 1197 | }; |
| 1198 | |
Axel Lin | f9b8a51 | 2011-11-25 10:09:27 +0800 | [diff] [blame] | 1199 | module_platform_driver(davinci_mcasp_driver); |
Chaithrika U S | b67f448 | 2009-06-05 06:28:40 -0400 | [diff] [blame] | 1200 | |
| 1201 | MODULE_AUTHOR("Steve Chen"); |
| 1202 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); |
| 1203 | MODULE_LICENSE("GPL"); |