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Chaithrika U Sb67f4482009-06-05 06:28:40 -04001/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040022#include <linux/delay.h>
23#include <linux/io.h>
Peter Ujfalusiae726e92013-11-14 11:35:35 +020024#include <linux/clk.h>
Hebbar, Gururaja10884342012-08-08 20:40:32 +053025#include <linux/pm_runtime.h>
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +053026#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/of_device.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040029
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/initval.h>
34#include <sound/soc.h>
Peter Ujfalusi453c4992013-11-14 11:35:34 +020035#include <sound/dmaengine_pcm.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040036
37#include "davinci-pcm.h"
38#include "davinci-mcasp.h"
39
Peter Ujfalusi70091a32013-11-14 11:35:29 +020040struct davinci_mcasp {
Peter Ujfalusi21400a72013-11-14 11:35:26 +020041 struct davinci_pcm_dma_params dma_params[2];
Peter Ujfalusi453c4992013-11-14 11:35:34 +020042 struct snd_dmaengine_dai_dma_data dma_data[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +020043 void __iomem *base;
Peter Ujfalusi487dce82013-11-14 11:35:31 +020044 u32 fifo_base;
Peter Ujfalusi21400a72013-11-14 11:35:26 +020045 struct device *dev;
46
47 /* McASP specific data */
48 int tdm_slots;
49 u8 op_mode;
50 u8 num_serializer;
51 u8 *serial_dir;
52 u8 version;
53 u16 bclk_lrclk_ratio;
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +020054 int streams;
Peter Ujfalusi21400a72013-11-14 11:35:26 +020055
Jyri Sarhaab8b14b2014-01-27 17:37:52 +020056 int sysclk_freq;
57 bool bclk_master;
58
Peter Ujfalusi21400a72013-11-14 11:35:26 +020059 /* McASP FIFO related */
60 u8 txnumevt;
61 u8 rxnumevt;
62
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +020063 bool dat_port;
64
Peter Ujfalusi21400a72013-11-14 11:35:26 +020065#ifdef CONFIG_PM_SLEEP
66 struct {
67 u32 txfmtctl;
68 u32 rxfmtctl;
69 u32 txfmt;
70 u32 rxfmt;
71 u32 aclkxctl;
72 u32 aclkrctl;
73 u32 pdir;
74 } context;
75#endif
76};
77
Peter Ujfalusif68205a2013-11-14 11:35:36 +020078static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
79 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -040080{
Peter Ujfalusif68205a2013-11-14 11:35:36 +020081 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -040082 __raw_writel(__raw_readl(reg) | val, reg);
83}
84
Peter Ujfalusif68205a2013-11-14 11:35:36 +020085static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
86 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -040087{
Peter Ujfalusif68205a2013-11-14 11:35:36 +020088 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -040089 __raw_writel((__raw_readl(reg) & ~(val)), reg);
90}
91
Peter Ujfalusif68205a2013-11-14 11:35:36 +020092static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
93 u32 val, u32 mask)
Chaithrika U Sb67f4482009-06-05 06:28:40 -040094{
Peter Ujfalusif68205a2013-11-14 11:35:36 +020095 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -040096 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
97}
98
Peter Ujfalusif68205a2013-11-14 11:35:36 +020099static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
100 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400101{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200102 __raw_writel(val, mcasp->base + offset);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400103}
104
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200105static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400106{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200107 return (u32)__raw_readl(mcasp->base + offset);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400108}
109
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200110static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400111{
112 int i = 0;
113
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200114 mcasp_set_bits(mcasp, ctl_reg, val);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400115
116 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
117 /* loop count is to avoid the lock-up */
118 for (i = 0; i < 1000; i++) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200119 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400120 break;
121 }
122
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200123 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400124 printk(KERN_ERR "GBLCTL write error\n");
125}
126
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200127static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
128{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200129 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
130 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200131
132 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
133}
134
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200135static void mcasp_start_rx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400136{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200137 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
138 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200139
140 /*
141 * When ASYNC == 0 the transmit and receive sections operate
142 * synchronously from the transmit clock and frame sync. We need to make
143 * sure that the TX signlas are enabled when starting reception.
144 */
145 if (mcasp_is_synchronous(mcasp)) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200146 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
147 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200148 }
149
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200150 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
151 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400152
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200153 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
154 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
155 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400156
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200157 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
158 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200159
160 if (mcasp_is_synchronous(mcasp))
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200161 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400162}
163
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200164static void mcasp_start_tx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400165{
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400166 u8 offset = 0, i;
167 u32 cnt;
168
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200169 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
170 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
171 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
172 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400173
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200174 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
175 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
176 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200177 for (i = 0; i < mcasp->num_serializer; i++) {
178 if (mcasp->serial_dir[i] == TX_MODE) {
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400179 offset = i;
180 break;
181 }
182 }
183
184 /* wait for TX ready */
185 cnt = 0;
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200186 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400187 TXSTATE) && (cnt < 100000))
188 cnt++;
189
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200190 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400191}
192
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200193static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400194{
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200195 u32 reg;
196
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200197 mcasp->streams++;
198
Chaithrika U S539d3d82009-09-23 10:12:08 -0400199 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200200 if (mcasp->txnumevt) { /* enable FIFO */
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200201 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200202 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
203 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
Vaibhav Bedia0d624272012-08-08 20:40:31 +0530204 }
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200205 mcasp_start_tx(mcasp);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400206 } else {
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200207 if (mcasp->rxnumevt) { /* enable FIFO */
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200208 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200209 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
210 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
Vaibhav Bedia0d624272012-08-08 20:40:31 +0530211 }
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200212 mcasp_start_rx(mcasp);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400213 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400214}
215
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200216static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400217{
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200218 /*
219 * In synchronous mode stop the TX clocks if no other stream is
220 * running
221 */
222 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200223 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200224
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200225 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
226 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400227}
228
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200229static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400230{
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200231 u32 val = 0;
232
233 /*
234 * In synchronous mode keep TX clocks running if the capture stream is
235 * still running.
236 */
237 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
238 val = TXHCLKRST | TXCLKRST | TXFSRST;
239
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200240 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
241 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400242}
243
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200244static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400245{
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200246 u32 reg;
247
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200248 mcasp->streams--;
249
Chaithrika U S539d3d82009-09-23 10:12:08 -0400250 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200251 if (mcasp->txnumevt) { /* disable FIFO */
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200252 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200253 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530254 }
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200255 mcasp_stop_tx(mcasp);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400256 } else {
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200257 if (mcasp->rxnumevt) { /* disable FIFO */
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200258 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200259 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530260 }
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200261 mcasp_stop_rx(mcasp);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400262 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400263}
264
265static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
266 unsigned int fmt)
267{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200268 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200269 int ret = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400270
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200271 pm_runtime_get_sync(mcasp->dev);
Daniel Mack5296cf22012-10-04 15:08:42 +0200272 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
273 case SND_SOC_DAIFMT_DSP_B:
274 case SND_SOC_DAIFMT_AC97:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200275 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
276 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
Daniel Mack5296cf22012-10-04 15:08:42 +0200277 break;
278 default:
279 /* configure a full-word SYNC pulse (LRCLK) */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200280 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
281 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
Daniel Mack5296cf22012-10-04 15:08:42 +0200282
283 /* make 1st data bit occur one ACLK cycle after the frame sync */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200284 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
285 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
Daniel Mack5296cf22012-10-04 15:08:42 +0200286 break;
287 }
288
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400289 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
290 case SND_SOC_DAIFMT_CBS_CFS:
291 /* codec is clock and frame slave */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200292 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
293 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400294
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200295 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
296 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400297
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200298 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
299 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200300 mcasp->bclk_master = 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400301 break;
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400302 case SND_SOC_DAIFMT_CBM_CFS:
303 /* codec is clock master and frame slave */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200304 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
305 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400306
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200307 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
308 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400309
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200310 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
311 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200312 mcasp->bclk_master = 0;
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400313 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400314 case SND_SOC_DAIFMT_CBM_CFM:
315 /* codec is clock and frame master */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200316 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
317 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400318
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200319 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
320 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400321
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200322 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
323 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200324 mcasp->bclk_master = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400325 break;
326
327 default:
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200328 ret = -EINVAL;
329 goto out;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400330 }
331
332 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
333 case SND_SOC_DAIFMT_IB_NF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200334 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
335 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400336
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200337 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
338 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400339 break;
340
341 case SND_SOC_DAIFMT_NB_IF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200342 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
343 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400344
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200345 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
346 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400347 break;
348
349 case SND_SOC_DAIFMT_IB_IF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200350 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
351 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400352
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200353 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
354 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400355 break;
356
357 case SND_SOC_DAIFMT_NB_NF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200358 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
359 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400360
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200361 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
362 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400363 break;
364
365 default:
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200366 ret = -EINVAL;
367 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400368 }
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200369out:
370 pm_runtime_put_sync(mcasp->dev);
371 return ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400372}
373
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200374static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
375{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200376 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200377
378 switch (div_id) {
379 case 0: /* MCLK divider */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200380 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200381 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200382 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200383 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
384 break;
385
386 case 1: /* BCLK divider */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200387 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200388 ACLKXDIV(div - 1), ACLKXDIV_MASK);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200389 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200390 ACLKRDIV(div - 1), ACLKRDIV_MASK);
391 break;
392
Daniel Mack1b3bc062012-12-05 18:20:38 +0100393 case 2: /* BCLK/LRCLK ratio */
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200394 mcasp->bclk_lrclk_ratio = div;
Daniel Mack1b3bc062012-12-05 18:20:38 +0100395 break;
396
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200397 default:
398 return -EINVAL;
399 }
400
401 return 0;
402}
403
Daniel Mack5b66aa22012-10-04 15:08:41 +0200404static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
405 unsigned int freq, int dir)
406{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200407 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200408
409 if (dir == SND_SOC_CLOCK_OUT) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200410 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
411 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
412 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200413 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200414 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
415 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
416 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200417 }
418
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200419 mcasp->sysclk_freq = freq;
420
Daniel Mack5b66aa22012-10-04 15:08:41 +0200421 return 0;
422}
423
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200424static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
Daniel Mackba764b32012-12-05 18:20:37 +0100425 int word_length)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400426{
Daniel Mackba764b32012-12-05 18:20:37 +0100427 u32 fmt;
Daniel Mack79671892013-05-16 15:25:01 +0200428 u32 tx_rotate = (word_length / 4) & 0x7;
429 u32 rx_rotate = (32 - word_length) / 4;
Daniel Mackba764b32012-12-05 18:20:37 +0100430 u32 mask = (1ULL << word_length) - 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400431
Daniel Mack1b3bc062012-12-05 18:20:38 +0100432 /*
433 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
434 * callback, take it into account here. That allows us to for example
435 * send 32 bits per channel to the codec, while only 16 of them carry
436 * audio payload.
Michal Bachratyd486fea2013-04-19 15:28:44 +0200437 * The clock ratio is given for a full period of data (for I2S format
438 * both left and right channels), so it has to be divided by number of
439 * tdm-slots (for I2S - divided by 2).
Daniel Mack1b3bc062012-12-05 18:20:38 +0100440 */
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200441 if (mcasp->bclk_lrclk_ratio)
442 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
Daniel Mack1b3bc062012-12-05 18:20:38 +0100443
Daniel Mackba764b32012-12-05 18:20:37 +0100444 /* mapping of the XSSZ bit-field as described in the datasheet */
445 fmt = (word_length >> 1) - 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400446
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200447 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200448 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
449 RXSSZ(0x0F));
450 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
451 TXSSZ(0x0F));
452 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
453 TXROT(7));
454 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
455 RXROT(7));
456 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
Yegor Yefremovf5023af2013-04-04 16:13:20 +0200457 }
458
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200459 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400460
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400461 return 0;
462}
463
Peter Ujfalusi662ffae2014-01-30 15:15:22 +0200464static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
Michal Bachraty2952b272013-02-28 16:07:08 +0100465 int channels)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400466{
467 int i;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400468 u8 tx_ser = 0;
469 u8 rx_ser = 0;
Michal Bachraty2952b272013-02-28 16:07:08 +0100470 u8 ser;
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200471 u8 slots = mcasp->tdm_slots;
Michal Bachraty2952b272013-02-28 16:07:08 +0100472 u8 max_active_serializers = (channels + slots - 1) / slots;
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200473 u32 reg;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400474 /* Default configuration */
Peter Ujfalusi453c4992013-11-14 11:35:34 +0200475 if (mcasp->version != MCASP_VERSION_4)
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200476 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400477
478 /* All PINS as McASP */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200479 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400480
481 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200482 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
483 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400484 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200485 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
486 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400487 }
488
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200489 for (i = 0; i < mcasp->num_serializer; i++) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200490 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
491 mcasp->serial_dir[i]);
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200492 if (mcasp->serial_dir[i] == TX_MODE &&
Michal Bachraty2952b272013-02-28 16:07:08 +0100493 tx_ser < max_active_serializers) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200494 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400495 tx_ser++;
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200496 } else if (mcasp->serial_dir[i] == RX_MODE &&
Michal Bachraty2952b272013-02-28 16:07:08 +0100497 rx_ser < max_active_serializers) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200498 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400499 rx_ser++;
Michal Bachraty2952b272013-02-28 16:07:08 +0100500 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200501 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
502 SRMOD_INACTIVE, SRMOD_MASK);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400503 }
504 }
505
Daniel Mackecf327c2013-03-08 14:19:38 +0100506 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
507 ser = tx_ser;
508 else
509 ser = rx_ser;
510
511 if (ser < max_active_serializers) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200512 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
Daniel Mackecf327c2013-03-08 14:19:38 +0100513 "enabled in mcasp (%d)\n", channels, ser * slots);
514 return -EINVAL;
515 }
516
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200517 if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
518 if (mcasp->txnumevt * tx_ser > 64)
519 mcasp->txnumevt = 1;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400520
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200521 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200522 mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK);
523 mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8),
524 NUMEVT_MASK);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400525 }
526
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200527 if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
528 if (mcasp->rxnumevt * rx_ser > 64)
529 mcasp->rxnumevt = 1;
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200530
531 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200532 mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK);
533 mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8),
534 NUMEVT_MASK);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400535 }
Michal Bachraty2952b272013-02-28 16:07:08 +0100536
537 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400538}
539
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200540static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400541{
542 int i, active_slots;
543 u32 mask = 0;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +0200544 u32 busel = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400545
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200546 if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
547 dev_err(mcasp->dev, "tdm slot %d not supported\n",
548 mcasp->tdm_slots);
549 return -EINVAL;
550 }
551
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200552 active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400553 for (i = 0; i < active_slots; i++)
554 mask |= (1 << i);
555
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200556 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400557
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +0200558 if (!mcasp->dat_port)
559 busel = TXSEL;
560
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200561 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
562 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
563 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
564 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400565
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200566 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
567 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
568 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
569 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400570
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200571 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400572}
573
574/* S/PDIF */
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200575static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400576{
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400577 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
578 and LSB first */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200579 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400580
581 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200582 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400583
584 /* Set the TX tdm : for all the slots */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200585 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400586
587 /* Set the TX clock controls : div = 1 and internal */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200588 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400589
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200590 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400591
592 /* Only 44100 and 48000 are valid, both have the same setting */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200593 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400594
595 /* Enable the DIT */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200596 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200597
598 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400599}
600
601static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
602 struct snd_pcm_hw_params *params,
603 struct snd_soc_dai *cpu_dai)
604{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200605 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400606 struct davinci_pcm_dma_params *dma_params =
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200607 &mcasp->dma_params[substream->stream];
Peter Ujfalusi453c4992013-11-14 11:35:34 +0200608 struct snd_dmaengine_dai_dma_data *dma_data =
609 &mcasp->dma_data[substream->stream];
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400610 int word_length;
Chaithrika U S4fa9c1a2009-09-30 17:32:27 -0400611 u8 fifo_level;
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200612 u8 slots = mcasp->tdm_slots;
Michal Bachraty7c21a782013-04-19 15:28:03 +0200613 u8 active_serializers;
Michal Bachraty2952b272013-02-28 16:07:08 +0100614 int channels;
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200615 int ret;
Michal Bachraty2952b272013-02-28 16:07:08 +0100616 struct snd_interval *pcm_channels = hw_param_interval(params,
617 SNDRV_PCM_HW_PARAM_CHANNELS);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200618
619 /* If mcasp is BCLK master we need to set BCLK divider */
620 if (mcasp->bclk_master) {
621 unsigned int bclk_freq = snd_soc_params_to_bclk(params);
622 if (mcasp->sysclk_freq % bclk_freq != 0) {
623 dev_err(mcasp->dev, "Can't produce requred BCLK\n");
624 return -EINVAL;
625 }
626 davinci_mcasp_set_clkdiv(
627 cpu_dai, 1, mcasp->sysclk_freq / bclk_freq);
628 }
629
Michal Bachraty2952b272013-02-28 16:07:08 +0100630 channels = pcm_channels->min;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400631
Michal Bachraty7c21a782013-04-19 15:28:03 +0200632 active_serializers = (channels + slots - 1) / slots;
633
Peter Ujfalusi0f7d9a62014-01-30 15:15:24 +0200634 ret = mcasp_common_hw_param(mcasp, substream->stream, channels);
635 if (ret)
636 return ret;
637
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400638 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200639 fifo_level = mcasp->txnumevt * active_serializers;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400640 else
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200641 fifo_level = mcasp->rxnumevt * active_serializers;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400642
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200643 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200644 ret = mcasp_dit_hw_param(mcasp);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400645 else
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200646 ret = mcasp_i2s_hw_param(mcasp, substream->stream);
647
648 if (ret)
649 return ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400650
651 switch (params_format(params)) {
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400652 case SNDRV_PCM_FORMAT_U8:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400653 case SNDRV_PCM_FORMAT_S8:
654 dma_params->data_type = 1;
Daniel Mackba764b32012-12-05 18:20:37 +0100655 word_length = 8;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400656 break;
657
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400658 case SNDRV_PCM_FORMAT_U16_LE:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400659 case SNDRV_PCM_FORMAT_S16_LE:
660 dma_params->data_type = 2;
Daniel Mackba764b32012-12-05 18:20:37 +0100661 word_length = 16;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400662 break;
663
Daniel Mack21eb24d2012-10-09 09:35:16 +0200664 case SNDRV_PCM_FORMAT_U24_3LE:
665 case SNDRV_PCM_FORMAT_S24_3LE:
Daniel Mack21eb24d2012-10-09 09:35:16 +0200666 dma_params->data_type = 3;
Daniel Mackba764b32012-12-05 18:20:37 +0100667 word_length = 24;
Daniel Mack21eb24d2012-10-09 09:35:16 +0200668 break;
669
Daniel Mack6b7fa012012-10-09 11:56:40 +0200670 case SNDRV_PCM_FORMAT_U24_LE:
671 case SNDRV_PCM_FORMAT_S24_LE:
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400672 case SNDRV_PCM_FORMAT_U32_LE:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400673 case SNDRV_PCM_FORMAT_S32_LE:
674 dma_params->data_type = 4;
Daniel Mackba764b32012-12-05 18:20:37 +0100675 word_length = 32;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400676 break;
677
678 default:
679 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
680 return -EINVAL;
681 }
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400682
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200683 if (mcasp->version == MCASP_VERSION_2 && !fifo_level)
Chaithrika U S4fa9c1a2009-09-30 17:32:27 -0400684 dma_params->acnt = 4;
685 else
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400686 dma_params->acnt = dma_params->data_type;
687
Chaithrika U S4fa9c1a2009-09-30 17:32:27 -0400688 dma_params->fifo_level = fifo_level;
Peter Ujfalusi453c4992013-11-14 11:35:34 +0200689 dma_data->maxburst = fifo_level;
690
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200691 davinci_config_channel_size(mcasp, word_length);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400692
693 return 0;
694}
695
696static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
697 int cmd, struct snd_soc_dai *cpu_dai)
698{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200699 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400700 int ret = 0;
701
702 switch (cmd) {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400703 case SNDRV_PCM_TRIGGER_RESUME:
Chaithrika U Se473b842010-01-20 17:06:33 +0530704 case SNDRV_PCM_TRIGGER_START:
705 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200706 davinci_mcasp_start(mcasp, substream->stream);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400707 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400708 case SNDRV_PCM_TRIGGER_SUSPEND:
Chaithrika U Sa47979b2009-12-03 18:56:56 +0530709 case SNDRV_PCM_TRIGGER_STOP:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400710 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200711 davinci_mcasp_stop(mcasp, substream->stream);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400712 break;
713
714 default:
715 ret = -EINVAL;
716 }
717
718 return ret;
719}
720
Chris Paulson-Ellisbedad0c2010-11-16 12:27:09 +0000721static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
722 struct snd_soc_dai *dai)
723{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200724 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Chris Paulson-Ellisbedad0c2010-11-16 12:27:09 +0000725
Peter Ujfalusi453c4992013-11-14 11:35:34 +0200726 if (mcasp->version == MCASP_VERSION_4)
727 snd_soc_dai_set_dma_data(dai, substream,
728 &mcasp->dma_data[substream->stream]);
729 else
730 snd_soc_dai_set_dma_data(dai, substream, mcasp->dma_params);
731
Chris Paulson-Ellisbedad0c2010-11-16 12:27:09 +0000732 return 0;
733}
734
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100735static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
Chris Paulson-Ellisbedad0c2010-11-16 12:27:09 +0000736 .startup = davinci_mcasp_startup,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400737 .trigger = davinci_mcasp_trigger,
738 .hw_params = davinci_mcasp_hw_params,
739 .set_fmt = davinci_mcasp_set_dai_fmt,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200740 .set_clkdiv = davinci_mcasp_set_clkdiv,
Daniel Mack5b66aa22012-10-04 15:08:41 +0200741 .set_sysclk = davinci_mcasp_set_sysclk,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400742};
743
Peter Ujfalusied29cd52013-11-14 11:35:22 +0200744#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
745
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400746#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
747 SNDRV_PCM_FMTBIT_U8 | \
748 SNDRV_PCM_FMTBIT_S16_LE | \
749 SNDRV_PCM_FMTBIT_U16_LE | \
Daniel Mack21eb24d2012-10-09 09:35:16 +0200750 SNDRV_PCM_FMTBIT_S24_LE | \
751 SNDRV_PCM_FMTBIT_U24_LE | \
752 SNDRV_PCM_FMTBIT_S24_3LE | \
753 SNDRV_PCM_FMTBIT_U24_3LE | \
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400754 SNDRV_PCM_FMTBIT_S32_LE | \
755 SNDRV_PCM_FMTBIT_U32_LE)
756
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000757static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400758 {
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000759 .name = "davinci-mcasp.0",
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400760 .playback = {
761 .channels_min = 2,
Michal Bachraty2952b272013-02-28 16:07:08 +0100762 .channels_max = 32 * 16,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400763 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400764 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400765 },
766 .capture = {
767 .channels_min = 2,
Michal Bachraty2952b272013-02-28 16:07:08 +0100768 .channels_max = 32 * 16,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400769 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400770 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400771 },
772 .ops = &davinci_mcasp_dai_ops,
773
774 },
775 {
Peter Ujfalusi58e48d92013-11-14 11:35:24 +0200776 .name = "davinci-mcasp.1",
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400777 .playback = {
778 .channels_min = 1,
779 .channels_max = 384,
780 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400781 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400782 },
783 .ops = &davinci_mcasp_dai_ops,
784 },
785
786};
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400787
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -0700788static const struct snd_soc_component_driver davinci_mcasp_component = {
789 .name = "davinci-mcasp",
790};
791
Jyri Sarha256ba182013-10-18 18:37:42 +0300792/* Some HW specific values and defaults. The rest is filled in from DT. */
793static struct snd_platform_data dm646x_mcasp_pdata = {
794 .tx_dma_offset = 0x400,
795 .rx_dma_offset = 0x400,
796 .asp_chan_q = EVENTQ_0,
797 .version = MCASP_VERSION_1,
798};
799
800static struct snd_platform_data da830_mcasp_pdata = {
801 .tx_dma_offset = 0x2000,
802 .rx_dma_offset = 0x2000,
803 .asp_chan_q = EVENTQ_0,
804 .version = MCASP_VERSION_2,
805};
806
Peter Ujfalusib14899d2013-11-14 11:35:37 +0200807static struct snd_platform_data am33xx_mcasp_pdata = {
Jyri Sarha256ba182013-10-18 18:37:42 +0300808 .tx_dma_offset = 0,
809 .rx_dma_offset = 0,
810 .asp_chan_q = EVENTQ_0,
811 .version = MCASP_VERSION_3,
812};
813
Peter Ujfalusi453c4992013-11-14 11:35:34 +0200814static struct snd_platform_data dra7_mcasp_pdata = {
815 .tx_dma_offset = 0x200,
816 .rx_dma_offset = 0x284,
817 .asp_chan_q = EVENTQ_0,
818 .version = MCASP_VERSION_4,
819};
820
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530821static const struct of_device_id mcasp_dt_ids[] = {
822 {
823 .compatible = "ti,dm646x-mcasp-audio",
Jyri Sarha256ba182013-10-18 18:37:42 +0300824 .data = &dm646x_mcasp_pdata,
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530825 },
826 {
827 .compatible = "ti,da830-mcasp-audio",
Jyri Sarha256ba182013-10-18 18:37:42 +0300828 .data = &da830_mcasp_pdata,
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530829 },
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530830 {
Jyri Sarha3af9e032013-10-18 18:37:44 +0300831 .compatible = "ti,am33xx-mcasp-audio",
Peter Ujfalusib14899d2013-11-14 11:35:37 +0200832 .data = &am33xx_mcasp_pdata,
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530833 },
Peter Ujfalusi453c4992013-11-14 11:35:34 +0200834 {
835 .compatible = "ti,dra7-mcasp-audio",
836 .data = &dra7_mcasp_pdata,
837 },
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530838 { /* sentinel */ }
839};
840MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
841
Peter Ujfalusiae726e92013-11-14 11:35:35 +0200842static int mcasp_reparent_fck(struct platform_device *pdev)
843{
844 struct device_node *node = pdev->dev.of_node;
845 struct clk *gfclk, *parent_clk;
846 const char *parent_name;
847 int ret;
848
849 if (!node)
850 return 0;
851
852 parent_name = of_get_property(node, "fck_parent", NULL);
853 if (!parent_name)
854 return 0;
855
856 gfclk = clk_get(&pdev->dev, "fck");
857 if (IS_ERR(gfclk)) {
858 dev_err(&pdev->dev, "failed to get fck\n");
859 return PTR_ERR(gfclk);
860 }
861
862 parent_clk = clk_get(NULL, parent_name);
863 if (IS_ERR(parent_clk)) {
864 dev_err(&pdev->dev, "failed to get parent clock\n");
865 ret = PTR_ERR(parent_clk);
866 goto err1;
867 }
868
869 ret = clk_set_parent(gfclk, parent_clk);
870 if (ret) {
871 dev_err(&pdev->dev, "failed to reparent fck\n");
872 goto err2;
873 }
874
875err2:
876 clk_put(parent_clk);
877err1:
878 clk_put(gfclk);
879 return ret;
880}
881
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530882static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
883 struct platform_device *pdev)
884{
885 struct device_node *np = pdev->dev.of_node;
886 struct snd_platform_data *pdata = NULL;
887 const struct of_device_id *match =
Sachin Kamatea421eb2013-05-22 16:53:37 +0530888 of_match_device(mcasp_dt_ids, &pdev->dev);
Jyri Sarha4023fe62013-10-18 18:37:43 +0300889 struct of_phandle_args dma_spec;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530890
891 const u32 *of_serial_dir32;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530892 u32 val;
893 int i, ret = 0;
894
895 if (pdev->dev.platform_data) {
896 pdata = pdev->dev.platform_data;
897 return pdata;
898 } else if (match) {
Jyri Sarha256ba182013-10-18 18:37:42 +0300899 pdata = (struct snd_platform_data *) match->data;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530900 } else {
901 /* control shouldn't reach here. something is wrong */
902 ret = -EINVAL;
903 goto nodata;
904 }
905
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530906 ret = of_property_read_u32(np, "op-mode", &val);
907 if (ret >= 0)
908 pdata->op_mode = val;
909
910 ret = of_property_read_u32(np, "tdm-slots", &val);
Michal Bachraty2952b272013-02-28 16:07:08 +0100911 if (ret >= 0) {
912 if (val < 2 || val > 32) {
913 dev_err(&pdev->dev,
914 "tdm-slots must be in rage [2-32]\n");
915 ret = -EINVAL;
916 goto nodata;
917 }
918
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530919 pdata->tdm_slots = val;
Michal Bachraty2952b272013-02-28 16:07:08 +0100920 }
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530921
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530922 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
923 val /= sizeof(u32);
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530924 if (of_serial_dir32) {
Peter Ujfalusi1427e662013-10-18 18:37:46 +0300925 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
926 (sizeof(*of_serial_dir) * val),
927 GFP_KERNEL);
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530928 if (!of_serial_dir) {
929 ret = -ENOMEM;
930 goto nodata;
931 }
932
Peter Ujfalusi1427e662013-10-18 18:37:46 +0300933 for (i = 0; i < val; i++)
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530934 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
935
Peter Ujfalusi1427e662013-10-18 18:37:46 +0300936 pdata->num_serializer = val;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530937 pdata->serial_dir = of_serial_dir;
938 }
939
Jyri Sarha4023fe62013-10-18 18:37:43 +0300940 ret = of_property_match_string(np, "dma-names", "tx");
941 if (ret < 0)
942 goto nodata;
943
944 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
945 &dma_spec);
946 if (ret < 0)
947 goto nodata;
948
949 pdata->tx_dma_channel = dma_spec.args[0];
950
951 ret = of_property_match_string(np, "dma-names", "rx");
952 if (ret < 0)
953 goto nodata;
954
955 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
956 &dma_spec);
957 if (ret < 0)
958 goto nodata;
959
960 pdata->rx_dma_channel = dma_spec.args[0];
961
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530962 ret = of_property_read_u32(np, "tx-num-evt", &val);
963 if (ret >= 0)
964 pdata->txnumevt = val;
965
966 ret = of_property_read_u32(np, "rx-num-evt", &val);
967 if (ret >= 0)
968 pdata->rxnumevt = val;
969
970 ret = of_property_read_u32(np, "sram-size-playback", &val);
971 if (ret >= 0)
972 pdata->sram_size_playback = val;
973
974 ret = of_property_read_u32(np, "sram-size-capture", &val);
975 if (ret >= 0)
976 pdata->sram_size_capture = val;
977
978 return pdata;
979
980nodata:
981 if (ret < 0) {
982 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
983 ret);
984 pdata = NULL;
985 }
986 return pdata;
987}
988
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400989static int davinci_mcasp_probe(struct platform_device *pdev)
990{
991 struct davinci_pcm_dma_params *dma_data;
Jyri Sarha256ba182013-10-18 18:37:42 +0300992 struct resource *mem, *ioarea, *res, *dat;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400993 struct snd_platform_data *pdata;
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200994 struct davinci_mcasp *mcasp;
Julia Lawall96d31e22011-12-29 17:51:21 +0100995 int ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400996
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530997 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
998 dev_err(&pdev->dev, "No platform data supplied\n");
999 return -EINVAL;
1000 }
1001
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001002 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
Julia Lawall96d31e22011-12-29 17:51:21 +01001003 GFP_KERNEL);
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001004 if (!mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001005 return -ENOMEM;
1006
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301007 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1008 if (!pdata) {
1009 dev_err(&pdev->dev, "no platform data\n");
1010 return -EINVAL;
1011 }
1012
Jyri Sarha256ba182013-10-18 18:37:42 +03001013 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001014 if (!mem) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001015 dev_warn(mcasp->dev,
Jyri Sarha256ba182013-10-18 18:37:42 +03001016 "\"mpu\" mem resource not found, using index 0\n");
1017 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1018 if (!mem) {
1019 dev_err(&pdev->dev, "no mem resource?\n");
1020 return -ENODEV;
1021 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001022 }
1023
Julia Lawall96d31e22011-12-29 17:51:21 +01001024 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
Vaibhav Bediad852f4462011-02-09 18:39:52 +05301025 resource_size(mem), pdev->name);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001026 if (!ioarea) {
1027 dev_err(&pdev->dev, "Audio region already claimed\n");
Julia Lawall96d31e22011-12-29 17:51:21 +01001028 return -EBUSY;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001029 }
1030
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301031 pm_runtime_enable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001032
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301033 ret = pm_runtime_get_sync(&pdev->dev);
1034 if (IS_ERR_VALUE(ret)) {
1035 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1036 return ret;
1037 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001038
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001039 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1040 if (!mcasp->base) {
Vaibhav Bedia4f82f022011-02-09 18:39:54 +05301041 dev_err(&pdev->dev, "ioremap failed\n");
1042 ret = -ENOMEM;
1043 goto err_release_clk;
1044 }
1045
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001046 mcasp->op_mode = pdata->op_mode;
1047 mcasp->tdm_slots = pdata->tdm_slots;
1048 mcasp->num_serializer = pdata->num_serializer;
1049 mcasp->serial_dir = pdata->serial_dir;
1050 mcasp->version = pdata->version;
1051 mcasp->txnumevt = pdata->txnumevt;
1052 mcasp->rxnumevt = pdata->rxnumevt;
Peter Ujfalusi487dce82013-11-14 11:35:31 +02001053
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001054 mcasp->dev = &pdev->dev;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001055
Jyri Sarha256ba182013-10-18 18:37:42 +03001056 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001057 if (dat)
1058 mcasp->dat_port = true;
Jyri Sarha256ba182013-10-18 18:37:42 +03001059
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001060 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
Sekhar Nori48519f02010-07-19 12:31:16 +05301061 dma_data->asp_chan_q = pdata->asp_chan_q;
1062 dma_data->ram_chan_q = pdata->ram_chan_q;
Matt Porterb8ec56d2012-10-17 16:08:03 +02001063 dma_data->sram_pool = pdata->sram_pool;
Ben Gardinera0c83262011-05-18 09:27:45 -04001064 dma_data->sram_size = pdata->sram_size_playback;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001065 if (dat)
1066 dma_data->dma_addr = dat->start;
1067 else
1068 dma_data->dma_addr = mem->start + pdata->tx_dma_offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001069
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001070 /* Unconditional dmaengine stuff */
1071 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = dma_data->dma_addr;
1072
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001073 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
Jyri Sarha4023fe62013-10-18 18:37:43 +03001074 if (res)
1075 dma_data->channel = res->start;
1076 else
1077 dma_data->channel = pdata->tx_dma_channel;
Troy Kisky92e2a6f2009-09-11 14:29:03 -07001078
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001079 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
Sekhar Nori48519f02010-07-19 12:31:16 +05301080 dma_data->asp_chan_q = pdata->asp_chan_q;
1081 dma_data->ram_chan_q = pdata->ram_chan_q;
Matt Porterb8ec56d2012-10-17 16:08:03 +02001082 dma_data->sram_pool = pdata->sram_pool;
Ben Gardinera0c83262011-05-18 09:27:45 -04001083 dma_data->sram_size = pdata->sram_size_capture;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001084 if (dat)
1085 dma_data->dma_addr = dat->start;
1086 else
1087 dma_data->dma_addr = mem->start + pdata->rx_dma_offset;
1088
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001089 /* Unconditional dmaengine stuff */
1090 mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = dma_data->dma_addr;
1091
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001092 if (mcasp->version < MCASP_VERSION_3) {
1093 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1094 /* dma_data->dma_addr is pointing to the data port address */
1095 mcasp->dat_port = true;
1096 } else {
1097 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1098 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001099
1100 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
Jyri Sarha4023fe62013-10-18 18:37:43 +03001101 if (res)
1102 dma_data->channel = res->start;
1103 else
1104 dma_data->channel = pdata->rx_dma_channel;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001105
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001106 /* Unconditional dmaengine stuff */
1107 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = "tx";
1108 mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].filter_data = "rx";
1109
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001110 dev_set_drvdata(&pdev->dev, mcasp);
Peter Ujfalusiae726e92013-11-14 11:35:35 +02001111
1112 mcasp_reparent_fck(pdev);
1113
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001114 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1115 &davinci_mcasp_dai[pdata->op_mode], 1);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001116
1117 if (ret != 0)
Julia Lawall96d31e22011-12-29 17:51:21 +01001118 goto err_release_clk;
Hebbar, Gururajaf08095a2012-08-27 18:56:39 +05301119
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001120 if (mcasp->version != MCASP_VERSION_4) {
1121 ret = davinci_soc_platform_register(&pdev->dev);
1122 if (ret) {
1123 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1124 goto err_unregister_component;
1125 }
Hebbar, Gururajaf08095a2012-08-27 18:56:39 +05301126 }
1127
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001128 return 0;
1129
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001130err_unregister_component:
1131 snd_soc_unregister_component(&pdev->dev);
Vaibhav Bediaeef6d7b2011-02-09 18:39:53 +05301132err_release_clk:
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301133 pm_runtime_put_sync(&pdev->dev);
1134 pm_runtime_disable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001135 return ret;
1136}
1137
1138static int davinci_mcasp_remove(struct platform_device *pdev)
1139{
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001140 struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001141
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001142 snd_soc_unregister_component(&pdev->dev);
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001143 if (mcasp->version != MCASP_VERSION_4)
1144 davinci_soc_platform_unregister(&pdev->dev);
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301145
1146 pm_runtime_put_sync(&pdev->dev);
1147 pm_runtime_disable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001148
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001149 return 0;
1150}
1151
Daniel Macka85e4192013-10-01 14:50:02 +02001152#ifdef CONFIG_PM_SLEEP
1153static int davinci_mcasp_suspend(struct device *dev)
1154{
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001155 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
Daniel Macka85e4192013-10-01 14:50:02 +02001156
Peter Ujfalusif68205a2013-11-14 11:35:36 +02001157 mcasp->context.txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
1158 mcasp->context.rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
1159 mcasp->context.txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
1160 mcasp->context.rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
1161 mcasp->context.aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
1162 mcasp->context.aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
1163 mcasp->context.pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
Daniel Macka85e4192013-10-01 14:50:02 +02001164
1165 return 0;
1166}
1167
1168static int davinci_mcasp_resume(struct device *dev)
1169{
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001170 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
Daniel Macka85e4192013-10-01 14:50:02 +02001171
Peter Ujfalusif68205a2013-11-14 11:35:36 +02001172 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl);
1173 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl);
1174 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt);
1175 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt);
1176 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl);
1177 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl);
1178 mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
Daniel Macka85e4192013-10-01 14:50:02 +02001179
1180 return 0;
1181}
1182#endif
1183
1184SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops,
1185 davinci_mcasp_suspend,
1186 davinci_mcasp_resume);
1187
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001188static struct platform_driver davinci_mcasp_driver = {
1189 .probe = davinci_mcasp_probe,
1190 .remove = davinci_mcasp_remove,
1191 .driver = {
1192 .name = "davinci-mcasp",
1193 .owner = THIS_MODULE,
Daniel Macka85e4192013-10-01 14:50:02 +02001194 .pm = &davinci_mcasp_pm_ops,
Sachin Kamatea421eb2013-05-22 16:53:37 +05301195 .of_match_table = mcasp_dt_ids,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001196 },
1197};
1198
Axel Linf9b8a512011-11-25 10:09:27 +08001199module_platform_driver(davinci_mcasp_driver);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001200
1201MODULE_AUTHOR("Steve Chen");
1202MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1203MODULE_LICENSE("GPL");