Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 1 | /* |
| 2 | * CXL Flash Device Driver |
| 3 | * |
| 4 | * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation |
| 5 | * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation |
| 6 | * |
| 7 | * Copyright (C) 2015 IBM Corporation |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation; either version |
| 12 | * 2 of the License, or (at your option) any later version. |
| 13 | */ |
| 14 | |
| 15 | #ifndef _CXLFLASH_MAIN_H |
| 16 | #define _CXLFLASH_MAIN_H |
| 17 | |
| 18 | #include <linux/list.h> |
| 19 | #include <linux/types.h> |
| 20 | #include <scsi/scsi.h> |
| 21 | #include <scsi/scsi_device.h> |
| 22 | |
| 23 | #define CXLFLASH_NAME "cxlflash" |
| 24 | #define CXLFLASH_ADAPTER_NAME "IBM POWER CXL Flash Adapter" |
Uma Krishnan | a834a36 | 2017-06-21 21:15:18 -0500 | [diff] [blame] | 25 | #define CXLFLASH_MAX_ADAPTERS 32 |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 26 | |
Manoj Kumar | a2746fb | 2015-12-14 15:07:43 -0600 | [diff] [blame] | 27 | #define PCI_DEVICE_ID_IBM_CORSA 0x04F0 |
| 28 | #define PCI_DEVICE_ID_IBM_FLASH_GT 0x0600 |
Matthew R. Ochs | 9434452 | 2017-02-16 21:39:32 -0600 | [diff] [blame] | 29 | #define PCI_DEVICE_ID_IBM_BRIARD 0x0624 |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 30 | |
| 31 | /* Since there is only one target, make it 0 */ |
| 32 | #define CXLFLASH_TARGET 0 |
| 33 | #define CXLFLASH_MAX_CDB_LEN 16 |
| 34 | |
| 35 | /* Really only one target per bus since the Texan is directly attached */ |
| 36 | #define CXLFLASH_MAX_NUM_TARGETS_PER_BUS 1 |
| 37 | #define CXLFLASH_MAX_NUM_LUNS_PER_TARGET 65536 |
| 38 | |
| 39 | #define CXLFLASH_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ) |
| 40 | |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 41 | /* FC defines */ |
| 42 | #define FC_MTIP_CMDCONFIG 0x010 |
| 43 | #define FC_MTIP_STATUS 0x018 |
Matthew R. Ochs | 9cf43a3 | 2017-06-21 21:16:13 -0500 | [diff] [blame] | 44 | #define FC_MAX_NUM_LUNS 0x080 /* Max LUNs host can provision for port */ |
| 45 | #define FC_CUR_NUM_LUNS 0x088 /* Cur number LUNs provisioned for port */ |
| 46 | #define FC_MAX_CAP_PORT 0x090 /* Max capacity all LUNs for port (4K blocks) */ |
| 47 | #define FC_CUR_CAP_PORT 0x098 /* Cur capacity all LUNs for port (4K blocks) */ |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 48 | |
| 49 | #define FC_PNAME 0x300 |
| 50 | #define FC_CONFIG 0x320 |
| 51 | #define FC_CONFIG2 0x328 |
| 52 | #define FC_STATUS 0x330 |
| 53 | #define FC_ERROR 0x380 |
| 54 | #define FC_ERRCAP 0x388 |
| 55 | #define FC_ERRMSK 0x390 |
| 56 | #define FC_CNT_CRCERR 0x538 |
| 57 | #define FC_CRC_THRESH 0x580 |
| 58 | |
| 59 | #define FC_MTIP_CMDCONFIG_ONLINE 0x20ULL |
| 60 | #define FC_MTIP_CMDCONFIG_OFFLINE 0x40ULL |
| 61 | |
| 62 | #define FC_MTIP_STATUS_MASK 0x30ULL |
| 63 | #define FC_MTIP_STATUS_ONLINE 0x20ULL |
| 64 | #define FC_MTIP_STATUS_OFFLINE 0x10ULL |
| 65 | |
| 66 | /* TIMEOUT and RETRY definitions */ |
| 67 | |
| 68 | /* AFU command timeout values */ |
| 69 | #define MC_AFU_SYNC_TIMEOUT 5 /* 5 secs */ |
Matthew R. Ochs | 9cf43a3 | 2017-06-21 21:16:13 -0500 | [diff] [blame] | 70 | #define MC_LUN_PROV_TIMEOUT 5 /* 5 secs */ |
Matthew R. Ochs | bc88ac4 | 2017-06-21 21:16:22 -0500 | [diff] [blame] | 71 | #define MC_AFU_DEBUG_TIMEOUT 5 /* 5 secs */ |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 72 | |
| 73 | /* AFU command room retry limit */ |
| 74 | #define MC_ROOM_RETRY_CNT 10 |
| 75 | |
| 76 | /* FC CRC clear periodic timer */ |
| 77 | #define MC_CRC_THRESH 100 /* threshold in 5 mins */ |
| 78 | |
| 79 | #define FC_PORT_STATUS_RETRY_CNT 100 /* 100 100ms retries = 10 seconds */ |
| 80 | #define FC_PORT_STATUS_RETRY_INTERVAL_US 100000 /* microseconds */ |
| 81 | |
| 82 | /* VPD defines */ |
| 83 | #define CXLFLASH_VPD_LEN 256 |
| 84 | #define WWPN_LEN 16 |
| 85 | #define WWPN_BUF_LEN (WWPN_LEN + 1) |
| 86 | |
| 87 | enum undo_level { |
Manoj N. Kumar | 9526f36 | 2016-03-25 14:26:34 -0500 | [diff] [blame] | 88 | UNDO_NOOP = 0, |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 89 | FREE_IRQ, |
| 90 | UNMAP_ONE, |
| 91 | UNMAP_TWO, |
Manoj N. Kumar | 9526f36 | 2016-03-25 14:26:34 -0500 | [diff] [blame] | 92 | UNMAP_THREE |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 93 | }; |
| 94 | |
| 95 | struct dev_dependent_vals { |
| 96 | u64 max_sectors; |
Uma Krishnan | 96e1b66 | 2016-06-15 18:49:38 -0500 | [diff] [blame] | 97 | u64 flags; |
Matthew R. Ochs | 0d41913 | 2017-10-25 16:36:20 -0500 | [diff] [blame] | 98 | #define CXLFLASH_NOTIFY_SHUTDOWN 0x0000000000000001ULL |
| 99 | #define CXLFLASH_WWPN_VPD_REQUIRED 0x0000000000000002ULL |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 100 | }; |
| 101 | |
| 102 | struct asyc_intr_info { |
| 103 | u64 status; |
| 104 | char *desc; |
| 105 | u8 port; |
| 106 | u8 action; |
| 107 | #define CLR_FC_ERROR 0x01 |
| 108 | #define LINK_RESET 0x02 |
Matthew R. Ochs | ef51074 | 2015-10-21 15:13:37 -0500 | [diff] [blame] | 109 | #define SCAN_HOST 0x04 |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 110 | }; |
| 111 | |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 112 | #endif /* _CXLFLASH_MAIN_H */ |