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Maxime Chevallierdb9d7d32018-05-31 10:07:43 +02001/*
2 * Definitions for Marvell PPv2 network controller for Armada 375 SoC.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Marcin Wojtas <mw@semihalf.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12#ifndef _MVPP2_H_
13#define _MVPP2_H_
14
Antoine Tenartb32b0882018-07-09 17:00:43 +020015#include <linux/interrupt.h>
Maxime Chevallierdb9d7d32018-05-31 10:07:43 +020016#include <linux/kernel.h>
17#include <linux/netdevice.h>
18#include <linux/phy.h>
19#include <linux/phylink.h>
20
21/* Fifo Registers */
22#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
23#define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
24#define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
25#define MVPP2_RX_FIFO_INIT_REG 0x64
26#define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))
27#define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
28
29/* RX DMA Top Registers */
30#define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
31#define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
32#define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
33#define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
34#define MVPP2_POOL_BUF_SIZE_OFFSET 5
35#define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
36#define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
37#define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
38#define MVPP2_RXQ_POOL_SHORT_OFFS 20
39#define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
40#define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
41#define MVPP2_RXQ_POOL_LONG_OFFS 24
42#define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
43#define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
44#define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
45#define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
46#define MVPP2_RXQ_DISABLE_MASK BIT(31)
47
48/* Top Registers */
49#define MVPP2_MH_REG(port) (0x5040 + 4 * (port))
50#define MVPP2_DSA_EXTENDED BIT(5)
51
52/* Parser Registers */
53#define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
54#define MVPP2_PRS_PORT_LU_MAX 0xf
55#define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
56#define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
57#define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
58#define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
59#define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
60#define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
61#define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
62#define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
63#define MVPP2_PRS_TCAM_IDX_REG 0x1100
64#define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
65#define MVPP2_PRS_TCAM_INV_MASK BIT(31)
66#define MVPP2_PRS_SRAM_IDX_REG 0x1200
67#define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
68#define MVPP2_PRS_TCAM_CTRL_REG 0x1230
69#define MVPP2_PRS_TCAM_EN_MASK BIT(0)
70
71/* RSS Registers */
72#define MVPP22_RSS_INDEX 0x1500
73#define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) (idx)
74#define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8)
75#define MVPP22_RSS_INDEX_QUEUE(idx) ((idx) << 16)
76#define MVPP22_RSS_TABLE_ENTRY 0x1508
77#define MVPP22_RSS_TABLE 0x1510
78#define MVPP22_RSS_TABLE_POINTER(p) (p)
79#define MVPP22_RSS_WIDTH 0x150c
80
81/* Classifier Registers */
82#define MVPP2_CLS_MODE_REG 0x1800
83#define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
84#define MVPP2_CLS_PORT_WAY_REG 0x1810
85#define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
86#define MVPP2_CLS_LKP_INDEX_REG 0x1814
87#define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
88#define MVPP2_CLS_LKP_TBL_REG 0x1818
89#define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
90#define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
91#define MVPP2_CLS_FLOW_INDEX_REG 0x1820
92#define MVPP2_CLS_FLOW_TBL0_REG 0x1824
93#define MVPP2_CLS_FLOW_TBL1_REG 0x1828
94#define MVPP2_CLS_FLOW_TBL2_REG 0x182c
95#define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
96#define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
97#define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
98#define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
99#define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
100#define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
101
102/* Descriptor Manager Top Registers */
103#define MVPP2_RXQ_NUM_REG 0x2040
104#define MVPP2_RXQ_DESC_ADDR_REG 0x2044
105#define MVPP22_DESC_ADDR_OFFS 8
106#define MVPP2_RXQ_DESC_SIZE_REG 0x2048
107#define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
108#define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
109#define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
110#define MVPP2_RXQ_NUM_NEW_OFFSET 16
111#define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
112#define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
113#define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
114#define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
115#define MVPP2_RXQ_THRESH_REG 0x204c
116#define MVPP2_OCCUPIED_THRESH_OFFSET 0
117#define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
118#define MVPP2_RXQ_INDEX_REG 0x2050
119#define MVPP2_TXQ_NUM_REG 0x2080
120#define MVPP2_TXQ_DESC_ADDR_REG 0x2084
121#define MVPP2_TXQ_DESC_SIZE_REG 0x2088
122#define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
123#define MVPP2_TXQ_THRESH_REG 0x2094
124#define MVPP2_TXQ_THRESH_OFFSET 16
125#define MVPP2_TXQ_THRESH_MASK 0x3fff
126#define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
127#define MVPP2_TXQ_INDEX_REG 0x2098
128#define MVPP2_TXQ_PREF_BUF_REG 0x209c
129#define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
130#define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
131#define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
132#define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
133#define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
134#define MVPP2_TXQ_PENDING_REG 0x20a0
135#define MVPP2_TXQ_PENDING_MASK 0x3fff
136#define MVPP2_TXQ_INT_STATUS_REG 0x20a4
137#define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
138#define MVPP2_TRANSMITTED_COUNT_OFFSET 16
139#define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
140#define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
141#define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
142#define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
143#define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
144#define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
145#define MVPP2_TXQ_RSVD_CLR_OFFSET 16
146#define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
147#define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
148#define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
149#define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
150#define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
151#define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
152#define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
153
154/* MBUS bridge registers */
155#define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
156#define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
157#define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
158#define MVPP2_BASE_ADDR_ENABLE 0x4060
159
160/* AXI Bridge Registers */
161#define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
162#define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
163#define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
164#define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
165#define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
166#define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
167#define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
168#define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
169#define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
170#define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
171#define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
172#define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
173
174/* Values for AXI Bridge registers */
175#define MVPP22_AXI_ATTR_CACHE_OFFS 0
176#define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
177
178#define MVPP22_AXI_CODE_CACHE_OFFS 0
179#define MVPP22_AXI_CODE_DOMAIN_OFFS 4
180
181#define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
182#define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
183#define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
184
185#define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
186#define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
187
188/* Interrupt Cause and Mask registers */
189#define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port))
190#define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0
191
192#define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
193#define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0
194#define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port))
195
196#define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
197#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
198#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
199#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
200
201#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
202#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
203
204#define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
205#define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
206#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
207#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
208
209#define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
210#define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
211#define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
212#define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
213#define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
214#define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
215#define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16
216#define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
217#define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
218#define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
219#define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
220#define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
221#define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
222#define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
223#define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
224#define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
225#define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
226#define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
227#define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
228
229/* Buffer Manager registers */
230#define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
231#define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
232#define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
233#define MVPP2_BM_POOL_SIZE_MASK 0xfff0
234#define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
235#define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
236#define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
237#define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
238#define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
239#define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
240#define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
241#define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8
242#define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
243#define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
244#define MVPP2_BM_START_MASK BIT(0)
245#define MVPP2_BM_STOP_MASK BIT(1)
246#define MVPP2_BM_STATE_MASK BIT(4)
247#define MVPP2_BM_LOW_THRESH_OFFS 8
248#define MVPP2_BM_LOW_THRESH_MASK 0x7f00
249#define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
250 MVPP2_BM_LOW_THRESH_OFFS)
251#define MVPP2_BM_HIGH_THRESH_OFFS 16
252#define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
253#define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
254 MVPP2_BM_HIGH_THRESH_OFFS)
255#define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
256#define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
257#define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
258#define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
259#define MVPP2_BM_BPPE_FULL_MASK BIT(3)
260#define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
261#define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
262#define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
263#define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
264#define MVPP2_BM_VIRT_ALLOC_REG 0x6440
265#define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444
266#define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff
267#define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00
268#define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8
269#define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
270#define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
271#define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
272#define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
273#define MVPP2_BM_VIRT_RLS_REG 0x64c0
274#define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
275#define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
276#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
277#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
278
279/* TX Scheduler registers */
280#define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
281#define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
282#define MVPP2_TXP_SCHED_ENQ_MASK 0xff
283#define MVPP2_TXP_SCHED_DISQ_OFFSET 8
284#define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
285#define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
286#define MVPP2_TXP_SCHED_MTU_REG 0x801c
287#define MVPP2_TXP_MTU_MAX 0x7FFFF
288#define MVPP2_TXP_SCHED_REFILL_REG 0x8020
289#define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
290#define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
291#define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
292#define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
293#define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
294#define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
295#define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
296#define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
297#define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
298#define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
299#define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
300#define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
301#define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
302
303/* TX general registers */
304#define MVPP2_TX_SNOOP_REG 0x8800
305#define MVPP2_TX_PORT_FLUSH_REG 0x8810
306#define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
307
308/* LMS registers */
309#define MVPP2_SRC_ADDR_MIDDLE 0x24
310#define MVPP2_SRC_ADDR_HIGH 0x28
311#define MVPP2_PHY_AN_CFG0_REG 0x34
312#define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
313#define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
314#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
315
316/* Per-port registers */
317#define MVPP2_GMAC_CTRL_0_REG 0x0
318#define MVPP2_GMAC_PORT_EN_MASK BIT(0)
319#define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
320#define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
321#define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
322#define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
323#define MVPP2_GMAC_CTRL_1_REG 0x4
324#define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
325#define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
326#define MVPP2_GMAC_PCS_LB_EN_BIT 6
327#define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
328#define MVPP2_GMAC_SA_LOW_OFFS 7
329#define MVPP2_GMAC_CTRL_2_REG 0x8
330#define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
331#define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1)
332#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
333#define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4)
334#define MVPP2_GMAC_DISABLE_PADDING BIT(5)
335#define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
336#define MVPP2_GMAC_AUTONEG_CONFIG 0xc
337#define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
338#define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
339#define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2)
340#define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3)
341#define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4)
342#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
343#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
344#define MVPP2_GMAC_AN_SPEED_EN BIT(7)
345#define MVPP2_GMAC_FC_ADV_EN BIT(9)
346#define MVPP2_GMAC_FC_ADV_ASM_EN BIT(10)
347#define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11)
348#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
349#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
350#define MVPP2_GMAC_STATUS0 0x10
351#define MVPP2_GMAC_STATUS0_LINK_UP BIT(0)
352#define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1)
353#define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2)
354#define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3)
355#define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(6)
356#define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(7)
357#define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11)
358#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
359#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
360#define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
361#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
362 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
363#define MVPP22_GMAC_INT_STAT 0x20
364#define MVPP22_GMAC_INT_STAT_LINK BIT(1)
365#define MVPP22_GMAC_INT_MASK 0x24
366#define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1)
367#define MVPP22_GMAC_CTRL_4_REG 0x90
368#define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0)
369#define MVPP22_CTRL4_RX_FC_EN BIT(3)
370#define MVPP22_CTRL4_TX_FC_EN BIT(4)
371#define MVPP22_CTRL4_DP_CLK_SEL BIT(5)
372#define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6)
373#define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7)
374#define MVPP22_GMAC_INT_SUM_MASK 0xa4
375#define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
376
377/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
378 * relative to port->base.
379 */
380#define MVPP22_XLG_CTRL0_REG 0x100
381#define MVPP22_XLG_CTRL0_PORT_EN BIT(0)
382#define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1)
383#define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7)
384#define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8)
385#define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14)
386#define MVPP22_XLG_CTRL1_REG 0x104
387#define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0
388#define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff
389#define MVPP22_XLG_STATUS 0x10c
390#define MVPP22_XLG_STATUS_LINK_UP BIT(0)
391#define MVPP22_XLG_INT_STAT 0x114
392#define MVPP22_XLG_INT_STAT_LINK BIT(1)
393#define MVPP22_XLG_INT_MASK 0x118
394#define MVPP22_XLG_INT_MASK_LINK BIT(1)
395#define MVPP22_XLG_CTRL3_REG 0x11c
396#define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
397#define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
398#define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13)
399#define MVPP22_XLG_EXT_INT_MASK 0x15c
400#define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1)
401#define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2)
402#define MVPP22_XLG_CTRL4_REG 0x184
403#define MVPP22_XLG_CTRL4_FWD_FC BIT(5)
404#define MVPP22_XLG_CTRL4_FWD_PFC BIT(6)
405#define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12)
406#define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14)
407
408/* SMI registers. PPv2.2 only, relative to priv->iface_base. */
409#define MVPP22_SMI_MISC_CFG_REG 0x1204
410#define MVPP22_SMI_POLLING_EN BIT(10)
411
412#define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00)
413
414#define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
415
416/* Descriptor ring Macros */
417#define MVPP2_QUEUE_NEXT_DESC(q, index) \
418 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
419
420/* XPCS registers. PPv2.2 only */
421#define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000)
422#define MVPP22_MPCS_CTRL 0x14
423#define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10)
424#define MVPP22_MPCS_CLK_RESET 0x14c
425#define MAC_CLK_RESET_SD_TX BIT(0)
426#define MAC_CLK_RESET_SD_RX BIT(1)
427#define MAC_CLK_RESET_MAC BIT(2)
428#define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4)
429#define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11)
430
431/* XPCS registers. PPv2.2 only */
432#define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
433#define MVPP22_XPCS_CFG0 0x0
434#define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3)
435#define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5)
436
437/* System controller registers. Accessed through a regmap. */
438#define GENCONF_SOFT_RESET1 0x1108
439#define GENCONF_SOFT_RESET1_GOP BIT(6)
440#define GENCONF_PORT_CTRL0 0x1110
441#define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1)
442#define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29)
443#define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31)
444#define GENCONF_PORT_CTRL1 0x1114
445#define GENCONF_PORT_CTRL1_EN(p) BIT(p)
446#define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28)
447#define GENCONF_CTRL0 0x1120
448#define GENCONF_CTRL0_PORT0_RGMII BIT(0)
449#define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1)
450#define GENCONF_CTRL0_PORT1_RGMII BIT(2)
451
452/* Various constants */
453
454/* Coalescing */
455#define MVPP2_TXDONE_COAL_PKTS_THRESH 64
456#define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
457#define MVPP2_TXDONE_COAL_USEC 1000
458#define MVPP2_RX_COAL_PKTS 32
459#define MVPP2_RX_COAL_USEC 64
460
461/* The two bytes Marvell header. Either contains a special value used
462 * by Marvell switches when a specific hardware mode is enabled (not
463 * supported by this driver) or is filled automatically by zeroes on
464 * the RX side. Those two bytes being at the front of the Ethernet
465 * header, they allow to have the IP header aligned on a 4 bytes
466 * boundary automatically: the hardware skips those two bytes on its
467 * own.
468 */
469#define MVPP2_MH_SIZE 2
470#define MVPP2_ETH_TYPE_LEN 2
471#define MVPP2_PPPOE_HDR_SIZE 8
472#define MVPP2_VLAN_TAG_LEN 4
473#define MVPP2_VLAN_TAG_EDSA_LEN 8
474
475/* Lbtd 802.3 type */
476#define MVPP2_IP_LBDT_TYPE 0xfffa
477
478#define MVPP2_TX_CSUM_MAX_SIZE 9800
479
480/* Timeout constants */
481#define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
482#define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
483
484#define MVPP2_TX_MTU_MAX 0x7ffff
485
486/* Maximum number of T-CONTs of PON port */
487#define MVPP2_MAX_TCONT 16
488
489/* Maximum number of supported ports */
490#define MVPP2_MAX_PORTS 4
491
492/* Maximum number of TXQs used by single port */
493#define MVPP2_MAX_TXQ 8
494
495/* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO
496 * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data),
497 * multiply this value by two to count the maximum number of skb descs needed.
498 */
499#define MVPP2_MAX_TSO_SEGS 300
500#define MVPP2_MAX_SKB_DESCS (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
501
502/* Dfault number of RXQs in use */
503#define MVPP2_DEFAULT_RXQ 4
504
505/* Max number of Rx descriptors */
506#define MVPP2_MAX_RXD_MAX 1024
507#define MVPP2_MAX_RXD_DFLT 128
508
509/* Max number of Tx descriptors */
510#define MVPP2_MAX_TXD_MAX 2048
511#define MVPP2_MAX_TXD_DFLT 1024
512
513/* Amount of Tx descriptors that can be reserved at once by CPU */
514#define MVPP2_CPU_DESC_CHUNK 64
515
516/* Max number of Tx descriptors in each aggregated queue */
517#define MVPP2_AGGR_TXQ_SIZE 256
518
519/* Descriptor aligned size */
520#define MVPP2_DESC_ALIGNED_SIZE 32
521
522/* Descriptor alignment mask */
523#define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
524
525/* RX FIFO constants */
526#define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000
527#define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000
528#define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000
529#define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200
530#define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80
531#define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40
532#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
533
534/* TX FIFO constants */
535#define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa
536#define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3
537#define MVPP2_TX_FIFO_THRESHOLD_MIN 256
538#define MVPP2_TX_FIFO_THRESHOLD_10KB \
539 (MVPP22_TX_FIFO_DATA_SIZE_10KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
540#define MVPP2_TX_FIFO_THRESHOLD_3KB \
541 (MVPP22_TX_FIFO_DATA_SIZE_3KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
542
543/* RX buffer constants */
544#define MVPP2_SKB_SHINFO_SIZE \
545 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
546
547#define MVPP2_RX_PKT_SIZE(mtu) \
548 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
549 ETH_HLEN + ETH_FCS_LEN, cache_line_size())
550
551#define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
552#define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
553#define MVPP2_RX_MAX_PKT_SIZE(total_size) \
554 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
555
556#define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
Maxime Chevallierbd43d1b2018-06-28 14:42:05 +0200557#define MVPP2_BIT_TO_WORD(bit) ((bit) / 32)
558#define MVPP2_BIT_IN_WORD(bit) ((bit) % 32)
Maxime Chevallierdb9d7d32018-05-31 10:07:43 +0200559
Maxime Chevallier0ad2f532018-07-12 13:54:11 +0200560/* RSS constants */
561#define MVPP22_RSS_TABLE_ENTRIES 32
562
Maxime Chevallierdb9d7d32018-05-31 10:07:43 +0200563/* IPv6 max L3 address size */
564#define MVPP2_MAX_L3_ADDR_SIZE 16
565
566/* Port flags */
567#define MVPP2_F_LOOPBACK BIT(0)
568
569/* Marvell tag types */
570enum mvpp2_tag_type {
571 MVPP2_TAG_TYPE_NONE = 0,
572 MVPP2_TAG_TYPE_MH = 1,
573 MVPP2_TAG_TYPE_DSA = 2,
574 MVPP2_TAG_TYPE_EDSA = 3,
575 MVPP2_TAG_TYPE_VLAN = 4,
576 MVPP2_TAG_TYPE_LAST = 5
577};
578
579/* L2 cast enum */
580enum mvpp2_prs_l2_cast {
581 MVPP2_PRS_L2_UNI_CAST,
582 MVPP2_PRS_L2_MULTI_CAST,
583};
584
585/* L3 cast enum */
586enum mvpp2_prs_l3_cast {
587 MVPP2_PRS_L3_UNI_CAST,
588 MVPP2_PRS_L3_MULTI_CAST,
589 MVPP2_PRS_L3_BROAD_CAST
590};
591
592/* BM constants */
593#define MVPP2_BM_JUMBO_BUF_NUM 512
594#define MVPP2_BM_LONG_BUF_NUM 1024
595#define MVPP2_BM_SHORT_BUF_NUM 2048
596#define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
597#define MVPP2_BM_POOL_PTR_ALIGN 128
598
599/* BM cookie (32 bits) definition */
600#define MVPP2_BM_COOKIE_POOL_OFFS 8
601#define MVPP2_BM_COOKIE_CPU_OFFS 24
602
603#define MVPP2_BM_SHORT_FRAME_SIZE 512
604#define MVPP2_BM_LONG_FRAME_SIZE 2048
605#define MVPP2_BM_JUMBO_FRAME_SIZE 10240
606/* BM short pool packet size
607 * These value assure that for SWF the total number
608 * of bytes allocated for each buffer will be 512
609 */
610#define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_SHORT_FRAME_SIZE)
611#define MVPP2_BM_LONG_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_LONG_FRAME_SIZE)
612#define MVPP2_BM_JUMBO_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_JUMBO_FRAME_SIZE)
613
614#define MVPP21_ADDR_SPACE_SZ 0
615#define MVPP22_ADDR_SPACE_SZ SZ_64K
616
617#define MVPP2_MAX_THREADS 8
618#define MVPP2_MAX_QVECS MVPP2_MAX_THREADS
619
620/* GMAC MIB Counters register definitions */
621#define MVPP21_MIB_COUNTERS_OFFSET 0x1000
622#define MVPP21_MIB_COUNTERS_PORT_SZ 0x400
623#define MVPP22_MIB_COUNTERS_OFFSET 0x0
624#define MVPP22_MIB_COUNTERS_PORT_SZ 0x100
625
626#define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0
627#define MVPP2_MIB_BAD_OCTETS_RCVD 0x8
628#define MVPP2_MIB_CRC_ERRORS_SENT 0xc
629#define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10
630#define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18
631#define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c
632#define MVPP2_MIB_FRAMES_64_OCTETS 0x20
633#define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24
634#define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28
635#define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c
636#define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30
637#define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
638#define MVPP2_MIB_GOOD_OCTETS_SENT 0x38
639#define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40
640#define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48
641#define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c
642#define MVPP2_MIB_FC_SENT 0x54
643#define MVPP2_MIB_FC_RCVD 0x58
644#define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c
645#define MVPP2_MIB_UNDERSIZE_RCVD 0x60
646#define MVPP2_MIB_FRAGMENTS_RCVD 0x64
647#define MVPP2_MIB_OVERSIZE_RCVD 0x68
648#define MVPP2_MIB_JABBER_RCVD 0x6c
649#define MVPP2_MIB_MAC_RCV_ERROR 0x70
650#define MVPP2_MIB_BAD_CRC_EVENT 0x74
651#define MVPP2_MIB_COLLISION 0x78
652#define MVPP2_MIB_LATE_COLLISION 0x7c
653
654#define MVPP2_MIB_COUNTERS_STATS_DELAY (1 * HZ)
655
656#define MVPP2_DESC_DMA_MASK DMA_BIT_MASK(40)
657
658/* Definitions */
659
660/* Shared Packet Processor resources */
661struct mvpp2 {
662 /* Shared registers' base addresses */
663 void __iomem *lms_base;
664 void __iomem *iface_base;
665
666 /* On PPv2.2, each "software thread" can access the base
667 * register through a separate address space, each 64 KB apart
668 * from each other. Typically, such address spaces will be
669 * used per CPU.
670 */
671 void __iomem *swth_base[MVPP2_MAX_THREADS];
672
673 /* On PPv2.2, some port control registers are located into the system
674 * controller space. These registers are accessible through a regmap.
675 */
676 struct regmap *sysctrl_base;
677
678 /* Common clocks */
679 struct clk *pp_clk;
680 struct clk *gop_clk;
681 struct clk *mg_clk;
682 struct clk *mg_core_clk;
683 struct clk *axi_clk;
684
685 /* List of pointers to port structures */
686 int port_count;
687 struct mvpp2_port *port_list[MVPP2_MAX_PORTS];
688
689 /* Aggregated TXQs */
690 struct mvpp2_tx_queue *aggr_txqs;
691
692 /* BM pools */
693 struct mvpp2_bm_pool *bm_pools;
694
695 /* PRS shadow table */
696 struct mvpp2_prs_shadow *prs_shadow;
697 /* PRS auxiliary table for double vlan entries control */
698 bool *prs_double_vlans;
699
700 /* Tclk value */
701 u32 tclk;
702
703 /* HW version */
704 enum { MVPP21, MVPP22 } hw_version;
705
706 /* Maximum number of RXQs per port */
707 unsigned int max_port_rxqs;
708
709 /* Workqueue to gather hardware statistics */
710 char queue_name[30];
711 struct workqueue_struct *stats_queue;
712};
713
714struct mvpp2_pcpu_stats {
715 struct u64_stats_sync syncp;
716 u64 rx_packets;
717 u64 rx_bytes;
718 u64 tx_packets;
719 u64 tx_bytes;
720};
721
722/* Per-CPU port control */
723struct mvpp2_port_pcpu {
724 struct hrtimer tx_done_timer;
725 bool timer_scheduled;
726 /* Tasklet for egress finalization */
727 struct tasklet_struct tx_done_tasklet;
728};
729
730struct mvpp2_queue_vector {
731 int irq;
732 struct napi_struct napi;
733 enum { MVPP2_QUEUE_VECTOR_SHARED, MVPP2_QUEUE_VECTOR_PRIVATE } type;
734 int sw_thread_id;
735 u16 sw_thread_mask;
736 int first_rxq;
737 int nrxqs;
738 u32 pending_cause_rx;
739 struct mvpp2_port *port;
740};
741
742struct mvpp2_port {
743 u8 id;
744
745 /* Index of the port from the "group of ports" complex point
746 * of view
747 */
748 int gop_id;
749
750 int link_irq;
751
752 struct mvpp2 *priv;
753
754 /* Firmware node associated to the port */
755 struct fwnode_handle *fwnode;
756
757 /* Is a PHY always connected to the port */
758 bool has_phy;
759
760 /* Per-port registers' base address */
761 void __iomem *base;
762 void __iomem *stats_base;
763
764 struct mvpp2_rx_queue **rxqs;
765 unsigned int nrxqs;
766 struct mvpp2_tx_queue **txqs;
767 unsigned int ntxqs;
768 struct net_device *dev;
769
770 int pkt_size;
771
772 /* Per-CPU port control */
773 struct mvpp2_port_pcpu __percpu *pcpu;
774
775 /* Flags */
776 unsigned long flags;
777
778 u16 tx_ring_size;
779 u16 rx_ring_size;
780 struct mvpp2_pcpu_stats __percpu *stats;
781 u64 *ethtool_stats;
782
783 /* Per-port work and its lock to gather hardware statistics */
784 struct mutex gather_stats_lock;
785 struct delayed_work stats_work;
786
787 struct device_node *of_node;
788
789 phy_interface_t phy_interface;
790 struct phylink *phylink;
791 struct phy *comphy;
792
793 struct mvpp2_bm_pool *pool_long;
794 struct mvpp2_bm_pool *pool_short;
795
796 /* Index of first port's physical RXQ */
797 u8 first_rxq;
798
799 struct mvpp2_queue_vector qvecs[MVPP2_MAX_QVECS];
800 unsigned int nqvecs;
801 bool has_tx_irqs;
802
803 u32 tx_time_coal;
804};
805
806/* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
807 * layout of the transmit and reception DMA descriptors, and their
808 * layout is therefore defined by the hardware design
809 */
810
811#define MVPP2_TXD_L3_OFF_SHIFT 0
812#define MVPP2_TXD_IP_HLEN_SHIFT 8
813#define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
814#define MVPP2_TXD_L4_CSUM_NOT BIT(14)
815#define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
816#define MVPP2_TXD_PADDING_DISABLE BIT(23)
817#define MVPP2_TXD_L4_UDP BIT(24)
818#define MVPP2_TXD_L3_IP6 BIT(26)
819#define MVPP2_TXD_L_DESC BIT(28)
820#define MVPP2_TXD_F_DESC BIT(29)
821
822#define MVPP2_RXD_ERR_SUMMARY BIT(15)
823#define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
824#define MVPP2_RXD_ERR_CRC 0x0
825#define MVPP2_RXD_ERR_OVERRUN BIT(13)
826#define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
827#define MVPP2_RXD_BM_POOL_ID_OFFS 16
828#define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
829#define MVPP2_RXD_HWF_SYNC BIT(21)
830#define MVPP2_RXD_L4_CSUM_OK BIT(22)
831#define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
832#define MVPP2_RXD_L4_TCP BIT(25)
833#define MVPP2_RXD_L4_UDP BIT(26)
834#define MVPP2_RXD_L3_IP4 BIT(28)
835#define MVPP2_RXD_L3_IP6 BIT(30)
836#define MVPP2_RXD_BUF_HDR BIT(31)
837
838/* HW TX descriptor for PPv2.1 */
839struct mvpp21_tx_desc {
Maxime Chevallier7b9c7d72018-06-28 14:42:04 +0200840 __le32 command; /* Options used by HW for packet transmitting.*/
Maxime Chevallierdb9d7d32018-05-31 10:07:43 +0200841 u8 packet_offset; /* the offset from the buffer beginning */
842 u8 phys_txq; /* destination queue ID */
Maxime Chevallier7b9c7d72018-06-28 14:42:04 +0200843 __le16 data_size; /* data size of transmitted packet in bytes */
844 __le32 buf_dma_addr; /* physical addr of transmitted buffer */
845 __le32 buf_cookie; /* cookie for access to TX buffer in tx path */
846 __le32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
847 __le32 reserved2; /* reserved (for future use) */
Maxime Chevallierdb9d7d32018-05-31 10:07:43 +0200848};
849
850/* HW RX descriptor for PPv2.1 */
851struct mvpp21_rx_desc {
Maxime Chevallier7b9c7d72018-06-28 14:42:04 +0200852 __le32 status; /* info about received packet */
853 __le16 reserved1; /* parser_info (for future use, PnC) */
854 __le16 data_size; /* size of received packet in bytes */
855 __le32 buf_dma_addr; /* physical address of the buffer */
856 __le32 buf_cookie; /* cookie for access to RX buffer in rx path */
857 __le16 reserved2; /* gem_port_id (for future use, PON) */
858 __le16 reserved3; /* csum_l4 (for future use, PnC) */
Maxime Chevallierdb9d7d32018-05-31 10:07:43 +0200859 u8 reserved4; /* bm_qset (for future use, BM) */
860 u8 reserved5;
Maxime Chevallier7b9c7d72018-06-28 14:42:04 +0200861 __le16 reserved6; /* classify_info (for future use, PnC) */
862 __le32 reserved7; /* flow_id (for future use, PnC) */
863 __le32 reserved8;
Maxime Chevallierdb9d7d32018-05-31 10:07:43 +0200864};
865
866/* HW TX descriptor for PPv2.2 */
867struct mvpp22_tx_desc {
Maxime Chevallier7b9c7d72018-06-28 14:42:04 +0200868 __le32 command;
Maxime Chevallierdb9d7d32018-05-31 10:07:43 +0200869 u8 packet_offset;
870 u8 phys_txq;
Maxime Chevallier7b9c7d72018-06-28 14:42:04 +0200871 __le16 data_size;
872 __le64 reserved1;
873 __le64 buf_dma_addr_ptp;
874 __le64 buf_cookie_misc;
Maxime Chevallierdb9d7d32018-05-31 10:07:43 +0200875};
876
877/* HW RX descriptor for PPv2.2 */
878struct mvpp22_rx_desc {
Maxime Chevallier7b9c7d72018-06-28 14:42:04 +0200879 __le32 status;
880 __le16 reserved1;
881 __le16 data_size;
882 __le32 reserved2;
883 __le32 reserved3;
884 __le64 buf_dma_addr_key_hash;
885 __le64 buf_cookie_misc;
Maxime Chevallierdb9d7d32018-05-31 10:07:43 +0200886};
887
888/* Opaque type used by the driver to manipulate the HW TX and RX
889 * descriptors
890 */
891struct mvpp2_tx_desc {
892 union {
893 struct mvpp21_tx_desc pp21;
894 struct mvpp22_tx_desc pp22;
895 };
896};
897
898struct mvpp2_rx_desc {
899 union {
900 struct mvpp21_rx_desc pp21;
901 struct mvpp22_rx_desc pp22;
902 };
903};
904
905struct mvpp2_txq_pcpu_buf {
906 /* Transmitted SKB */
907 struct sk_buff *skb;
908
909 /* Physical address of transmitted buffer */
910 dma_addr_t dma;
911
912 /* Size transmitted */
913 size_t size;
914};
915
916/* Per-CPU Tx queue control */
917struct mvpp2_txq_pcpu {
918 int cpu;
919
920 /* Number of Tx DMA descriptors in the descriptor ring */
921 int size;
922
923 /* Number of currently used Tx DMA descriptor in the
924 * descriptor ring
925 */
926 int count;
927
928 int wake_threshold;
929 int stop_threshold;
930
931 /* Number of Tx DMA descriptors reserved for each CPU */
932 int reserved_num;
933
934 /* Infos about transmitted buffers */
935 struct mvpp2_txq_pcpu_buf *buffs;
936
937 /* Index of last TX DMA descriptor that was inserted */
938 int txq_put_index;
939
940 /* Index of the TX DMA descriptor to be cleaned up */
941 int txq_get_index;
942
943 /* DMA buffer for TSO headers */
944 char *tso_headers;
945 dma_addr_t tso_headers_dma;
946};
947
948struct mvpp2_tx_queue {
949 /* Physical number of this Tx queue */
950 u8 id;
951
952 /* Logical number of this Tx queue */
953 u8 log_id;
954
955 /* Number of Tx DMA descriptors in the descriptor ring */
956 int size;
957
958 /* Number of currently used Tx DMA descriptor in the descriptor ring */
959 int count;
960
961 /* Per-CPU control of physical Tx queues */
962 struct mvpp2_txq_pcpu __percpu *pcpu;
963
964 u32 done_pkts_coal;
965
966 /* Virtual address of thex Tx DMA descriptors array */
967 struct mvpp2_tx_desc *descs;
968
969 /* DMA address of the Tx DMA descriptors array */
970 dma_addr_t descs_dma;
971
972 /* Index of the last Tx DMA descriptor */
973 int last_desc;
974
975 /* Index of the next Tx DMA descriptor to process */
976 int next_desc_to_proc;
977};
978
979struct mvpp2_rx_queue {
980 /* RX queue number, in the range 0-31 for physical RXQs */
981 u8 id;
982
983 /* Num of rx descriptors in the rx descriptor ring */
984 int size;
985
986 u32 pkts_coal;
987 u32 time_coal;
988
989 /* Virtual address of the RX DMA descriptors array */
990 struct mvpp2_rx_desc *descs;
991
992 /* DMA address of the RX DMA descriptors array */
993 dma_addr_t descs_dma;
994
995 /* Index of the last RX DMA descriptor */
996 int last_desc;
997
998 /* Index of the next RX DMA descriptor to process */
999 int next_desc_to_proc;
1000
1001 /* ID of port to which physical RXQ is mapped */
1002 int port;
1003
1004 /* Port's logic RXQ number to which physical RXQ is mapped */
1005 int logic_rxq;
1006};
1007
1008struct mvpp2_bm_pool {
1009 /* Pool number in the range 0-7 */
1010 int id;
1011
1012 /* Buffer Pointers Pool External (BPPE) size */
1013 int size;
1014 /* BPPE size in bytes */
1015 int size_bytes;
1016 /* Number of buffers for this pool */
1017 int buf_num;
1018 /* Pool buffer size */
1019 int buf_size;
1020 /* Packet size */
1021 int pkt_size;
1022 int frag_size;
1023
1024 /* BPPE virtual base address */
1025 u32 *virt_addr;
1026 /* BPPE DMA base address */
1027 dma_addr_t dma_addr;
1028
1029 /* Ports using BM pool */
1030 u32 port_map;
1031};
1032
1033#define IS_TSO_HEADER(txq_pcpu, addr) \
1034 ((addr) >= (txq_pcpu)->tso_headers_dma && \
1035 (addr) < (txq_pcpu)->tso_headers_dma + \
1036 (txq_pcpu)->size * TSO_HEADER_SIZE)
1037
1038#define MVPP2_DRIVER_NAME "mvpp2"
1039#define MVPP2_DRIVER_VERSION "1.0"
1040
1041void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data);
1042u32 mvpp2_read(struct mvpp2 *priv, u32 offset);
1043
1044u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset);
1045
1046void mvpp2_percpu_write(struct mvpp2 *priv, int cpu, u32 offset, u32 data);
1047u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu, u32 offset);
1048
1049void mvpp2_percpu_write_relaxed(struct mvpp2 *priv, int cpu, u32 offset,
1050 u32 data);
1051
1052#endif