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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 0837f52463583f76670ab2350e0f1541cb0351f5 / . / arch / sh / mm / flush-sh4.c
blob: edefc53891a821b0e20db68c95f6ed66c71f06df [file] [log] [blame]
Paul Mundt81742522009-08-04 18:06:01 +0900[diff] [blame]1#include <linux/mm.h>
2#include <asm/mmu_context.h>
3#include <asm/cacheflush.h>
4
5/*
6 * Write back the dirty D-caches, but not invalidate them.
7 *
8 * START: Virtual Address (U0, P1, or P3)
9 * SIZE: Size of the region.
10 */
11void __weak __flush_wback_region(void *start, int size)
12{
Paul Mundt0837f522009-08-04 18:09:54 +0900[diff] [blame^]13 unsigned long v, cnt, end;
Paul Mundt81742522009-08-04 18:06:01 +0900[diff] [blame]14
Paul Mundt0837f522009-08-04 18:09:54 +0900[diff] [blame^]15 v = (unsigned long)start & ~(L1_CACHE_BYTES-1);
Paul Mundt81742522009-08-04 18:06:01 +0900[diff] [blame]16 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
17 & ~(L1_CACHE_BYTES-1);
Paul Mundt0837f522009-08-04 18:09:54 +0900[diff] [blame^]18 cnt = (end - v) / L1_CACHE_BYTES;
19
20 while (cnt >= 8) {
21 asm volatile("ocbwb @%0" : : "r" (v));
22 v += L1_CACHE_BYTES;
23 asm volatile("ocbwb @%0" : : "r" (v));
24 v += L1_CACHE_BYTES;
25 asm volatile("ocbwb @%0" : : "r" (v));
26 v += L1_CACHE_BYTES;
27 asm volatile("ocbwb @%0" : : "r" (v));
28 v += L1_CACHE_BYTES;
29 asm volatile("ocbwb @%0" : : "r" (v));
30 v += L1_CACHE_BYTES;
31 asm volatile("ocbwb @%0" : : "r" (v));
32 v += L1_CACHE_BYTES;
33 asm volatile("ocbwb @%0" : : "r" (v));
34 v += L1_CACHE_BYTES;
35 asm volatile("ocbwb @%0" : : "r" (v));
36 v += L1_CACHE_BYTES;
37 cnt -= 8;
38 }
39
40 while (cnt) {
41 asm volatile("ocbwb @%0" : : "r" (v));
42 v += L1_CACHE_BYTES;
43 cnt--;
Paul Mundt81742522009-08-04 18:06:01 +0900[diff] [blame]44 }
45}
46
47/*
48 * Write back the dirty D-caches and invalidate them.
49 *
50 * START: Virtual Address (U0, P1, or P3)
51 * SIZE: Size of the region.
52 */
53void __weak __flush_purge_region(void *start, int size)
54{
Paul Mundt0837f522009-08-04 18:09:54 +0900[diff] [blame^]55 unsigned long v, cnt, end;
Paul Mundt81742522009-08-04 18:06:01 +0900[diff] [blame]56
Paul Mundt0837f522009-08-04 18:09:54 +0900[diff] [blame^]57 v = (unsigned long)start & ~(L1_CACHE_BYTES-1);
Paul Mundt81742522009-08-04 18:06:01 +0900[diff] [blame]58 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
59 & ~(L1_CACHE_BYTES-1);
Paul Mundt0837f522009-08-04 18:09:54 +0900[diff] [blame^]60 cnt = (end - v) / L1_CACHE_BYTES;
61
62 while (cnt >= 8) {
63 asm volatile("ocbp @%0" : : "r" (v));
64 v += L1_CACHE_BYTES;
65 asm volatile("ocbp @%0" : : "r" (v));
66 v += L1_CACHE_BYTES;
67 asm volatile("ocbp @%0" : : "r" (v));
68 v += L1_CACHE_BYTES;
69 asm volatile("ocbp @%0" : : "r" (v));
70 v += L1_CACHE_BYTES;
71 asm volatile("ocbp @%0" : : "r" (v));
72 v += L1_CACHE_BYTES;
73 asm volatile("ocbp @%0" : : "r" (v));
74 v += L1_CACHE_BYTES;
75 asm volatile("ocbp @%0" : : "r" (v));
76 v += L1_CACHE_BYTES;
77 asm volatile("ocbp @%0" : : "r" (v));
78 v += L1_CACHE_BYTES;
79 cnt -= 8;
80 }
81 while (cnt) {
82 asm volatile("ocbp @%0" : : "r" (v));
83 v += L1_CACHE_BYTES;
84 cnt--;
Paul Mundt81742522009-08-04 18:06:01 +0900[diff] [blame]85 }
86}
87
88/*
89 * No write back please
90 */
91void __weak __flush_invalidate_region(void *start, int size)
92{
Paul Mundt0837f522009-08-04 18:09:54 +0900[diff] [blame^]93 unsigned long v, cnt, end;
Paul Mundt81742522009-08-04 18:06:01 +0900[diff] [blame]94
Paul Mundt0837f522009-08-04 18:09:54 +0900[diff] [blame^]95 v = (unsigned long)start & ~(L1_CACHE_BYTES-1);
Paul Mundt81742522009-08-04 18:06:01 +0900[diff] [blame]96 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
97 & ~(L1_CACHE_BYTES-1);
Paul Mundt0837f522009-08-04 18:09:54 +0900[diff] [blame^]98 cnt = (end - v) / L1_CACHE_BYTES;
99
100 while (cnt >= 8) {
101 asm volatile("ocbi @%0" : : "r" (v));
102 v += L1_CACHE_BYTES;
103 asm volatile("ocbi @%0" : : "r" (v));
104 v += L1_CACHE_BYTES;
105 asm volatile("ocbi @%0" : : "r" (v));
106 v += L1_CACHE_BYTES;
107 asm volatile("ocbi @%0" : : "r" (v));
108 v += L1_CACHE_BYTES;
109 asm volatile("ocbi @%0" : : "r" (v));
110 v += L1_CACHE_BYTES;
111 asm volatile("ocbi @%0" : : "r" (v));
112 v += L1_CACHE_BYTES;
113 asm volatile("ocbi @%0" : : "r" (v));
114 v += L1_CACHE_BYTES;
115 asm volatile("ocbi @%0" : : "r" (v));
116 v += L1_CACHE_BYTES;
117 cnt -= 8;
118 }
119
120 while (cnt) {
121 asm volatile("ocbi @%0" : : "r" (v));
122 v += L1_CACHE_BYTES;
123 cnt--;
Paul Mundt81742522009-08-04 18:06:01 +0900[diff] [blame]124 }
125}