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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 01db527e657d6cf646c6e6f059ad41e7023a25e7 / . / arch / arm / boot / dts / kirkwood.dtsi
blob: 1ae3eb2dea2eb4f176630f44b030569f44301709 [file] [log] [blame]
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]4 compatible = "marvell,kirkwood";
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]5 interrupt-parent = <&intc>;
6
Adam Baker33a66752013-06-02 22:59:50 +0100[diff] [blame]7 cpus {
8 #address-cells = <1>;
9 #size-cells = <0>;
10
11 cpu@0 {
12 device_type = "cpu";
13 compatible = "marvell,feroceon";
14 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
15 clock-names = "cpu_clk", "ddrclk", "powersave";
16 };
17 };
18
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]19 aliases {
20 gpio0 = &gpio0;
21 gpio1 = &gpio1;
22 };
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]23 intc: interrupt-controller {
24 compatible = "marvell,orion-intc", "marvell,intc";
25 interrupt-controller;
26 #interrupt-cells = <1>;
27 reg = <0xf1020204 0x04>,
28 <0xf1020214 0x04>;
29 };
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]30
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]31 ocp@f1000000 {
32 compatible = "simple-bus";
Ezequiel Garcia01db5272013-06-18 12:31:19 -0300[diff] [blame^]33 ranges = <0x00000000 0xf1000000 0x0100000
34 0xf4000000 0xf4000000 0x0000400
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]35 0xf5000000 0xf5000000 0x0000400>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]36 #address-cells = <1>;
37 #size-cells = <1>;
38
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]39 core_clk: core-clocks@10030 {
40 compatible = "marvell,kirkwood-core-clock";
41 reg = <0x10030 0x4>;
42 #clock-cells = <1>;
43 };
44
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]45 gpio0: gpio@10100 {
46 compatible = "marvell,orion-gpio";
47 #gpio-cells = <2>;
48 gpio-controller;
49 reg = <0x10100 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]50 ngpios = <32>;
51 interrupt-controller;
Sebastian Hesselbarth09d75bc2013-01-22 20:46:33 +0100[diff] [blame]52 #interrupt-cells = <2>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]53 interrupts = <35>, <36>, <37>, <38>;
Andrew Lunnde887472013-02-03 11:34:26 +0100[diff] [blame]54 clocks = <&gate_clk 7>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]55 };
56
57 gpio1: gpio@10140 {
58 compatible = "marvell,orion-gpio";
59 #gpio-cells = <2>;
60 gpio-controller;
61 reg = <0x10140 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]62 ngpios = <18>;
63 interrupt-controller;
Sebastian Hesselbarth09d75bc2013-01-22 20:46:33 +0100[diff] [blame]64 #interrupt-cells = <2>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]65 interrupts = <39>, <40>, <41>;
Andrew Lunnde887472013-02-03 11:34:26 +0100[diff] [blame]66 clocks = <&gate_clk 7>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]67 };
68
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]69 serial@12000 {
70 compatible = "ns16550a";
71 reg = <0x12000 0x100>;
72 reg-shift = <2>;
73 interrupts = <33>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]74 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]75 status = "disabled";
76 };
77
78 serial@12100 {
79 compatible = "ns16550a";
80 reg = <0x12100 0x100>;
81 reg-shift = <2>;
82 interrupts = <34>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]83 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]84 status = "disabled";
85 };
Jason Coopere871b872012-03-06 23:55:04 +0000[diff] [blame]86
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]87 spi@10600 {
88 compatible = "marvell,orion-spi";
89 #address-cells = <1>;
90 #size-cells = <0>;
91 cell-index = <0>;
92 interrupts = <23>;
93 reg = <0x10600 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]94 clocks = <&gate_clk 7>;
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]95 status = "disabled";
96 };
97
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]98 gate_clk: clock-gating-control@2011c {
99 compatible = "marvell,kirkwood-gating-clock";
100 reg = <0x2011c 0x4>;
101 clocks = <&core_clk 0>;
102 #clock-cells = <1>;
103 };
104
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]105 wdt@20300 {
106 compatible = "marvell,orion-wdt";
107 reg = <0x20300 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]108 clocks = <&gate_clk 7>;
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]109 status = "okay";
110 };
111
Andrew Lunnc896ed02012-11-18 11:44:57 +0100[diff] [blame]112 xor@60800 {
113 compatible = "marvell,orion-xor";
114 reg = <0x60800 0x100
115 0x60A00 0x100>;
116 status = "okay";
117 clocks = <&gate_clk 8>;
118
119 xor00 {
120 interrupts = <5>;
121 dmacap,memcpy;
122 dmacap,xor;
123 };
124 xor01 {
125 interrupts = <6>;
126 dmacap,memcpy;
127 dmacap,xor;
128 dmacap,memset;
129 };
130 };
131
132 xor@60900 {
133 compatible = "marvell,orion-xor";
134 reg = <0x60900 0x100
135 0xd0B00 0x100>;
136 status = "okay";
137 clocks = <&gate_clk 16>;
138
139 xor00 {
140 interrupts = <7>;
141 dmacap,memcpy;
142 dmacap,xor;
143 };
144 xor01 {
145 interrupts = <8>;
146 dmacap,memcpy;
147 dmacap,xor;
148 dmacap,memset;
149 };
150 };
151
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200[diff] [blame]152 ehci@50000 {
153 compatible = "marvell,orion-ehci";
154 reg = <0x50000 0x1000>;
155 interrupts = <19>;
Andrew Lunn53dfa8e2013-01-06 11:10:34 +0100[diff] [blame]156 clocks = <&gate_clk 3>;
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200[diff] [blame]157 status = "okay";
158 };
159
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]160 nand@3000000 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 cle = <0>;
164 ale = <1>;
165 bank-width = <1>;
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]166 compatible = "marvell,orion-nand";
Ezequiel Garcia01db5272013-06-18 12:31:19 -0300[diff] [blame^]167 reg = <0xf4000000 0x400>;
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]168 chip-delay = <25>;
169 /* set partition map and/or chip-delay in board dts */
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]170 clocks = <&gate_clk 7>;
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]171 status = "disabled";
172 };
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]173
174 i2c@11000 {
175 compatible = "marvell,mv64xxx-i2c";
176 reg = <0x11000 0x20>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 interrupts = <29>;
180 clock-frequency = <100000>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]181 clocks = <&gate_clk 7>;
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]182 status = "disabled";
183 };
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]184
185 crypto@30000 {
186 compatible = "marvell,orion-crypto";
187 reg = <0x30000 0x10000>,
188 <0xf5000000 0x800>;
189 reg-names = "regs", "sram";
190 interrupts = <22>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]191 clocks = <&gate_clk 17>;
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]192 status = "okay";
193 };
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]194 };
195};