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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 00a6a5ef39e7db3648b35c86361058854db84c83 / . / arch / arm / boot / dts / at91sam9x5_lcd.dtsi
blob: f81c9d1691e036276f1d55600ec54591ed41114c [file] [log] [blame]
Thomas Gleixnerf50a7f32019-05-28 09:57:18 -0700[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
Boris BREZILLONa80d3ec2014-05-12 18:23:35 +0200[diff] [blame]2/*
3 * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
4 * LCD controller.
5 *
6 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
Boris BREZILLONa80d3ec2014-05-12 18:23:35 +0200[diff] [blame]7 */
8
9#include <dt-bindings/pinctrl/at91.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13 ahb {
14 apb {
Boris Brezilloneeff0402014-07-31 09:35:31 +0200[diff] [blame]15 hlcdc: hlcdc@f8038000 {
16 compatible = "atmel,at91sam9x5-hlcdc";
17 reg = <0xf8038000 0x4000>;
18 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
Alexandre Belloni6cf8f822018-07-16 11:24:17 +0200[diff] [blame]19 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
Boris Brezilloneeff0402014-07-31 09:35:31 +0200[diff] [blame]20 clock-names = "periph_clk","sys_clk", "slow_clk";
21 status = "disabled";
22
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 port@0 {
29 #address-cells = <1>;
30 #size-cells = <0>;
31 reg = <0>;
32 };
33 };
34
35 hlcdc_pwm: hlcdc-pwm {
36 compatible = "atmel,hlcdc-pwm";
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_lcd_pwm>;
39 #pwm-cells = <3>;
40 };
41 };
Uwe Kleine-König532173b42019-08-12 23:27:56 +0200[diff] [blame]42 };
43 };
44};
Boris Brezilloneeff0402014-07-31 09:35:31 +0200[diff] [blame]45
Uwe Kleine-König532173b42019-08-12 23:27:56 +0200[diff] [blame]46&pinctrl {
47 lcd {
48 pinctrl_lcd_base: lcd-base-0 {
49 atmel,pins =
50 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
51 AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
52 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
53 AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
54 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
55 };
Boris Brezilloneeff0402014-07-31 09:35:31 +0200[diff] [blame]56
Uwe Kleine-König532173b42019-08-12 23:27:56 +0200[diff] [blame]57 pinctrl_lcd_pwm: lcd-pwm-0 {
58 atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
59 };
Boris Brezilloneeff0402014-07-31 09:35:31 +0200[diff] [blame]60
Uwe Kleine-König532173b42019-08-12 23:27:56 +0200[diff] [blame]61 pinctrl_lcd_rgb444: lcd-rgb-0 {
62 atmel,pins =
63 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
64 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
65 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
66 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
67 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
68 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
69 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
70 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
71 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
72 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
73 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
74 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
75 };
Boris Brezilloneeff0402014-07-31 09:35:31 +0200[diff] [blame]76
Uwe Kleine-König532173b42019-08-12 23:27:56 +0200[diff] [blame]77 pinctrl_lcd_rgb565: lcd-rgb-1 {
78 atmel,pins =
79 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
80 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
81 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
82 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
83 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
84 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
85 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
86 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
87 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
88 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
89 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
90 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
91 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
92 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
93 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
94 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
95 };
Boris Brezilloneeff0402014-07-31 09:35:31 +0200[diff] [blame]96
Uwe Kleine-König532173b42019-08-12 23:27:56 +0200[diff] [blame]97 pinctrl_lcd_rgb666: lcd-rgb-2 {
98 atmel,pins =
99 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
100 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
101 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
102 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
103 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
104 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
105 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
106 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
107 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
108 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
109 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
110 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
111 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
112 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
113 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
114 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
115 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
116 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */
117 };
Boris Brezilloneeff0402014-07-31 09:35:31 +0200[diff] [blame]118
Uwe Kleine-König532173b42019-08-12 23:27:56 +0200[diff] [blame]119 pinctrl_lcd_rgb888: lcd-rgb-3 {
120 atmel,pins =
121 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
122 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
123 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
124 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
125 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
126 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
127 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
128 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
129 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
130 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
131 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
132 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
133 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
134 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
135 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
136 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
137 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
138 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
139 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
140 AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
141 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
142 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
143 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
144 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
Boris BREZILLONa80d3ec2014-05-12 18:23:35 +0200[diff] [blame]145 };
146 };
147};