| commit | c09513cfebd8d936a7aed3c0302104fb47a4a03a | [log] [tgz] |
|---|---|---|
| author | Jordan Crouse <jcrouse@codeaurora.org> | Tue Nov 21 12:40:57 2017 -0700 |
| committer | Rob Clark <robdclark@gmail.com> | Wed Jan 10 08:58:42 2018 -0500 |
| tree | 00def9b8aa3880725e4a494ba88139e104fb75a8 | |
| parent | f56d9df656c41b141399c1edbcc9b0ed048120c2 [diff] |
drm/msm/adreno: a5xx: Explicitly program the CP0 performance counter Even though the default countable for CP0 is CP_ALWAYS_COUNT (0), program the selector during HW initialization in an effort to be up front about which counters are programmed and why. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>