| commit | f56d9df656c41b141399c1edbcc9b0ed048120c2 | [log] [tgz] |
|---|---|---|
| author | Jordan Crouse <jcrouse@codeaurora.org> | Tue Nov 21 12:40:56 2017 -0700 |
| committer | Rob Clark <robdclark@gmail.com> | Wed Jan 10 08:58:42 2018 -0500 |
| tree | 50b17f3c9461c2d04e3627e74b60f77408f69f41 | |
| parent | 999ae6edc1c19e316dd61f4b3e1a6984ea293280 [diff] |
drm/msm/adreno: Read the speed bins for a5xx targets Some 5xx based chipsets have different bins for GPU clock speeds. Read the fuses (if applicable) and set the appropriate OPP table. This will only work with OPP v2 tables - the bin will be ignored for legacy pwrlevel tables. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>