| commit | f48e699ddf7056f83bb8e2dbe3c2ae8d1ff1a31a | [log] [tgz] |
|---|---|---|
| author | Brendan Higgins <brendanhiggins@google.com> | Fri Jun 02 18:29:49 2017 -0700 |
| committer | Marc Zyngier <marc.zyngier@arm.com> | Thu Jun 22 14:15:00 2017 +0100 |
| tree | acdac0e97e8286bee1ebdb30e21aa8f8e9013a1e | |
| parent | 0a56f9eebe6320980b68c60c852436cbf2a14b61 [diff] |
irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed The Aspeed 24XX/25XX chips share a single hardware interrupt across 14 separate I2C busses. This adds a dummy irqchip which maps the single hardware interrupt to software interrupts for each of the busses. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>