tree acdac0e97e8286bee1ebdb30e21aa8f8e9013a1e
parent 0a56f9eebe6320980b68c60c852436cbf2a14b61
author Brendan Higgins <brendanhiggins@google.com> 1496453389 -0700
committer Marc Zyngier <marc.zyngier@arm.com> 1498137300 +0100

irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed

The Aspeed 24XX/25XX chips share a single hardware interrupt across 14
separate I2C busses. This adds a dummy irqchip which maps the single
hardware interrupt to software interrupts for each of the busses.

Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>