Documentation/devicetree/bindings/display/msm/gmu.txt

Qualcomm adreno/snapdragon GMU (Graphics management unit)

The GMU is a programmable power controller for the GPU. the CPU controls the
GMU which in turn handles power controls for the GPU.

Required properties:
- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
    for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
  Note that you need to list the less specific "qcom,adreno-gmu"
  for generic matches and the more specific identifier to identify
  the specific device.
- reg: Physical base address and length of the GMU registers.
- reg-names: Matching names for the register regions
  * "gmu"
  * "gmu_pdc"
  * "gmu_pdc_seg"
- interrupts: The interrupt signals from the GMU.
- interrupt-names: Matching names for the interrupts
  * "hfi"
  * "gmu"
- clocks: phandles to the device clocks
- clock-names: Matching names for the clocks
   * "gmu"
   * "cxo"
   * "axi"
   * "mnoc"
- power-domains: should be:
	<&clock_gpucc GPU_CX_GDSC>
	<&clock_gpucc GPU_GX_GDSC>
- power-domain-names: Matching names for the power domains
- iommus: phandle to the adreno iommu
- operating-points-v2: phandle to the OPP operating points

Optional properties:
- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
        SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.

Example:

/ {
	...

	gmu: gmu@506a000 {
		compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";

		reg = <0x506a000 0x30000>,
			<0xb280000 0x10000>,
			<0xb480000 0x10000>;
		reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";

		interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hfi", "gmu";

		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
			<&gpucc GPU_CC_CXO_CLK>,
			<&gcc GCC_DDRSS_GPU_AXI_CLK>,
			<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
		clock-names = "gmu", "cxo", "axi", "memnoc";

		power-domains = <&gpucc GPU_CX_GDSC>,
				<&gpucc GPU_GX_GDSC>;
		power-domain-names = "cx", "gx";

		iommus = <&adreno_smmu 5>;

		operating-points-v2 = <&gmu_opp_table>;
	};
};

a3xx example with OCMEM support:

/ {
	...

	gpu: adreno@fdb00000 {
		compatible = "qcom,adreno-330.2",
		             "qcom,adreno";
		reg = <0xfdb00000 0x10000>;
		reg-names = "kgsl_3d0_reg_memory";
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "kgsl_3d0_irq";
		clock-names = "core",
		              "iface",
		              "mem_iface";
		clocks = <&mmcc OXILI_GFX3D_CLK>,
		         <&mmcc OXILICX_AHB_CLK>,
		         <&mmcc OXILICX_AXI_CLK>;
		sram = <&gmu_sram>;
		power-domains = <&mmcc OXILICX_GDSC>;
		operating-points-v2 = <&gpu_opp_table>;
		iommus = <&gpu_iommu 0>;
	};

	ocmem@fdd00000 {
		compatible = "qcom,msm8974-ocmem";

		reg = <0xfdd00000 0x2000>,
		      <0xfec00000 0x180000>;
		reg-names = "ctrl",
		             "mem";

		clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
		         <&mmcc OCMEMCX_OCMEMNOC_CLK>;
		clock-names = "core",
		              "iface";

		#address-cells = <1>;
		#size-cells = <1>;

		gmu_sram: gmu-sram@0 {
			reg = <0x0 0x100000>;
			ranges = <0 0 0xfec00000 0x100000>;
		};
	};
};