| ML-AHB interconnect bindings |
| |
| These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects |
| a Cortex-M subsystem with dedicated memories. |
| The MCU SRAM and RETRAM memory parts can be accessed through different addresses |
| (see "RAM aliases" in [1]) using different buses (see [2]) : balancing the |
| Cortex-M firmware accesses among those ports allows to tune the system |
| performance. |
| |
| [1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf |
| [2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping |
| |
| Required properties: |
| - compatible: should be "simple-bus" |
| - dma-ranges: describes memory addresses translation between the local CPU and |
| the remote Cortex-M processor. Each memory region, is declared with |
| 3 parameters: |
| - param 1: device base address (Cortex-M processor address) |
| - param 2: physical base address (local CPU address) |
| - param 3: size of the memory region. |
| |
| The Cortex-M remote processor accessed via the mlahb interconnect is described |
| by a child node. |
| |
| Example: |
| mlahb { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| dma-ranges = <0x00000000 0x38000000 0x10000>, |
| <0x10000000 0x10000000 0x60000>, |
| <0x30000000 0x30000000 0x60000>; |
| |
| m4_rproc: m4@10000000 { |
| ... |
| }; |
| }; |