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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02002 * linux/drivers/ide/pci/hpt366.c Version 1.20 Oct 1, 2007
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02007 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Sergei Shtylyov38b66f82007-04-20 22:16:58 +02008 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * Thanks to HighPoint Technologies for their assistance, and hardware.
11 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
12 * donation of an ABit BP6 mainboard, processor, and memory acellerated
13 * development and support.
14 *
Alan Coxb39b01f2005-06-27 15:24:27 -070015 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080016 * HighPoint has its own drivers (open source except for the RAID part)
17 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
18 * This may be useful to anyone wanting to work on this driver, however do not
19 * trust them too much since the code tends to become less and less meaningful
20 * as the time passes... :-/
Alan Coxb39b01f2005-06-27 15:24:27 -070021 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070022 * Note that final HPT370 support was done by force extraction of GPL.
23 *
24 * - add function for getting/setting power status of drive
25 * - the HPT370's state machine can get confused. reset it before each dma
26 * xfer to prevent that from happening.
27 * - reset state engine whenever we get an error.
28 * - check for busmaster state at end of dma.
29 * - use new highpoint timings.
30 * - detect bus speed using highpoint register.
31 * - use pll if we don't have a clock table. added a 66MHz table that's
32 * just 2x the 33MHz table.
33 * - removed turnaround. NOTE: we never want to switch between pll and
34 * pci clocks as the chip can glitch in those cases. the highpoint
35 * approved workaround slows everything down too much to be useful. in
36 * addition, we would have to serialize access to each chip.
37 * Adrian Sun <a.sun@sun.com>
38 *
39 * add drive timings for 66MHz PCI bus,
40 * fix ATA Cable signal detection, fix incorrect /proc info
41 * add /proc display for per-drive PIO/DMA/UDMA mode and
42 * per-channel ATA-33/66 Cable detect.
43 * Duncan Laurie <void@sun.com>
44 *
45 * fixup /proc output for multiple controllers
46 * Tim Hockin <thockin@sun.com>
47 *
48 * On hpt366:
49 * Reset the hpt366 on error, reset on dma
50 * Fix disabling Fast Interrupt hpt366.
51 * Mike Waychison <crlf@sun.com>
52 *
53 * Added support for 372N clocking and clock switching. The 372N needs
54 * different clocks on read/write. This requires overloading rw_disk and
55 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
56 * keeping me sane.
57 * Alan Cox <alan@redhat.com>
58 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080059 * - fix the clock turnaround code: it was writing to the wrong ports when
60 * called for the secondary channel, caching the current clock mode per-
61 * channel caused the cached register value to get out of sync with the
62 * actual one, the channels weren't serialized, the turnaround shouldn't
63 * be done on 66 MHz PCI bus
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010064 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
65 * does not allow for this speed anyway
66 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
67 * their primary channel is kind of virtual, it isn't tied to any pins)
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -080068 * - fix/remove bad/unused timing tables and use one set of tables for the whole
69 * HPT37x chip family; save space by introducing the separate transfer mode
70 * table in which the mode lookup is done
Sergei Shtylyov26c068d2006-12-13 00:35:52 -080071 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
Sergei Shtylyov72931362007-09-11 22:28:35 +020072 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
73 * read it only from the function 0 of HPT374 chips
Sergei Shtylyov33b18a62006-12-13 00:35:50 -080074 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
75 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
Sergei Shtylyov73d1dd92006-12-13 00:35:51 -080076 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
77 * they tamper with its fields
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010078 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
79 * since they may tamper with its fields
Sergei Shtylyov90778572007-02-07 18:17:51 +010080 * - prefix the driver startup messages with the real chip name
81 * - claim the extra 240 bytes of I/O space for all chips
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +020082 * - optimize the UltraDMA filtering and the drive list lookup code
Sergei Shtylyovb4586712007-02-07 18:17:54 +010083 * - use pci_get_slot() to get to the function 1 of HPT36x/374
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010084 * - cache offset of the channel's misc. control registers (MCRs) being used
85 * throughout the driver
86 * - only touch the relevant MCR when detecting the cable type on HPT374's
87 * function 1
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +010088 * - rename all the register related variables consistently
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010089 * - move all the interrupt twiddling code from the speedproc handlers into
90 * init_hwif_hpt366(), also grouping all the DMA related code together there
91 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
92 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
93 * when setting an UltraDMA mode
94 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
95 * the best possible one
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +010096 * - clean up DMA timeout handling for HPT370
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010097 * - switch to using the enumeration type to differ between the numerous chip
98 * variants, matching PCI device/revision ID with the chip type early, at the
99 * init_setup stage
100 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
101 * stop duplicating it for each channel by storing the pointer in the pci_dev
102 * structure: first, at the init_setup stage, point it to a static "template"
103 * with only the chip type and its specific base DPLL frequency, the highest
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200104 * UltraDMA mode, and the chip settings table pointer filled, then, at the
105 * init_chipset stage, allocate per-chip instance and fill it with the rest
106 * of the necessary information
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100107 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
108 * switch to calculating PCI clock frequency based on the chip's base DPLL
109 * frequency
110 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
Sergei Shtylyov278978e2007-06-08 15:14:32 +0200111 * anything newer than HPT370/A (except HPT374 that is not capable of this
112 * mode according to the manual)
Sergei Shtylyov6273d262007-02-07 18:18:20 +0100113 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
114 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100115 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
116 * the register setting lists into the table indexed by the clock selected
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200117 * - set the correct hwif->ultra_mask for each individual chip
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200118 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 */
121
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122#include <linux/types.h>
123#include <linux/module.h>
124#include <linux/kernel.h>
125#include <linux/delay.h>
126#include <linux/timer.h>
127#include <linux/mm.h>
128#include <linux/ioport.h>
129#include <linux/blkdev.h>
130#include <linux/hdreg.h>
131
132#include <linux/interrupt.h>
133#include <linux/pci.h>
134#include <linux/init.h>
135#include <linux/ide.h>
136
137#include <asm/uaccess.h>
138#include <asm/io.h>
139#include <asm/irq.h>
140
141/* various tuning parameters */
142#define HPT_RESET_STATE_ENGINE
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800143#undef HPT_DELAY_INTERRUPT
144#define HPT_SERIALIZE_IO 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145
146static const char *quirk_drives[] = {
147 "QUANTUM FIREBALLlct08 08",
148 "QUANTUM FIREBALLP KA6.4",
149 "QUANTUM FIREBALLP LM20.4",
150 "QUANTUM FIREBALLP LM20.5",
151 NULL
152};
153
154static const char *bad_ata100_5[] = {
155 "IBM-DTLA-307075",
156 "IBM-DTLA-307060",
157 "IBM-DTLA-307045",
158 "IBM-DTLA-307030",
159 "IBM-DTLA-307020",
160 "IBM-DTLA-307015",
161 "IBM-DTLA-305040",
162 "IBM-DTLA-305030",
163 "IBM-DTLA-305020",
164 "IC35L010AVER07-0",
165 "IC35L020AVER07-0",
166 "IC35L030AVER07-0",
167 "IC35L040AVER07-0",
168 "IC35L060AVER07-0",
169 "WDC AC310200R",
170 NULL
171};
172
173static const char *bad_ata66_4[] = {
174 "IBM-DTLA-307075",
175 "IBM-DTLA-307060",
176 "IBM-DTLA-307045",
177 "IBM-DTLA-307030",
178 "IBM-DTLA-307020",
179 "IBM-DTLA-307015",
180 "IBM-DTLA-305040",
181 "IBM-DTLA-305030",
182 "IBM-DTLA-305020",
183 "IC35L010AVER07-0",
184 "IC35L020AVER07-0",
185 "IC35L030AVER07-0",
186 "IC35L040AVER07-0",
187 "IC35L060AVER07-0",
188 "WDC AC310200R",
Sergei Shtylyov783353b2007-07-03 22:28:35 +0200189 "MAXTOR STM3320620A",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190 NULL
191};
192
193static const char *bad_ata66_3[] = {
194 "WDC AC310200R",
195 NULL
196};
197
198static const char *bad_ata33[] = {
199 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
200 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
201 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
202 "Maxtor 90510D4",
203 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
204 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
205 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
206 NULL
207};
208
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800209static u8 xfer_speeds[] = {
210 XFER_UDMA_6,
211 XFER_UDMA_5,
212 XFER_UDMA_4,
213 XFER_UDMA_3,
214 XFER_UDMA_2,
215 XFER_UDMA_1,
216 XFER_UDMA_0,
217
218 XFER_MW_DMA_2,
219 XFER_MW_DMA_1,
220 XFER_MW_DMA_0,
221
222 XFER_PIO_4,
223 XFER_PIO_3,
224 XFER_PIO_2,
225 XFER_PIO_1,
226 XFER_PIO_0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227};
228
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800229/* Key for bus clock timings
230 * 36x 37x
231 * bits bits
232 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
233 * cycles = value + 1
234 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
235 * cycles = value + 1
236 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
237 * register access.
238 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
239 * register access.
240 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
241 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
242 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
243 * MW DMA xfer.
244 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
245 * task file register access.
246 * 28 28 UDMA enable.
247 * 29 29 DMA enable.
248 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
249 * PIO xfer.
250 * 31 31 FIFO enable.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800253static u32 forty_base_hpt36x[] = {
254 /* XFER_UDMA_6 */ 0x900fd943,
255 /* XFER_UDMA_5 */ 0x900fd943,
256 /* XFER_UDMA_4 */ 0x900fd943,
257 /* XFER_UDMA_3 */ 0x900ad943,
258 /* XFER_UDMA_2 */ 0x900bd943,
259 /* XFER_UDMA_1 */ 0x9008d943,
260 /* XFER_UDMA_0 */ 0x9008d943,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800262 /* XFER_MW_DMA_2 */ 0xa008d943,
263 /* XFER_MW_DMA_1 */ 0xa010d955,
264 /* XFER_MW_DMA_0 */ 0xa010d9fc,
265
266 /* XFER_PIO_4 */ 0xc008d963,
267 /* XFER_PIO_3 */ 0xc010d974,
268 /* XFER_PIO_2 */ 0xc010d997,
269 /* XFER_PIO_1 */ 0xc010d9c7,
270 /* XFER_PIO_0 */ 0xc018d9d9
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271};
272
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800273static u32 thirty_three_base_hpt36x[] = {
274 /* XFER_UDMA_6 */ 0x90c9a731,
275 /* XFER_UDMA_5 */ 0x90c9a731,
276 /* XFER_UDMA_4 */ 0x90c9a731,
277 /* XFER_UDMA_3 */ 0x90cfa731,
278 /* XFER_UDMA_2 */ 0x90caa731,
279 /* XFER_UDMA_1 */ 0x90cba731,
280 /* XFER_UDMA_0 */ 0x90c8a731,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800282 /* XFER_MW_DMA_2 */ 0xa0c8a731,
283 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
284 /* XFER_MW_DMA_0 */ 0xa0c8a797,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800286 /* XFER_PIO_4 */ 0xc0c8a731,
287 /* XFER_PIO_3 */ 0xc0c8a742,
288 /* XFER_PIO_2 */ 0xc0d0a753,
289 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
290 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291};
292
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800293static u32 twenty_five_base_hpt36x[] = {
294 /* XFER_UDMA_6 */ 0x90c98521,
295 /* XFER_UDMA_5 */ 0x90c98521,
296 /* XFER_UDMA_4 */ 0x90c98521,
297 /* XFER_UDMA_3 */ 0x90cf8521,
298 /* XFER_UDMA_2 */ 0x90cf8521,
299 /* XFER_UDMA_1 */ 0x90cb8521,
300 /* XFER_UDMA_0 */ 0x90cb8521,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800302 /* XFER_MW_DMA_2 */ 0xa0ca8521,
303 /* XFER_MW_DMA_1 */ 0xa0ca8532,
304 /* XFER_MW_DMA_0 */ 0xa0ca8575,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800306 /* XFER_PIO_4 */ 0xc0ca8521,
307 /* XFER_PIO_3 */ 0xc0ca8532,
308 /* XFER_PIO_2 */ 0xc0ca8542,
309 /* XFER_PIO_1 */ 0xc0d08572,
310 /* XFER_PIO_0 */ 0xc0d08585
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311};
312
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800313static u32 thirty_three_base_hpt37x[] = {
314 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
315 /* XFER_UDMA_5 */ 0x12446231,
316 /* XFER_UDMA_4 */ 0x12446231,
317 /* XFER_UDMA_3 */ 0x126c6231,
318 /* XFER_UDMA_2 */ 0x12486231,
319 /* XFER_UDMA_1 */ 0x124c6233,
320 /* XFER_UDMA_0 */ 0x12506297,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800322 /* XFER_MW_DMA_2 */ 0x22406c31,
323 /* XFER_MW_DMA_1 */ 0x22406c33,
324 /* XFER_MW_DMA_0 */ 0x22406c97,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800326 /* XFER_PIO_4 */ 0x06414e31,
327 /* XFER_PIO_3 */ 0x06414e42,
328 /* XFER_PIO_2 */ 0x06414e53,
329 /* XFER_PIO_1 */ 0x06814e93,
330 /* XFER_PIO_0 */ 0x06814ea7
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331};
332
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800333static u32 fifty_base_hpt37x[] = {
334 /* XFER_UDMA_6 */ 0x12848242,
335 /* XFER_UDMA_5 */ 0x12848242,
336 /* XFER_UDMA_4 */ 0x12ac8242,
337 /* XFER_UDMA_3 */ 0x128c8242,
338 /* XFER_UDMA_2 */ 0x120c8242,
339 /* XFER_UDMA_1 */ 0x12148254,
340 /* XFER_UDMA_0 */ 0x121882ea,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800342 /* XFER_MW_DMA_2 */ 0x22808242,
343 /* XFER_MW_DMA_1 */ 0x22808254,
344 /* XFER_MW_DMA_0 */ 0x228082ea,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800346 /* XFER_PIO_4 */ 0x0a81f442,
347 /* XFER_PIO_3 */ 0x0a81f443,
348 /* XFER_PIO_2 */ 0x0a81f454,
349 /* XFER_PIO_1 */ 0x0ac1f465,
350 /* XFER_PIO_0 */ 0x0ac1f48a
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351};
352
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800353static u32 sixty_six_base_hpt37x[] = {
354 /* XFER_UDMA_6 */ 0x1c869c62,
355 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
356 /* XFER_UDMA_4 */ 0x1c8a9c62,
357 /* XFER_UDMA_3 */ 0x1c8e9c62,
358 /* XFER_UDMA_2 */ 0x1c929c62,
359 /* XFER_UDMA_1 */ 0x1c9a9c62,
360 /* XFER_UDMA_0 */ 0x1c829c62,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800362 /* XFER_MW_DMA_2 */ 0x2c829c62,
363 /* XFER_MW_DMA_1 */ 0x2c829c66,
364 /* XFER_MW_DMA_0 */ 0x2c829d2e,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800366 /* XFER_PIO_4 */ 0x0c829c62,
367 /* XFER_PIO_3 */ 0x0c829c84,
368 /* XFER_PIO_2 */ 0x0c829ca6,
369 /* XFER_PIO_1 */ 0x0d029d26,
370 /* XFER_PIO_0 */ 0x0d029d5e
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371};
372
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373#define HPT366_DEBUG_DRIVE_INFO 0
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100374#define HPT371_ALLOW_ATA133_6 1
375#define HPT302_ALLOW_ATA133_6 1
376#define HPT372_ALLOW_ATA133_6 1
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100377#define HPT370_ALLOW_ATA100_5 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378#define HPT366_ALLOW_ATA66_4 1
379#define HPT366_ALLOW_ATA66_3 1
380#define HPT366_MAX_DEVS 8
381
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100382/* Supported ATA clock frequencies */
383enum ata_clock {
384 ATA_CLOCK_25MHZ,
385 ATA_CLOCK_33MHZ,
386 ATA_CLOCK_40MHZ,
387 ATA_CLOCK_50MHZ,
388 ATA_CLOCK_66MHZ,
389 NUM_ATA_CLOCKS
Alan Coxb39b01f2005-06-27 15:24:27 -0700390};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391
Alan Coxb39b01f2005-06-27 15:24:27 -0700392/*
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100393 * Hold all the HighPoint chip information in one place.
Alan Coxb39b01f2005-06-27 15:24:27 -0700394 */
395
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100396struct hpt_info {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200397 char *chip_name; /* Chip name */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100398 u8 chip_type; /* Chip type */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200399 u8 udma_mask; /* Allowed UltraDMA modes mask. */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100400 u8 dpll_clk; /* DPLL clock in MHz */
401 u8 pci_clk; /* PCI clock in MHz */
402 u32 **settings; /* Chipset settings table */
403};
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100404
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100405/* Supported HighPoint chips */
406enum {
407 HPT36x,
408 HPT370,
409 HPT370A,
410 HPT374,
411 HPT372,
412 HPT372A,
413 HPT302,
414 HPT371,
415 HPT372N,
416 HPT302N,
417 HPT371N
418};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100420static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
421 twenty_five_base_hpt36x,
422 thirty_three_base_hpt36x,
423 forty_base_hpt36x,
424 NULL,
425 NULL
426};
427
428static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
429 NULL,
430 thirty_three_base_hpt37x,
431 NULL,
432 fifty_base_hpt37x,
433 sixty_six_base_hpt37x
434};
435
436static struct hpt_info hpt36x __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200437 .chip_name = "HPT36x",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100438 .chip_type = HPT36x,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200439 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100440 .dpll_clk = 0, /* no DPLL */
441 .settings = hpt36x_settings
442};
443
444static struct hpt_info hpt370 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200445 .chip_name = "HPT370",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100446 .chip_type = HPT370,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200447 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100448 .dpll_clk = 48,
449 .settings = hpt37x_settings
450};
451
452static struct hpt_info hpt370a __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200453 .chip_name = "HPT370A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100454 .chip_type = HPT370A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200455 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100456 .dpll_clk = 48,
457 .settings = hpt37x_settings
458};
459
460static struct hpt_info hpt374 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200461 .chip_name = "HPT374",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100462 .chip_type = HPT374,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200463 .udma_mask = ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100464 .dpll_clk = 48,
465 .settings = hpt37x_settings
466};
467
468static struct hpt_info hpt372 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200469 .chip_name = "HPT372",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100470 .chip_type = HPT372,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200471 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100472 .dpll_clk = 55,
473 .settings = hpt37x_settings
474};
475
476static struct hpt_info hpt372a __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200477 .chip_name = "HPT372A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100478 .chip_type = HPT372A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200479 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100480 .dpll_clk = 66,
481 .settings = hpt37x_settings
482};
483
484static struct hpt_info hpt302 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200485 .chip_name = "HPT302",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100486 .chip_type = HPT302,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200487 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100488 .dpll_clk = 66,
489 .settings = hpt37x_settings
490};
491
492static struct hpt_info hpt371 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200493 .chip_name = "HPT371",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100494 .chip_type = HPT371,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200495 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100496 .dpll_clk = 66,
497 .settings = hpt37x_settings
498};
499
500static struct hpt_info hpt372n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200501 .chip_name = "HPT372N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100502 .chip_type = HPT372N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200503 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100504 .dpll_clk = 77,
505 .settings = hpt37x_settings
506};
507
508static struct hpt_info hpt302n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200509 .chip_name = "HPT302N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100510 .chip_type = HPT302N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200511 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100512 .dpll_clk = 77,
Sergei Shtylyov38b66f82007-04-20 22:16:58 +0200513 .settings = hpt37x_settings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100514};
515
516static struct hpt_info hpt371n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200517 .chip_name = "HPT371N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100518 .chip_type = HPT371N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200519 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100520 .dpll_clk = 77,
521 .settings = hpt37x_settings
522};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100524static int check_in_drive_list(ide_drive_t *drive, const char **list)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525{
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100526 struct hd_driveid *id = drive->id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100528 while (*list)
529 if (!strcmp(*list++,id->model))
530 return 1;
531 return 0;
532}
Alan Coxb39b01f2005-06-27 15:24:27 -0700533
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534/*
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200535 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
536 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 */
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200538
539static u8 hpt3xx_udma_filter(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540{
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200541 ide_hwif_t *hwif = HWIF(drive);
542 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
543 u8 mask = hwif->ultra_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200545 switch (info->chip_type) {
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200546 case HPT36x:
547 if (!HPT366_ALLOW_ATA66_4 ||
548 check_in_drive_list(drive, bad_ata66_4))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200549 mask = ATA_UDMA3;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100550
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200551 if (!HPT366_ALLOW_ATA66_3 ||
552 check_in_drive_list(drive, bad_ata66_3))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200553 mask = ATA_UDMA2;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200554 break;
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200555 case HPT370:
556 if (!HPT370_ALLOW_ATA100_5 ||
557 check_in_drive_list(drive, bad_ata100_5))
558 mask = ATA_UDMA4;
559 break;
560 case HPT370A:
561 if (!HPT370_ALLOW_ATA100_5 ||
562 check_in_drive_list(drive, bad_ata100_5))
563 return ATA_UDMA4;
564 case HPT372 :
565 case HPT372A:
566 case HPT372N:
567 case HPT374 :
568 if (ide_dev_is_sata(drive->id))
569 mask &= ~0x0e;
570 /* Fall thru */
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200571 default:
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200572 return mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573 }
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200574
575 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576}
577
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200578static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
579{
580 ide_hwif_t *hwif = HWIF(drive);
581 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
582
583 switch (info->chip_type) {
584 case HPT372 :
585 case HPT372A:
586 case HPT372N:
587 case HPT374 :
588 if (ide_dev_is_sata(drive->id))
589 return 0x00;
590 /* Fall thru */
591 default:
592 return 0x07;
593 }
594}
595
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100596static u32 get_speed_setting(u8 speed, struct hpt_info *info)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597{
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800598 int i;
599
600 /*
601 * Lookup the transfer mode table to get the index into
602 * the timing table.
603 *
604 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
605 */
606 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
607 if (xfer_speeds[i] == speed)
608 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100609 /*
610 * NOTE: info->settings only points to the pointer
611 * to the list of the actual register values
612 */
613 return (*info->settings)[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614}
615
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200616static void hpt36x_set_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100618 ide_hwif_t *hwif = HWIF(drive);
619 struct pci_dev *dev = hwif->pci_dev;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100620 struct hpt_info *info = pci_get_drvdata(dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100621 u8 itr_addr = drive->dn ? 0x44 : 0x40;
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100622 u32 old_itr = 0;
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200623 u32 itr_mask, new_itr;
624
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200625 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 :
626 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff);
627
628 new_itr = get_speed_setting(speed, info);
Alan Coxb39b01f2005-06-27 15:24:27 -0700629
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630 /*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100631 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
632 * to avoid problems handling I/O errors later
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633 */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100634 pci_read_config_dword(dev, itr_addr, &old_itr);
635 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
636 new_itr &= ~0xc0000000;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100638 pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639}
640
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200641static void hpt37x_set_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700642{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100643 ide_hwif_t *hwif = HWIF(drive);
644 struct pci_dev *dev = hwif->pci_dev;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100645 struct hpt_info *info = pci_get_drvdata(dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100646 u8 itr_addr = 0x40 + (drive->dn * 4);
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100647 u32 old_itr = 0;
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200648 u32 itr_mask, new_itr;
649
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200650 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
651 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff);
652
653 new_itr = get_speed_setting(speed, info);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100655 pci_read_config_dword(dev, itr_addr, &old_itr);
656 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657
Alan Coxb39b01f2005-06-27 15:24:27 -0700658 if (speed < XFER_MW_DMA_0)
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100659 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
660 pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661}
662
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200663static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100665 ide_hwif_t *hwif = HWIF(drive);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100666 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100668 if (info->chip_type >= HPT370)
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200669 hpt37x_set_mode(drive, speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670 else /* hpt368: hpt_minimum_revision(dev, 2) */
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200671 hpt36x_set_mode(drive, speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672}
673
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200674static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675{
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200676 hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677}
678
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100679static int hpt3xx_quirkproc(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680{
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100681 struct hd_driveid *id = drive->id;
682 const char **list = quirk_drives;
683
684 while (*list)
685 if (strstr(id->model, *list++))
686 return 1;
687 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688}
689
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100690static void hpt3xx_intrproc(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692 if (drive->quirk_list)
693 return;
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +0200694
Linus Torvalds1da177e2005-04-16 15:20:36 -0700695 /* drives in the quirk_list may not like intr setups/cleanups */
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +0200696 outb(drive->ctl | 2, IDE_CONTROL_REG);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697}
698
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100699static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100701 ide_hwif_t *hwif = HWIF(drive);
702 struct pci_dev *dev = hwif->pci_dev;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100703 struct hpt_info *info = pci_get_drvdata(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704
705 if (drive->quirk_list) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100706 if (info->chip_type >= HPT370) {
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100707 u8 scr1 = 0;
708
709 pci_read_config_byte(dev, 0x5a, &scr1);
710 if (((scr1 & 0x10) >> 4) != mask) {
711 if (mask)
712 scr1 |= 0x10;
713 else
714 scr1 &= ~0x10;
715 pci_write_config_byte(dev, 0x5a, scr1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716 }
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100717 } else {
718 if (mask)
719 disable_irq(hwif->irq);
720 else
721 enable_irq (hwif->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722 }
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100723 } else
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +0200724 outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
725 IDE_CONTROL_REG);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726}
727
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728/*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100729 * This is specific to the HPT366 UDMA chipset
Linus Torvalds1da177e2005-04-16 15:20:36 -0700730 * by HighPoint|Triones Technologies, Inc.
731 */
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200732static void hpt366_dma_lost_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100734 struct pci_dev *dev = HWIF(drive)->pci_dev;
735 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100737 pci_read_config_byte(dev, 0x50, &mcr1);
738 pci_read_config_byte(dev, 0x52, &mcr3);
739 pci_read_config_byte(dev, 0x5a, &scr1);
740 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
741 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
742 if (scr1 & 0x10)
743 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200744 ide_dma_lost_irq(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745}
746
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100747static void hpt370_clear_engine(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100749 ide_hwif_t *hwif = HWIF(drive);
750
751 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 udelay(10);
753}
754
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100755static void hpt370_irq_timeout(ide_drive_t *drive)
756{
757 ide_hwif_t *hwif = HWIF(drive);
758 u16 bfifo = 0;
759 u8 dma_cmd;
760
761 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
762 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
763
764 /* get DMA command mode */
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +0200765 dma_cmd = inb(hwif->dma_command);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100766 /* stop DMA */
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +0200767 outb(dma_cmd & ~0x1, hwif->dma_command);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100768 hpt370_clear_engine(drive);
769}
770
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771static void hpt370_ide_dma_start(ide_drive_t *drive)
772{
773#ifdef HPT_RESET_STATE_ENGINE
774 hpt370_clear_engine(drive);
775#endif
776 ide_dma_start(drive);
777}
778
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100779static int hpt370_ide_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780{
781 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +0200782 u8 dma_stat = inb(hwif->dma_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783
784 if (dma_stat & 0x01) {
785 /* wait a little */
786 udelay(20);
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +0200787 dma_stat = inb(hwif->dma_status);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100788 if (dma_stat & 0x01)
789 hpt370_irq_timeout(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700791 return __ide_dma_end(drive);
792}
793
Sergei Shtylyovc283f5d2007-07-09 23:17:54 +0200794static void hpt370_dma_timeout(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795{
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100796 hpt370_irq_timeout(drive);
Sergei Shtylyovc283f5d2007-07-09 23:17:54 +0200797 ide_dma_timeout(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798}
799
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800/* returns 1 if DMA IRQ issued, 0 otherwise */
801static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
802{
803 ide_hwif_t *hwif = HWIF(drive);
804 u16 bfifo = 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100805 u8 dma_stat;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700806
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100807 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808 if (bfifo & 0x1FF) {
809// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
810 return 0;
811 }
812
Bartlomiej Zolnierkiewicz0ecdca22007-02-17 02:40:25 +0100813 dma_stat = inb(hwif->dma_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 /* return 1 if INTR asserted */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100815 if (dma_stat & 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816 return 1;
817
818 if (!drive->waiting_for_dma)
819 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
820 drive->name, __FUNCTION__);
821 return 0;
822}
823
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100824static int hpt374_ide_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826 ide_hwif_t *hwif = HWIF(drive);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100827 struct pci_dev *dev = hwif->pci_dev;
828 u8 mcr = 0, mcr_addr = hwif->select_data;
829 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100831 pci_read_config_byte(dev, 0x6a, &bwsr);
832 pci_read_config_byte(dev, mcr_addr, &mcr);
833 if (bwsr & mask)
834 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835 return __ide_dma_end(drive);
836}
837
838/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800839 * hpt3xxn_set_clock - perform clock switching dance
840 * @hwif: hwif to switch
841 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800843 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700844 */
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800845
846static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847{
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +0200848 u8 scr2 = inb(hwif->dma_master + 0x7b);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800849
850 if ((scr2 & 0x7f) == mode)
851 return;
852
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 /* Tristate the bus */
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +0200854 outb(0x80, hwif->dma_master + 0x73);
855 outb(0x80, hwif->dma_master + 0x77);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800856
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857 /* Switch clock and reset channels */
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +0200858 outb(mode, hwif->dma_master + 0x7b);
859 outb(0xc0, hwif->dma_master + 0x79);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800860
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100861 /*
862 * Reset the state machines.
863 * NOTE: avoid accidentally enabling the disabled channels.
864 */
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +0200865 outb(inb(hwif->dma_master + 0x70) | 0x32, hwif->dma_master + 0x70);
866 outb(inb(hwif->dma_master + 0x74) | 0x32, hwif->dma_master + 0x74);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800867
Linus Torvalds1da177e2005-04-16 15:20:36 -0700868 /* Complete reset */
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +0200869 outb(0x00, hwif->dma_master + 0x79);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800870
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871 /* Reconnect channels to bus */
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +0200872 outb(0x00, hwif->dma_master + 0x73);
873 outb(0x00, hwif->dma_master + 0x77);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874}
875
876/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800877 * hpt3xxn_rw_disk - prepare for I/O
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878 * @drive: drive for command
879 * @rq: block request structure
880 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800881 * This is called when a disk I/O is issued to HPT3xxN.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700882 * We need it because of the clock switching.
883 */
884
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800885static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100887 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700888}
889
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890/*
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800891 * Set/get power state for a drive.
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100892 * NOTE: affects both drives on each channel.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700893 *
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800894 * When we turn the power back on, we need to re-initialize things.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700895 */
896#define TRISTATE_BIT 0x8000
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800897
898static int hpt3xx_busproc(ide_drive_t *drive, int state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700899{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100900 ide_hwif_t *hwif = HWIF(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901 struct pci_dev *dev = hwif->pci_dev;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100902 u8 mcr_addr = hwif->select_data + 2;
903 u8 resetmask = hwif->channel ? 0x80 : 0x40;
904 u8 bsr2 = 0;
905 u16 mcr = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700906
907 hwif->bus_state = state;
908
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800909 /* Grab the status. */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100910 pci_read_config_word(dev, mcr_addr, &mcr);
911 pci_read_config_byte(dev, 0x59, &bsr2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800913 /*
914 * Set the state. We don't set it if we don't need to do so.
915 * Make sure that the drive knows that it has failed if it's off.
916 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700917 switch (state) {
918 case BUSSTATE_ON:
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100919 if (!(bsr2 & resetmask))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920 return 0;
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800921 hwif->drives[0].failures = hwif->drives[1].failures = 0;
922
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100923 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
924 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800925 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700926 case BUSSTATE_OFF:
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100927 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700928 return 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100929 mcr &= ~TRISTATE_BIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700930 break;
931 case BUSSTATE_TRISTATE:
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100932 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933 return 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100934 mcr |= TRISTATE_BIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700935 break;
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800936 default:
937 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700939
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800940 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
941 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
942
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100943 pci_write_config_word(dev, mcr_addr, mcr);
944 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700945 return 0;
946}
947
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100948/**
949 * hpt37x_calibrate_dpll - calibrate the DPLL
950 * @dev: PCI device
951 *
952 * Perform a calibration cycle on the DPLL.
953 * Returns 1 if this succeeds
954 */
955static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100957 u32 dpll = (f_high << 16) | f_low | 0x100;
958 u8 scr2;
959 int i;
Alan Coxb39b01f2005-06-27 15:24:27 -0700960
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100961 pci_write_config_dword(dev, 0x5c, dpll);
Alan Coxb39b01f2005-06-27 15:24:27 -0700962
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100963 /* Wait for oscillator ready */
964 for(i = 0; i < 0x5000; ++i) {
965 udelay(50);
966 pci_read_config_byte(dev, 0x5b, &scr2);
967 if (scr2 & 0x80)
Alan Coxb39b01f2005-06-27 15:24:27 -0700968 break;
969 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100970 /* See if it stays ready (we'll just bail out if it's not yet) */
971 for(i = 0; i < 0x1000; ++i) {
972 pci_read_config_byte(dev, 0x5b, &scr2);
973 /* DPLL destabilized? */
974 if(!(scr2 & 0x80))
975 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +0100976 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100977 /* Turn off tuning, we have the DPLL set */
978 pci_read_config_dword (dev, 0x5c, &dpll);
979 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
980 return 1;
Alan Coxb39b01f2005-06-27 15:24:27 -0700981}
982
Linus Torvalds1da177e2005-04-16 15:20:36 -0700983static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
984{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100985 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
986 unsigned long io_base = pci_resource_start(dev, 4);
987 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200988 u8 chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100989 enum ata_clock clock;
990
991 if (info == NULL) {
992 printk(KERN_ERR "%s: out of memory!\n", name);
993 return -ENOMEM;
994 }
995
996 /*
997 * Copy everything from a static "template" structure
998 * to just allocated per-chip hpt_info structure.
999 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001000 memcpy(info, pci_get_drvdata(dev), sizeof(struct hpt_info));
1001 chip_type = info->chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001002
Alan Coxb39b01f2005-06-27 15:24:27 -07001003 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1004 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1005 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1006 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001008 /*
1009 * First, try to estimate the PCI clock frequency...
1010 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001011 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001012 u8 scr1 = 0;
1013 u16 f_cnt = 0;
1014 u32 temp = 0;
Alan Coxb39b01f2005-06-27 15:24:27 -07001015
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001016 /* Interrupt force enable. */
1017 pci_read_config_byte(dev, 0x5a, &scr1);
1018 if (scr1 & 0x10)
1019 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001020
1021 /*
1022 * HighPoint does this for HPT372A.
1023 * NOTE: This register is only writeable via I/O space.
1024 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001025 if (chip_type == HPT372A)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001026 outb(0x0e, io_base + 0x9c);
1027
1028 /*
1029 * Default to PCI clock. Make sure MA15/16 are set to output
1030 * to prevent drives having problems with 40-pin cables.
1031 */
1032 pci_write_config_byte(dev, 0x5b, 0x23);
1033
1034 /*
1035 * We'll have to read f_CNT value in order to determine
1036 * the PCI clock frequency according to the following ratio:
1037 *
1038 * f_CNT = Fpci * 192 / Fdpll
1039 *
1040 * First try reading the register in which the HighPoint BIOS
1041 * saves f_CNT value before reprogramming the DPLL from its
1042 * default setting (which differs for the various chips).
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001043 *
Sergei Shtylyov72931362007-09-11 22:28:35 +02001044 * NOTE: This register is only accessible via I/O space;
1045 * HPT374 BIOS only saves it for the function 0, so we have to
1046 * always read it from there -- no need to check the result of
1047 * pci_get_slot() for the function 0 as the whole device has
1048 * been already "pinned" (via function 1) in init_setup_hpt374()
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001049 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001050 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1051 struct pci_dev *dev1 = pci_get_slot(dev->bus,
1052 dev->devfn - 1);
1053 unsigned long io_base = pci_resource_start(dev1, 4);
1054
1055 temp = inl(io_base + 0x90);
1056 pci_dev_put(dev1);
1057 } else
1058 temp = inl(io_base + 0x90);
1059
1060 /*
1061 * In case the signature check fails, we'll have to
1062 * resort to reading the f_CNT register itself in hopes
1063 * that nobody has touched the DPLL yet...
1064 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001065 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1066 int i;
1067
1068 printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1069 name);
1070
1071 /* Calculate the average value of f_CNT. */
1072 for (temp = i = 0; i < 128; i++) {
1073 pci_read_config_word(dev, 0x78, &f_cnt);
1074 temp += f_cnt & 0x1ff;
1075 mdelay(1);
1076 }
1077 f_cnt = temp / 128;
1078 } else
1079 f_cnt = temp & 0x1ff;
1080
1081 dpll_clk = info->dpll_clk;
1082 pci_clk = (f_cnt * dpll_clk) / 192;
1083
1084 /* Clamp PCI clock to bands. */
1085 if (pci_clk < 40)
1086 pci_clk = 33;
1087 else if(pci_clk < 45)
1088 pci_clk = 40;
1089 else if(pci_clk < 55)
1090 pci_clk = 50;
1091 else
1092 pci_clk = 66;
1093
1094 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1095 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1096 } else {
1097 u32 itr1 = 0;
1098
1099 pci_read_config_dword(dev, 0x40, &itr1);
1100
1101 /* Detect PCI clock by looking at cmd_high_time. */
1102 switch((itr1 >> 8) & 0x07) {
1103 case 0x09:
1104 pci_clk = 40;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001105 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001106 case 0x05:
1107 pci_clk = 25;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001108 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001109 case 0x07:
1110 default:
1111 pci_clk = 33;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001112 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001113 }
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001114 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001115
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001116 /* Let's assume we'll use PCI clock for the ATA clock... */
1117 switch (pci_clk) {
1118 case 25:
1119 clock = ATA_CLOCK_25MHZ;
1120 break;
1121 case 33:
1122 default:
1123 clock = ATA_CLOCK_33MHZ;
1124 break;
1125 case 40:
1126 clock = ATA_CLOCK_40MHZ;
1127 break;
1128 case 50:
1129 clock = ATA_CLOCK_50MHZ;
1130 break;
1131 case 66:
1132 clock = ATA_CLOCK_66MHZ;
1133 break;
1134 }
1135
1136 /*
1137 * Only try the DPLL if we don't have a table for the PCI clock that
1138 * we are running at for HPT370/A, always use it for anything newer...
1139 *
1140 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1141 * We also don't like using the DPLL because this causes glitches
1142 * on PRST-/SRST- when the state engine gets reset...
1143 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001144 if (chip_type >= HPT374 || info->settings[clock] == NULL) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001145 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1146 int adjust;
1147
1148 /*
1149 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1150 * supported/enabled, use 50 MHz DPLL clock otherwise...
1151 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001152 if (info->udma_mask == ATA_UDMA6) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001153 dpll_clk = 66;
1154 clock = ATA_CLOCK_66MHZ;
1155 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1156 dpll_clk = 50;
1157 clock = ATA_CLOCK_50MHZ;
1158 }
1159
1160 if (info->settings[clock] == NULL) {
1161 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1162 kfree(info);
1163 return -EIO;
1164 }
1165
1166 /* Select the DPLL clock. */
1167 pci_write_config_byte(dev, 0x5b, 0x21);
1168
1169 /*
1170 * Adjust the DPLL based upon PCI clock, enable it,
1171 * and wait for stabilization...
1172 */
1173 f_low = (pci_clk * 48) / dpll_clk;
1174
1175 for (adjust = 0; adjust < 8; adjust++) {
1176 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1177 break;
1178
1179 /*
1180 * See if it'll settle at a fractionally different clock
1181 */
1182 if (adjust & 1)
1183 f_low -= adjust >> 1;
1184 else
1185 f_low += adjust >> 1;
1186 }
1187 if (adjust == 8) {
1188 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1189 kfree(info);
1190 return -EIO;
1191 }
1192
1193 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1194 } else {
1195 /* Mark the fact that we're not using the DPLL. */
1196 dpll_clk = 0;
1197
1198 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1199 }
1200
1201 /*
1202 * Advance the table pointer to a slot which points to the list
1203 * of the register values settings matching the clock being used.
1204 */
1205 info->settings += clock;
1206
1207 /* Store the clock frequencies. */
1208 info->dpll_clk = dpll_clk;
1209 info->pci_clk = pci_clk;
1210
1211 /* Point to this chip's own instance of the hpt_info structure. */
1212 pci_set_drvdata(dev, info);
1213
Sergei Shtylyov72931362007-09-11 22:28:35 +02001214 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001215 u8 mcr1, mcr4;
1216
1217 /*
1218 * Reset the state engines.
1219 * NOTE: Avoid accidentally enabling the disabled channels.
1220 */
1221 pci_read_config_byte (dev, 0x50, &mcr1);
1222 pci_read_config_byte (dev, 0x54, &mcr4);
1223 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1224 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1225 udelay(100);
1226 }
1227
1228 /*
1229 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1230 * the MISC. register to stretch the UltraDMA Tss timing.
1231 * NOTE: This register is only writeable via I/O space.
1232 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001233 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001234
1235 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1236
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237 return dev->irq;
1238}
1239
1240static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1241{
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001242 struct pci_dev *dev = hwif->pci_dev;
1243 struct hpt_info *info = pci_get_drvdata(dev);
1244 int serialize = HPT_SERIALIZE_IO;
1245 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1246 u8 chip_type = info->chip_type;
1247 u8 new_mcr, old_mcr = 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001248
1249 /* Cache the channel's MISC. control registers' offset */
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001250 hwif->select_data = hwif->channel ? 0x54 : 0x50;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001251
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +02001252 hwif->set_pio_mode = &hpt3xx_set_pio_mode;
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +02001253 hwif->set_dma_mode = &hpt3xx_set_mode;
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001254 hwif->quirkproc = &hpt3xx_quirkproc;
1255 hwif->intrproc = &hpt3xx_intrproc;
1256 hwif->maskproc = &hpt3xx_maskproc;
1257 hwif->busproc = &hpt3xx_busproc;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001258
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001259 hwif->udma_filter = &hpt3xx_udma_filter;
Sergei Shtylyovb4e44362007-10-11 23:53:58 +02001260 hwif->mdma_filter = &hpt3xx_mdma_filter;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001261
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001262 /*
1263 * HPT3xxN chips have some complications:
1264 *
1265 * - on 33 MHz PCI we must clock switch
1266 * - on 66 MHz PCI we must NOT use the PCI clock
1267 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001268 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001269 /*
1270 * Clock is shared between the channels,
1271 * so we'll have to serialize them... :-(
1272 */
1273 serialize = 1;
1274 hwif->rw_disk = &hpt3xxn_rw_disk;
1275 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001276
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001277 /* Serialize access to this device if needed */
1278 if (serialize && hwif->mate)
1279 hwif->serialized = hwif->mate->serialized = 1;
1280
1281 /*
1282 * Disable the "fast interrupt" prediction. Don't hold off
1283 * on interrupts. (== 0x01 despite what the docs say)
1284 */
1285 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1286
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001287 if (info->chip_type >= HPT374)
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001288 new_mcr = old_mcr & ~0x07;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001289 else if (info->chip_type >= HPT370) {
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001290 new_mcr = old_mcr;
1291 new_mcr &= ~0x02;
1292
1293#ifdef HPT_DELAY_INTERRUPT
1294 new_mcr &= ~0x01;
1295#else
1296 new_mcr |= 0x01;
1297#endif
1298 } else /* HPT366 and HPT368 */
1299 new_mcr = old_mcr & ~0x80;
1300
1301 if (new_mcr != old_mcr)
1302 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1303
Bartlomiej Zolnierkiewicza29ec3b2007-10-16 22:29:52 +02001304 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1305
1306 if (hwif->dma_base == 0)
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001307 return;
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001308
Linus Torvalds1da177e2005-04-16 15:20:36 -07001309 /*
1310 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001311 * address lines to access an external EEPROM. To read valid
Linus Torvalds1da177e2005-04-16 15:20:36 -07001312 * cable detect state the pins must be enabled as inputs.
1313 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001314 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001315 /*
1316 * HPT374 PCI function 1
1317 * - set bit 15 of reg 0x52 to enable TCBLID as input
1318 * - set bit 15 of reg 0x56 to enable FCBLID as input
1319 */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001320 u8 mcr_addr = hwif->select_data + 2;
1321 u16 mcr;
1322
1323 pci_read_config_word (dev, mcr_addr, &mcr);
1324 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001325 /* now read cable id register */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001326 pci_read_config_byte (dev, 0x5a, &scr1);
1327 pci_write_config_word(dev, mcr_addr, mcr);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001328 } else if (chip_type >= HPT370) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001329 /*
1330 * HPT370/372 and 374 pcifn 0
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001331 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
Linus Torvalds1da177e2005-04-16 15:20:36 -07001332 */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001333 u8 scr2 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001334
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001335 pci_read_config_byte (dev, 0x5b, &scr2);
1336 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1337 /* now read cable id register */
1338 pci_read_config_byte (dev, 0x5a, &scr1);
1339 pci_write_config_byte(dev, 0x5b, scr2);
1340 } else
1341 pci_read_config_byte (dev, 0x5a, &scr1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001342
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +02001343 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
1344 hwif->cbl = (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001345
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001346 if (chip_type >= HPT374) {
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001347 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1348 hwif->ide_dma_end = &hpt374_ide_dma_end;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001349 } else if (chip_type >= HPT370) {
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001350 hwif->dma_start = &hpt370_ide_dma_start;
1351 hwif->ide_dma_end = &hpt370_ide_dma_end;
Sergei Shtylyovc283f5d2007-07-09 23:17:54 +02001352 hwif->dma_timeout = &hpt370_dma_timeout;
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001353 } else
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001354 hwif->dma_lost_irq = &hpt366_dma_lost_irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001355}
1356
1357static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1358{
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001359 struct pci_dev *dev = hwif->pci_dev;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001360 u8 masterdma = 0, slavedma = 0;
1361 u8 dma_new = 0, dma_old = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362 unsigned long flags;
1363
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +02001364 dma_old = inb(dmabase + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001365
1366 local_irq_save(flags);
1367
1368 dma_new = dma_old;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001369 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1370 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001371
1372 if (masterdma & 0x30) dma_new |= 0x20;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001373 if ( slavedma & 0x30) dma_new |= 0x40;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374 if (dma_new != dma_old)
Bartlomiej Zolnierkiewicz31e8a462007-10-19 00:30:08 +02001375 outb(dma_new, dmabase + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001376
1377 local_irq_restore(flags);
1378
1379 ide_setup_dma(hwif, dmabase, 8);
1380}
1381
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001382static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001383{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001384 if (dev2->irq != dev->irq) {
1385 /* FIXME: we need a core pci_set_interrupt() */
1386 dev2->irq = dev->irq;
1387 printk(KERN_INFO "HPT374: PCI config space interrupt fixed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001388 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001389}
1390
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001391static void __devinit hpt371_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001392{
Auke Kok44c10132007-06-08 15:46:36 -07001393 u8 mcr1 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001394
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001395 /*
1396 * HPT371 chips physically have only one channel, the secondary one,
1397 * but the primary channel registers do exist! Go figure...
1398 * So, we manually disable the non-existing channel here
1399 * (if the BIOS hasn't done this already).
1400 */
1401 pci_read_config_byte(dev, 0x50, &mcr1);
1402 if (mcr1 & 0x04)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001403 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001404}
1405
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001406static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001407{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001408 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001409
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001410 /*
1411 * Now we'll have to force both channels enabled if
1412 * at least one of them has been enabled by BIOS...
1413 */
1414 pci_read_config_byte(dev, 0x50, &mcr1);
1415 if (mcr1 & 0x30)
1416 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001417
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001418 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1419 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001420
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001421 if (pin1 != pin2 && dev->irq == dev2->irq) {
1422 printk(KERN_INFO "HPT36x: onboard version of chipset, "
1423 "pin1=%d pin2=%d\n", pin1, pin2);
1424 return 1;
1425 }
1426
1427 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001428}
1429
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001430static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1431 { /* 0 */
1432 .name = "HPT36x",
1433 .init_chipset = init_chipset_hpt366,
1434 .init_hwif = init_hwif_hpt366,
1435 .init_dma = init_dma_hpt366,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001436 /*
1437 * HPT36x chips have one channel per function and have
1438 * both channel enable bits located differently and visible
1439 * to both functions -- really stupid design decision... :-(
1440 * Bit 4 is for the primary channel, bit 5 for the secondary.
1441 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001442 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001443 .extra = 240,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001444 .host_flags = IDE_HFLAG_SINGLE |
1445 IDE_HFLAG_NO_ATAPI_DMA |
1446 IDE_HFLAG_OFF_BOARD,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001447 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001448 .mwdma_mask = ATA_MWDMA2,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449 },{ /* 1 */
1450 .name = "HPT372A",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001451 .init_chipset = init_chipset_hpt366,
1452 .init_hwif = init_hwif_hpt366,
1453 .init_dma = init_dma_hpt366,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001454 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001455 .extra = 240,
Bartlomiej Zolnierkiewicz7cab14a2007-10-19 00:30:06 +02001456 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001457 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001458 .mwdma_mask = ATA_MWDMA2,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001459 },{ /* 2 */
1460 .name = "HPT302",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001461 .init_chipset = init_chipset_hpt366,
1462 .init_hwif = init_hwif_hpt366,
1463 .init_dma = init_dma_hpt366,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001464 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001465 .extra = 240,
Bartlomiej Zolnierkiewicz7cab14a2007-10-19 00:30:06 +02001466 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001467 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001468 .mwdma_mask = ATA_MWDMA2,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001469 },{ /* 3 */
1470 .name = "HPT371",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001471 .init_chipset = init_chipset_hpt366,
1472 .init_hwif = init_hwif_hpt366,
1473 .init_dma = init_dma_hpt366,
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001474 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001475 .extra = 240,
Bartlomiej Zolnierkiewicz7cab14a2007-10-19 00:30:06 +02001476 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001477 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001478 .mwdma_mask = ATA_MWDMA2,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001479 },{ /* 4 */
1480 .name = "HPT374",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001481 .init_chipset = init_chipset_hpt366,
1482 .init_hwif = init_hwif_hpt366,
1483 .init_dma = init_dma_hpt366,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001484 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001485 .udma_mask = ATA_UDMA5,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001486 .extra = 240,
Bartlomiej Zolnierkiewicz7cab14a2007-10-19 00:30:06 +02001487 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001488 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001489 .mwdma_mask = ATA_MWDMA2,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001490 },{ /* 5 */
1491 .name = "HPT372N",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001492 .init_chipset = init_chipset_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001493 .init_hwif = init_hwif_hpt366,
1494 .init_dma = init_dma_hpt366,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001495 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001496 .extra = 240,
Bartlomiej Zolnierkiewicz7cab14a2007-10-19 00:30:06 +02001497 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001498 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001499 .mwdma_mask = ATA_MWDMA2,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001500 }
1501};
1502
1503/**
1504 * hpt366_init_one - called when an HPT366 is found
1505 * @dev: the hpt366 device
1506 * @id: the matching pci id
1507 *
1508 * Called when the PCI registration layer (or the IDE initialization)
1509 * finds a device matching our IDE device tables.
1510 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001511static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1512{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001513 struct hpt_info *info = NULL;
1514 struct pci_dev *dev2 = NULL;
1515 ide_pci_device_t d;
1516 u8 idx = id->driver_data;
1517 u8 rev = dev->revision;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001518
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001519 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1520 return -ENODEV;
1521
1522 switch (idx) {
1523 case 0:
1524 if (rev < 3)
1525 info = &hpt36x;
1526 else {
1527 static struct hpt_info *hpt37x_info[] =
1528 { &hpt370, &hpt370a, &hpt372, &hpt372n };
1529
1530 info = hpt37x_info[min_t(u8, rev, 6) - 3];
1531 idx++;
1532 }
1533 break;
1534 case 1:
1535 info = (rev > 1) ? &hpt372n : &hpt372a;
1536 break;
1537 case 2:
1538 info = (rev > 1) ? &hpt302n : &hpt302;
1539 break;
1540 case 3:
1541 hpt371_init(dev);
1542 info = (rev > 1) ? &hpt371n : &hpt371;
1543 break;
1544 case 4:
1545 info = &hpt374;
1546 break;
1547 case 5:
1548 info = &hpt372n;
1549 break;
1550 }
1551
1552 d = hpt366_chipsets[idx];
1553
1554 d.name = info->chip_name;
1555 d.udma_mask = info->udma_mask;
1556
1557 pci_set_drvdata(dev, info);
1558
1559 if (info == &hpt36x || info == &hpt374)
1560 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1561
1562 if (dev2) {
1563 int ret;
1564
1565 pci_set_drvdata(dev2, info);
1566
1567 if (info == &hpt374)
1568 hpt374_init(dev, dev2);
1569 else {
1570 if (hpt36x_init(dev, dev2))
1571 d.host_flags |= IDE_HFLAG_BOOTABLE;
1572 }
1573
1574 ret = ide_setup_pci_devices(dev, dev2, &d);
1575 if (ret < 0)
1576 pci_dev_put(dev2);
1577 return ret;
1578 }
1579
1580 return ide_setup_pci_device(dev, &d);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001581}
1582
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +02001583static const struct pci_device_id hpt366_pci_tbl[] = {
1584 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1585 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1586 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1587 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1588 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1589 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001590 { 0, },
1591};
1592MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1593
1594static struct pci_driver driver = {
1595 .name = "HPT366_IDE",
1596 .id_table = hpt366_pci_tbl,
1597 .probe = hpt366_init_one,
1598};
1599
Bartlomiej Zolnierkiewicz82ab1ee2007-01-27 13:46:56 +01001600static int __init hpt366_ide_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001601{
1602 return ide_pci_register_driver(&driver);
1603}
1604
1605module_init(hpt366_ide_init);
1606
1607MODULE_AUTHOR("Andre Hedrick");
1608MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1609MODULE_LICENSE("GPL");