blob: a9db20815a39152ed130a41ebf9e6c4b79bcb829 [file] [log] [blame]
Alan Coxda9bb1d2006-01-18 17:44:13 -08001#
2# EDAC Kconfig
Doug Thompson4577ca52009-04-02 16:58:43 -07003# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
Alan Coxda9bb1d2006-01-18 17:44:13 -08004# Licensed and distributed under the GPL
5#
Alan Coxda9bb1d2006-01-18 17:44:13 -08006
Jan Engelhardt751cb5e2007-07-15 23:39:27 -07007menuconfig EDAC
GeunSik Lime24aca62009-06-17 16:28:02 -07008 bool "EDAC (Error Detection And Correction) reporting"
Martin Schwidefskye25df122007-05-10 15:45:57 +02009 depends on HAS_IOMEM
Ralf Baechlef65aad42012-10-17 00:39:09 +020010 depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
Alan Coxda9bb1d2006-01-18 17:44:13 -080011 help
12 EDAC is designed to report errors in the core system.
13 These are low-level errors that are reported in the CPU or
Douglas Thompson8cb2a392007-07-19 01:50:12 -070014 supporting chipset or other subsystems:
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
16 If unsure, select 'Y'.
Alan Coxda9bb1d2006-01-18 17:44:13 -080017
Tim Small57c432b2006-03-09 17:33:50 -080018 If this code is reporting problems on your system, please
19 see the EDAC project web pages for more information at:
20
21 <http://bluesmoke.sourceforge.net/>
22
23 and:
24
25 <http://buttersideup.com/edacwiki>
26
27 There is also a mailing list for the EDAC project, which can
28 be found via the sourceforge page.
29
Ralf Baechlef65aad42012-10-17 00:39:09 +020030config EDAC_SUPPORT
31 bool
32
Jan Engelhardt751cb5e2007-07-15 23:39:27 -070033if EDAC
Alan Coxda9bb1d2006-01-18 17:44:13 -080034
35comment "Reporting subsystems"
Alan Coxda9bb1d2006-01-18 17:44:13 -080036
Mauro Carvalho Chehab19974712012-03-21 17:06:53 -030037config EDAC_LEGACY_SYSFS
38 bool "EDAC legacy sysfs"
39 default y
40 help
41 Enable the compatibility sysfs nodes.
42 Use 'Y' if your edac utilities aren't ported to work with the newer
43 structures.
44
Alan Coxda9bb1d2006-01-18 17:44:13 -080045config EDAC_DEBUG
46 bool "Debugging"
Alan Coxda9bb1d2006-01-18 17:44:13 -080047 help
48 This turns on debugging information for the entire EDAC
49 sub-system. You can insert module with "debug_level=x", current
50 there're four debug levels (x=0,1,2,3 from low to high).
51 Usually you should select 'N'.
52
Borislav Petkov9cdeb402010-09-02 18:33:24 +020053config EDAC_DECODE_MCE
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020054 tristate "Decode MCEs in human-readable form (only on AMD for now)"
Borislav Petkov168eb342011-08-10 09:43:30 -030055 depends on CPU_SUP_AMD && X86_MCE_AMD
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020056 default y
57 ---help---
58 Enable this option if you want to decode Machine Check Exceptions
Lucas De Marchi25985ed2011-03-30 22:57:33 -030059 occurring on your machine in human-readable form.
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020060
61 You should definitely say Y here in case you want to decode MCEs
62 which occur really early upon boot, before the module infrastructure
63 has been initialized.
64
Borislav Petkov9cdeb402010-09-02 18:33:24 +020065config EDAC_MCE_INJ
66 tristate "Simple MCE injection interface over /sysfs"
67 depends on EDAC_DECODE_MCE
68 default n
69 help
70 This is a simple interface to inject MCEs over /sysfs and test
71 the MCE decoding code in EDAC.
72
73 This is currently AMD-only.
74
Alan Coxda9bb1d2006-01-18 17:44:13 -080075config EDAC_MM_EDAC
76 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
Alan Coxda9bb1d2006-01-18 17:44:13 -080077 help
78 Some systems are able to detect and correct errors in main
79 memory. EDAC can report statistics on memory error
80 detection and correction (EDAC - or commonly referred to ECC
81 errors). EDAC will also try to decode where these errors
82 occurred so that a particular failing memory module can be
83 replaced. If unsure, select 'Y'.
84
Doug Thompson7d6034d2009-04-27 20:01:01 +020085config EDAC_AMD64
Borislav Petkov027dbd62010-10-13 22:12:15 +020086 tristate "AMD64 (Opteron, Athlon64) K8, F10h"
87 depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
Doug Thompson7d6034d2009-04-27 20:01:01 +020088 help
Borislav Petkov027dbd62010-10-13 22:12:15 +020089 Support for error detection and correction of DRAM ECC errors on
90 the AMD64 families of memory controllers (K8 and F10h)
Doug Thompson7d6034d2009-04-27 20:01:01 +020091
92config EDAC_AMD64_ERROR_INJECTION
Borislav Petkov9cdeb402010-09-02 18:33:24 +020093 bool "Sysfs HW Error injection facilities"
Doug Thompson7d6034d2009-04-27 20:01:01 +020094 depends on EDAC_AMD64
95 help
96 Recent Opterons (Family 10h and later) provide for Memory Error
97 Injection into the ECC detection circuits. The amd64_edac module
98 allows the operator/user to inject Uncorrectable and Correctable
99 errors into DRAM.
100
101 When enabled, in each of the respective memory controller directories
102 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
103
104 - inject_section (0..3, 16-byte section of 64-byte cacheline),
105 - inject_word (0..8, 16-bit word of 16-byte section),
106 - inject_ecc_vector (hex ecc vector: select bits of inject word)
107
108 In addition, there are two control files, inject_read and inject_write,
109 which trigger the DRAM ECC Read and Write respectively.
Alan Coxda9bb1d2006-01-18 17:44:13 -0800110
111config EDAC_AMD76X
112 tristate "AMD 76x (760, 762, 768)"
Dave Jones90cbc452006-02-03 03:04:11 -0800113 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800114 help
115 Support for error detection and correction on the AMD 76x
116 series of chipsets used with the Athlon processor.
117
118config EDAC_E7XXX
119 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800120 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800121 help
122 Support for error detection and correction on the Intel
123 E7205, E7500, E7501 and E7505 server chipsets.
124
125config EDAC_E752X
Andrei Konovalov5135b792008-04-29 01:03:13 -0700126 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
Randy Dunlapda960a62006-03-31 02:30:34 -0800127 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
Alan Coxda9bb1d2006-01-18 17:44:13 -0800128 help
129 Support for error detection and correction on the Intel
130 E7520, E7525, E7320 server chipsets.
131
Tim Small5a2c6752007-07-19 01:49:42 -0700132config EDAC_I82443BXGX
133 tristate "Intel 82443BX/GX (440BX/GX)"
134 depends on EDAC_MM_EDAC && PCI && X86_32
Andrew Morton28f96eea2007-07-19 01:49:45 -0700135 depends on BROKEN
Tim Small5a2c6752007-07-19 01:49:42 -0700136 help
137 Support for error detection and correction on the Intel
138 82443BX/GX memory controllers (440BX/GX chipsets).
139
Alan Coxda9bb1d2006-01-18 17:44:13 -0800140config EDAC_I82875P
141 tristate "Intel 82875p (D82875P, E7210)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800142 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800143 help
144 Support for error detection and correction on the Intel
145 DP82785P and E7210 server chipsets.
146
Ranganathan Desikan420390f2007-07-19 01:50:31 -0700147config EDAC_I82975X
148 tristate "Intel 82975x (D82975x)"
149 depends on EDAC_MM_EDAC && PCI && X86
150 help
151 Support for error detection and correction on the Intel
152 DP82975x server chipsets.
153
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700154config EDAC_I3000
155 tristate "Intel 3000/3010"
Jason Uhlenkottf5c04542008-02-07 00:15:01 -0800156 depends on EDAC_MM_EDAC && PCI && X86
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700157 help
158 Support for error detection and correction on the Intel
159 3000 and 3010 server chipsets.
160
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700161config EDAC_I3200
162 tristate "Intel 3200"
163 depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
164 help
165 Support for error detection and correction on the Intel
166 3200 and 3210 server chipsets.
167
Hitoshi Mitakedf8bc08c2008-10-29 14:00:50 -0700168config EDAC_X38
169 tristate "Intel X38"
170 depends on EDAC_MM_EDAC && PCI && X86
171 help
172 Support for error detection and correction on the Intel
173 X38 server chipsets.
174
Mauro Carvalho Chehab920c8df2009-01-06 14:43:00 -0800175config EDAC_I5400
176 tristate "Intel 5400 (Seaburg) chipsets"
177 depends on EDAC_MM_EDAC && PCI && X86
178 help
179 Support for error detection and correction the Intel
180 i5400 MCH chipset (Seaburg).
181
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300182config EDAC_I7CORE
183 tristate "Intel i7 Core (Nehalem) processors"
Borislav Petkov168eb342011-08-10 09:43:30 -0300184 depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300185 help
186 Support for error detection and correction the Intel
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300187 i7 Core (Nehalem) Integrated Memory Controller that exists on
188 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
189 and Xeon 55xx processors.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300190
Alan Coxda9bb1d2006-01-18 17:44:13 -0800191config EDAC_I82860
192 tristate "Intel 82860"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800193 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800194 help
195 Support for error detection and correction on the Intel
196 82860 chipset.
197
198config EDAC_R82600
199 tristate "Radisys 82600 embedded chipset"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800200 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800201 help
202 Support for error detection and correction on the Radisys
203 82600 embedded chipset.
204
Eric Wolleseneb607052007-07-19 01:49:39 -0700205config EDAC_I5000
206 tristate "Intel Greencreek/Blackford chipset"
207 depends on EDAC_MM_EDAC && X86 && PCI
208 help
209 Support for error detection and correction the Intel
210 Greekcreek/Blackford chipsets.
211
Arthur Jones8f421c592008-07-25 01:49:04 -0700212config EDAC_I5100
213 tristate "Intel San Clemente MCH"
214 depends on EDAC_MM_EDAC && X86 && PCI
215 help
216 Support for error detection and correction the Intel
217 San Clemente MCH.
218
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300219config EDAC_I7300
220 tristate "Intel Clarksboro MCH"
221 depends on EDAC_MM_EDAC && X86 && PCI
222 help
223 Support for error detection and correction the Intel
224 Clarksboro MCH (Intel 7300 chipset).
225
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200226config EDAC_SBRIDGE
227 tristate "Intel Sandy-Bridge Integrated MC"
Hui Wang22a5c272012-02-06 04:10:59 -0300228 depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
229 depends on PCI_MMCONFIG && EXPERIMENTAL
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200230 help
231 Support for error detection and correction the Intel
232 Sandy Bridge Integrated Memory Controller.
233
Dave Jianga9a753d2008-02-07 00:14:55 -0800234config EDAC_MPC85XX
Ira W. Snyderb4846252009-09-23 15:57:25 -0700235 tristate "Freescale MPC83xx / MPC85xx"
Anton Vorontsov1cd85212010-07-20 13:24:27 -0700236 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
Dave Jianga9a753d2008-02-07 00:14:55 -0800237 help
238 Support for error detection and correction on the Freescale
Ira W. Snyderb4846252009-09-23 15:57:25 -0700239 MPC8349, MPC8560, MPC8540, MPC8548
Dave Jianga9a753d2008-02-07 00:14:55 -0800240
Dave Jiang4f4aeea2008-02-07 00:14:56 -0800241config EDAC_MV64X60
242 tristate "Marvell MV64x60"
243 depends on EDAC_MM_EDAC && MV64X60
244 help
245 Support for error detection and correction on the Marvell
246 MV64360 and MV64460 chipsets.
247
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700248config EDAC_PASEMI
249 tristate "PA Semi PWRficient"
250 depends on EDAC_MM_EDAC && PCI
Doug Thompsonddcc3052007-07-26 10:41:16 -0700251 depends on PPC_PASEMI
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700252 help
253 Support for error detection and correction on PA Semi
254 PWRficient.
255
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800256config EDAC_CELL
257 tristate "Cell Broadband Engine memory controller"
Benjamin Krilldef434c2008-11-27 16:15:44 +0100258 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800259 help
260 Support for error detection and correction on the
261 Cell Broadband Engine internal memory controller
262 on platform without a hypervisor
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700263
Grant Ericksondba7a772009-04-02 16:58:45 -0700264config EDAC_PPC4XX
265 tristate "PPC4xx IBM DDR2 Memory Controller"
266 depends on EDAC_MM_EDAC && 4xx
267 help
268 This enables support for EDAC on the ECC memory used
269 with the IBM DDR2 memory controller found in various
270 PowerPC 4xx embedded processors such as the 405EX[r],
271 440SP, 440SPe, 460EX, 460GT and 460SX.
272
Harry Ciaoe8765582009-04-02 16:58:51 -0700273config EDAC_AMD8131
274 tristate "AMD8131 HyperTransport PCI-X Tunnel"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700275 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciaoe8765582009-04-02 16:58:51 -0700276 help
277 Support for error detection and correction on the
278 AMD8131 HyperTransport PCI-X Tunnel chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700279 Note, add more Kconfig dependency if it's adopted
280 on some machine other than Maple.
Harry Ciaoe8765582009-04-02 16:58:51 -0700281
Harry Ciao58b4ce62009-04-02 16:58:51 -0700282config EDAC_AMD8111
283 tristate "AMD8111 HyperTransport I/O Hub"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700284 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciao58b4ce62009-04-02 16:58:51 -0700285 help
286 Support for error detection and correction on the
287 AMD8111 HyperTransport I/O Hub chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700288 Note, add more Kconfig dependency if it's adopted
289 on some machine other than Maple.
Harry Ciao58b4ce62009-04-02 16:58:51 -0700290
Harry Ciao2a9036a2009-06-17 16:27:58 -0700291config EDAC_CPC925
292 tristate "IBM CPC925 Memory Controller (PPC970FX)"
293 depends on EDAC_MM_EDAC && PPC64
294 help
295 Support for error detection and correction on the
296 IBM CPC925 Bridge and Memory Controller, which is
297 a companion chip to the PowerPC 970 family of
298 processors.
299
Chris Metcalf5c770752011-03-01 13:01:49 -0500300config EDAC_TILE
301 tristate "Tilera Memory Controller"
302 depends on EDAC_MM_EDAC && TILE
303 default y
304 help
305 Support for error detection and correction on the
306 Tilera memory controller.
307
Rob Herringa1b01ed2012-06-13 12:01:55 -0500308config EDAC_HIGHBANK_MC
309 tristate "Highbank Memory Controller"
310 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
311 help
312 Support for error detection and correction on the
313 Calxeda Highbank memory controller.
314
Rob Herring69154d02012-06-11 21:32:14 -0500315config EDAC_HIGHBANK_L2
316 tristate "Highbank L2 Cache"
317 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
318 help
319 Support for error detection and correction on the
320 Calxeda Highbank memory controller.
321
Ralf Baechlef65aad42012-10-17 00:39:09 +0200322config EDAC_OCTEON_PC
323 tristate "Cavium Octeon Primary Caches"
324 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
325 help
326 Support for error detection and correction on the primary caches of
327 the cnMIPS cores of Cavium Octeon family SOCs.
328
329config EDAC_OCTEON_L2C
330 tristate "Cavium Octeon Secondary Caches (L2C)"
331 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
332 help
333 Support for error detection and correction on the
334 Cavium Octeon family of SOCs.
335
336config EDAC_OCTEON_LMC
337 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
338 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
339 help
340 Support for error detection and correction on the
341 Cavium Octeon family of SOCs.
342
343config EDAC_OCTEON_PCI
344 tristate "Cavium Octeon PCI Controller"
345 depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON
346 help
347 Support for error detection and correction on the
348 Cavium Octeon family of SOCs.
349
Jan Engelhardt751cb5e2007-07-15 23:39:27 -0700350endif # EDAC