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Alexandru M Stan89bf26c2014-11-26 17:30:27 -08001/*
2 * Copyright 2014 Google, Inc
3 * Author: Alexandru M Stan <amstan@chromium.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/slab.h>
Stephen Boydf684ff82015-06-19 15:00:46 -070017#include <linux/clk.h>
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080018#include <linux/clk-provider.h>
Heiko Stuebner7c494ad2015-07-05 11:00:15 +020019#include <linux/io.h>
20#include <linux/kernel.h>
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080021#include "clk.h"
22
23struct rockchip_mmc_clock {
24 struct clk_hw hw;
25 void __iomem *reg;
26 int id;
27 int shift;
28};
29
30#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
31
32#define RK3288_MMC_CLKGEN_DIV 2
33
34static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
35 unsigned long parent_rate)
36{
37 return parent_rate / RK3288_MMC_CLKGEN_DIV;
38}
39
40#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
41#define ROCKCHIP_MMC_DEGREE_MASK 0x3
42#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
43#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
Shawn Lin7a03fe62015-09-04 08:15:33 +080044#define ROCKCHIP_MMC_INIT_STATE_RESET 0x1
45#define ROCKCHIP_MMC_INIT_STATE_SHIFT 1
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080046
47#define PSECS_PER_SEC 1000000000000LL
48
49/*
Douglas Andersonf0232062015-09-30 16:07:37 +020050 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
51 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080052 */
53#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
54
55static int rockchip_mmc_get_phase(struct clk_hw *hw)
56{
57 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
58 unsigned long rate = clk_get_rate(hw->clk);
59 u32 raw_value;
60 u16 degrees;
61 u32 delay_num = 0;
62
63 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
64
65 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
66
67 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
68 /* degrees/delaynum * 10000 */
69 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
70 36 * (rate / 1000000);
71
72 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
73 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
Douglas Anderson4351f192015-09-30 16:07:38 +020074 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080075 }
76
77 return degrees % 360;
78}
79
80static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
81{
82 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
83 unsigned long rate = clk_get_rate(hw->clk);
84 u8 nineties, remainder;
85 u8 delay_num;
86 u32 raw_value;
Douglas Anderson4351f192015-09-30 16:07:38 +020087 u32 delay;
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080088
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080089 nineties = degrees / 90;
Douglas Andersonf0232062015-09-30 16:07:37 +020090 remainder = (degrees % 90);
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080091
Douglas Andersonf0232062015-09-30 16:07:37 +020092 /*
93 * Due to the inexact nature of the "fine" delay, we might
94 * actually go non-monotonic. We don't go _too_ monotonic
95 * though, so we should be OK. Here are options of how we may
96 * work:
97 *
98 * Ideally we end up with:
99 * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0
100 *
101 * On one extreme (if delay is actually 44ps):
102 * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0
103 * The other (if delay is actually 77ps):
104 * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90
105 *
106 * It's possible we might make a delay that is up to 25
107 * degrees off from what we think we're making. That's OK
108 * though because we should be REALLY far from any bad range.
109 */
110
111 /*
112 * Convert to delay; do a little extra work to make sure we
113 * don't overflow 32-bit / 64-bit numbers.
114 */
Douglas Anderson4351f192015-09-30 16:07:38 +0200115 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800116 delay *= remainder;
Douglas Anderson4351f192015-09-30 16:07:38 +0200117 delay = DIV_ROUND_CLOSEST(delay,
118 (rate / 1000) * 36 *
119 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
Douglas Andersonf0232062015-09-30 16:07:37 +0200120
Douglas Anderson4351f192015-09-30 16:07:38 +0200121 delay_num = (u8) min_t(u32, delay, 255);
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800122
123 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
124 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
125 raw_value |= nineties;
Heiko Stuebner03ae1742016-04-19 21:29:27 +0200126 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),
127 mmc_clock->reg);
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800128
129 pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
Stephen Boyd836ee0f2015-08-12 11:42:23 -0700130 clk_hw_get_name(hw), degrees, delay_num,
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800131 mmc_clock->reg, raw_value>>(mmc_clock->shift),
132 rockchip_mmc_get_phase(hw)
133 );
134
135 return 0;
136}
137
138static const struct clk_ops rockchip_mmc_clk_ops = {
139 .recalc_rate = rockchip_mmc_recalc,
140 .get_phase = rockchip_mmc_get_phase,
141 .set_phase = rockchip_mmc_set_phase,
142};
143
144struct clk *rockchip_clk_register_mmc(const char *name,
Uwe Kleine-König4a1caed2015-05-28 10:45:51 +0200145 const char *const *parent_names, u8 num_parents,
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800146 void __iomem *reg, int shift)
147{
148 struct clk_init_data init;
149 struct rockchip_mmc_clock *mmc_clock;
150 struct clk *clk;
151
152 mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
153 if (!mmc_clock)
Shawn Lin022dce02016-02-15 11:33:41 +0800154 return ERR_PTR(-ENOMEM);
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800155
Heiko Stuebner7c494ad2015-07-05 11:00:15 +0200156 init.name = name;
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800157 init.num_parents = num_parents;
158 init.parent_names = parent_names;
159 init.ops = &rockchip_mmc_clk_ops;
160
161 mmc_clock->hw.init = &init;
162 mmc_clock->reg = reg;
163 mmc_clock->shift = shift;
164
Shawn Lin7a03fe62015-09-04 08:15:33 +0800165 /*
166 * Assert init_state to soft reset the CLKGEN
167 * for mmc tuning phase and degree
168 */
169 if (mmc_clock->shift == ROCKCHIP_MMC_INIT_STATE_SHIFT)
170 writel(HIWORD_UPDATE(ROCKCHIP_MMC_INIT_STATE_RESET,
171 ROCKCHIP_MMC_INIT_STATE_RESET,
172 mmc_clock->shift), mmc_clock->reg);
173
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800174 clk = clk_register(NULL, &mmc_clock->hw);
175 if (IS_ERR(clk))
Shawn Lin022dce02016-02-15 11:33:41 +0800176 kfree(mmc_clock);
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800177
178 return clk;
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800179}