Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / android_kernel_shift_sdm845 / d93ec5628929aa40e885184c599e053d915cd510 / . / drivers / clk / msm / clock-gcc-8952.c
blob: 7da217cc9aafa746528bf9d7b958a689eadc7112 [file] [log] [blame]
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]1/*
2 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/err.h>
17#include <linux/ctype.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/clk.h>
21#include <linux/regulator/consumer.h>
22#include <linux/platform_device.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <soc/qcom/clock-local2.h>
27#include <soc/qcom/clock-pll.h>
28#include <soc/qcom/clock-alpha-pll.h>
29#include <soc/qcom/clock-voter.h>
30#include <soc/qcom/rpm-smd.h>
31#include <soc/qcom/clock-rpm.h>
32
33#include <linux/clk/msm-clock-generic.h>
34#include <linux/regulator/rpm-smd-regulator.h>
35
36#include <dt-bindings/clock/msm-clocks-8952.h>
37#include <dt-bindings/clock/msm-clocks-hwio-8952.h>
38
39#include "clock.h"
40#include "reset.h"
41
42enum {
43 GCC_BASE,
44 APCS_C1_PLL_BASE,
45 APCS_C0_PLL_BASE,
46 APCS_CCI_PLL_BASE,
47 N_BASES,
48};
49
50static void __iomem *virt_bases[N_BASES];
51#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
52
53static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
54
55/* SMD clocks */
56DEFINE_CLK_RPM_SMD_BRANCH(xo_clk_src, xo_a_clk_src, RPM_MISC_CLK_TYPE,
57 CXO_CLK_SRC_ID, 19200000);
58DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_CLK_ID, NULL);
59DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_CLK_ID, NULL);
60DEFINE_CLK_RPM_SMD(bimc_gpu_clk, bimc_gpu_a_clk, RPM_MEM_CLK_TYPE,
61 BIMC_GPU_CLK_ID, NULL);
62DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_CLK_ID, NULL);
63DEFINE_CLK_RPM_SMD(sysmmnoc_clk, sysmmnoc_a_clk, RPM_BUS_CLK_TYPE,
64 SYSMMNOC_CLK_ID, NULL);
65DEFINE_CLK_RPM_SMD(ipa_clk, ipa_a_clk, RPM_IPA_CLK_TYPE, IPA_CLK_ID, NULL);
66DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_CLK_ID);
67
68/* SMD_XO_BUFFER */
69DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk1, bb_clk1_a, BB_CLK1_ID);
70DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk2, bb_clk2_a, BB_CLK2_ID);
71DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk2, rf_clk2_a, RF_CLK2_ID);
72DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_clk2_a, DIV_CLK2_ID);
73
74DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk1_pin, bb_clk1_a_pin, BB_CLK1_ID);
75DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk2_pin, bb_clk2_a_pin, BB_CLK2_ID);
76
77/* Voter clocks */
78static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
79static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
80static DEFINE_CLK_VOTER(sysmmnoc_msmbus_clk, &sysmmnoc_clk.c, LONG_MAX);
81static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
82
83static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
84static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
85static DEFINE_CLK_VOTER(sysmmnoc_msmbus_a_clk, &sysmmnoc_a_clk.c, LONG_MAX);
86static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
87static DEFINE_CLK_VOTER(pnoc_keepalive_a_clk, &pnoc_a_clk.c, LONG_MAX);
88
89static DEFINE_CLK_VOTER(pnoc_usb_a_clk, &pnoc_a_clk.c, LONG_MAX);
90static DEFINE_CLK_VOTER(snoc_usb_a_clk, &snoc_a_clk.c, LONG_MAX);
91static DEFINE_CLK_VOTER(bimc_usb_a_clk, &bimc_a_clk.c, LONG_MAX);
92
93static DEFINE_CLK_VOTER(pnoc_usb_clk, &pnoc_clk.c, LONG_MAX);
94static DEFINE_CLK_VOTER(snoc_usb_clk, &snoc_clk.c, LONG_MAX);
95static DEFINE_CLK_VOTER(bimc_usb_clk, &bimc_clk.c, LONG_MAX);
96
97static DEFINE_CLK_VOTER(snoc_wcnss_a_clk, &snoc_a_clk.c, LONG_MAX);
98static DEFINE_CLK_VOTER(bimc_wcnss_a_clk, &bimc_a_clk.c, LONG_MAX);
99
100/* Branch Voter clocks */
101static DEFINE_CLK_BRANCH_VOTER(xo_gcc, &xo_clk_src.c);
102static DEFINE_CLK_BRANCH_VOTER(xo_otg_clk, &xo_clk_src.c);
103static DEFINE_CLK_BRANCH_VOTER(xo_lpm_clk, &xo_clk_src.c);
104static DEFINE_CLK_BRANCH_VOTER(xo_pil_pronto_clk, &xo_clk_src.c);
105static DEFINE_CLK_BRANCH_VOTER(xo_pil_mss_clk, &xo_clk_src.c);
106static DEFINE_CLK_BRANCH_VOTER(xo_wlan_clk, &xo_clk_src.c);
107static DEFINE_CLK_BRANCH_VOTER(xo_pil_lpass_clk, &xo_clk_src.c);
108
109DEFINE_CLK_DUMMY(wcnss_m_clk, 0);
110
111enum vdd_sr2_pll_levels {
112 VDD_SR2_PLL_OFF,
113 VDD_SR2_PLL_SVS,
114 VDD_SR2_PLL_NOM,
115 VDD_SR2_PLL_TUR,
116 VDD_SR2_PLL_SUPER_TUR,
117 VDD_SR2_PLL_NUM,
118};
119
120static int vdd_sr2_levels[] = {
121 0, RPM_REGULATOR_LEVEL_NONE, /* VDD_SR2_PLL_OFF */
122 1800000, RPM_REGULATOR_LEVEL_SVS, /* VDD_SR2_PLL_SVS */
123 1800000, RPM_REGULATOR_LEVEL_NOM, /* VDD_SR2_PLL_NOM */
124 1800000, RPM_REGULATOR_LEVEL_TURBO, /* VDD_SR2_PLL_TUR */
125 1800000, RPM_REGULATOR_LEVEL_BINNING, /* VDD_SR2_PLL_SUPER_TUR */
126};
127
128static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_SR2_PLL_NUM, 2,
129 vdd_sr2_levels, NULL);
130
131enum vdd_hf_pll_levels {
132 VDD_HF_PLL_OFF,
133 VDD_HF_PLL_SVS,
134 VDD_HF_PLL_NOM,
135 VDD_HF_PLL_TUR,
136 VDD_HF_PLL_SUPER_TUR,
137 VDD_HF_PLL_NUM,
138};
139
140static int vdd_hf_levels[] = {
141 0, RPM_REGULATOR_LEVEL_NONE, /* VDD_HF_PLL_OFF */
142 1800000, RPM_REGULATOR_LEVEL_SVS, /* VDD_HF_PLL_SVS */
143 1800000, RPM_REGULATOR_LEVEL_NOM, /* VDD_HF_PLL_NOM */
144 1800000, RPM_REGULATOR_LEVEL_TURBO, /* VDD_HF_PLL_TUR */
145 1800000, RPM_REGULATOR_LEVEL_BINNING, /* VDD_HF_PLL_SUPER_TUR */
146};
147static DEFINE_VDD_REGULATORS(vdd_hf_pll, VDD_HF_PLL_NUM, 2,
148 vdd_hf_levels, NULL);
149
150static struct pll_freq_tbl apcs_cci_pll_freq[] = {
151 F_APCS_PLL(307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
152 F_APCS_PLL(600000000, 31, 0x1, 0x4, 0x0, 0x0, 0x0),
153};
154
155static struct pll_clk a53ss_cci_pll = {
156 .mode_reg = (void __iomem *)APCS_CCI_PLL_MODE,
157 .l_reg = (void __iomem *)APCS_CCI_PLL_L_VAL,
158 .m_reg = (void __iomem *)APCS_CCI_PLL_M_VAL,
159 .n_reg = (void __iomem *)APCS_CCI_PLL_N_VAL,
160 .config_reg = (void __iomem *)APCS_CCI_PLL_USER_CTL,
161 .status_reg = (void __iomem *)APCS_CCI_PLL_STATUS,
162 .freq_tbl = apcs_cci_pll_freq,
163 .masks = {
164 .vco_mask = BM(29, 28),
165 .pre_div_mask = BIT(12),
166 .post_div_mask = BM(9, 8),
167 .mn_en_mask = BIT(24),
168 .main_output_mask = BIT(0),
169 },
170 .base = &virt_bases[APCS_CCI_PLL_BASE],
171 .spm_ctrl = {
172 .offset = 0x40,
173 .event_bit = 0x0,
174 },
175 .c = {
176 .parent = &xo_a_clk_src.c,
177 .dbg_name = "a53ss_cci_pll",
178 .ops = &clk_ops_sr2_pll,
179 .vdd_class = &vdd_sr2_pll,
180 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
181 [VDD_SR2_PLL_SVS] = 1000000000,
182 [VDD_SR2_PLL_NOM] = 1900000000,
183 },
184 .num_fmax = VDD_SR2_PLL_NUM,
185 CLK_INIT(a53ss_cci_pll.c),
186 },
187};
188
189static struct pll_freq_tbl apcs_c0_pll_freq[] = {
190 F_APCS_PLL( 249600000, 13, 0x0, 0x1, 0x0, 0x0, 0x0),
191 F_APCS_PLL( 307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
192 F_APCS_PLL( 345600000, 18, 0x0, 0x1, 0x0, 0x0, 0x0),
193 F_APCS_PLL( 384000000, 20, 0x0, 0x1, 0x0, 0x0, 0x0),
194 F_APCS_PLL( 460800000, 24, 0x0, 0x1, 0x0, 0x0, 0x0),
195 F_APCS_PLL( 499200000, 26, 0x0, 0x1, 0x0, 0x0, 0x0),
196 F_APCS_PLL( 518400000, 27, 0x0, 0x1, 0x0, 0x0, 0x0),
197 F_APCS_PLL( 768000000, 40, 0x0, 0x1, 0x0, 0x0, 0x0),
198 F_APCS_PLL( 806400000, 42, 0x0, 0x1, 0x0, 0x0, 0x0),
199 F_APCS_PLL( 844800000, 44, 0x0, 0x1, 0x0, 0x0, 0x0),
200 F_APCS_PLL( 883200000, 46, 0x0, 0x1, 0x0, 0x0, 0x0),
201 F_APCS_PLL( 902400000, 47, 0x0, 0x1, 0x0, 0x0, 0x0),
202 F_APCS_PLL( 921600000, 48, 0x0, 0x1, 0x0, 0x0, 0x0),
203 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
204 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
205 F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),
206};
207
208static struct pll_clk a53ss_c0_pll = {
209 .mode_reg = (void __iomem *)APCS_C0_PLL_MODE,
210 .l_reg = (void __iomem *)APCS_C0_PLL_L_VAL,
211 .m_reg = (void __iomem *)APCS_C0_PLL_M_VAL,
212 .n_reg = (void __iomem *)APCS_C0_PLL_N_VAL,
213 .config_reg = (void __iomem *)APCS_C0_PLL_USER_CTL,
214 .status_reg = (void __iomem *)APCS_C0_PLL_STATUS,
215 .freq_tbl = apcs_c0_pll_freq,
216 .masks = {
217 .vco_mask = BM(29, 28),
218 .pre_div_mask = BIT(12),
219 .post_div_mask = BM(9, 8),
220 .mn_en_mask = BIT(24),
221 .main_output_mask = BIT(0),
222 },
223 .base = &virt_bases[APCS_C0_PLL_BASE],
224 .spm_ctrl = {
225 .offset = 0x50,
226 .event_bit = 0x4,
227 },
228 .c = {
229 .parent = &xo_a_clk_src.c,
230 .dbg_name = "a53ss_c0_pll",
231 .ops = &clk_ops_sr2_pll,
232 .vdd_class = &vdd_sr2_pll,
233 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
234 [VDD_SR2_PLL_SVS] = 1000000000,
235 [VDD_SR2_PLL_NOM] = 1900000000,
236 },
237 .num_fmax = VDD_SR2_PLL_NUM,
238 CLK_INIT(a53ss_c0_pll.c),
239 },
240};
241
242static struct pll_freq_tbl apcs_c1_pll_freq[] = {
243 F_APCS_PLL( 345600000, 18, 0x0, 0x1, 0x0, 0x0, 0x0),
244 F_APCS_PLL( 422400000, 22, 0x0, 0x1, 0x0, 0x0, 0x0),
245 F_APCS_PLL( 499200000, 26, 0x0, 0x1, 0x0, 0x0, 0x0),
246 F_APCS_PLL( 652800000, 34, 0x0, 0x1, 0x0, 0x0, 0x0),
247 F_APCS_PLL( 729600000, 38, 0x0, 0x1, 0x0, 0x0, 0x0),
248 F_APCS_PLL( 806400000, 42, 0x0, 0x1, 0x0, 0x0, 0x0),
249 F_APCS_PLL( 844800000, 44, 0x0, 0x1, 0x0, 0x0, 0x0),
250 F_APCS_PLL( 883200000, 46, 0x0, 0x1, 0x0, 0x0, 0x0),
251 F_APCS_PLL( 960000000, 50, 0x0, 0x1, 0x0, 0x0, 0x0),
252 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
253 F_APCS_PLL(1036800000, 54, 0x0, 0x1, 0x0, 0x0, 0x0),
254 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
255 F_APCS_PLL(1113600000, 58, 0x0, 0x1, 0x0, 0x0, 0x0),
256 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
257 F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),
258 F_APCS_PLL(1248000000, 65, 0x0, 0x1, 0x0, 0x0, 0x0),
259 F_APCS_PLL(1267200000, 66, 0x0, 0x1, 0x0, 0x0, 0x0),
260 F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0),
261 F_APCS_PLL(1401000000, 73, 0x0, 0x1, 0x0, 0x0, 0x0),
262 F_APCS_PLL(1420800000, 74, 0x0, 0x1, 0x0, 0x0, 0x0),
263 F_APCS_PLL(1440000000, 75, 0x0, 0x1, 0x0, 0x0, 0x0),
264 F_APCS_PLL(1459200000, 76, 0x0, 0x1, 0x0, 0x0, 0x0),
265 F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0),
266 F_APCS_PLL(1516800000, 79, 0x0, 0x1, 0x0, 0x0, 0x0),
267 F_APCS_PLL(1536000000, 80, 0x0, 0x1, 0x0, 0x0, 0x0),
268 F_APCS_PLL(1651200000, 86, 0x0, 0x1, 0x0, 0x0, 0x0),
269};
270
271static struct pll_clk a53ss_c1_pll = {
272 .mode_reg = (void __iomem *)APCS_C1_PLL_MODE,
273 .l_reg = (void __iomem *)APCS_C1_PLL_L_VAL,
274 .m_reg = (void __iomem *)APCS_C1_PLL_M_VAL,
275 .n_reg = (void __iomem *)APCS_C1_PLL_N_VAL,
276 .config_reg = (void __iomem *)APCS_C1_PLL_USER_CTL,
277 .status_reg = (void __iomem *)APCS_C1_PLL_STATUS,
278 .freq_tbl = apcs_c1_pll_freq,
279 .masks = {
280 .vco_mask = BM(29, 28),
281 .pre_div_mask = BIT(12),
282 .post_div_mask = BM(9, 8),
283 .mn_en_mask = BIT(24),
284 .main_output_mask = BIT(0),
285 },
286 .base = &virt_bases[APCS_C1_PLL_BASE],
287 .spm_ctrl = {
288 .offset = 0x50,
289 .event_bit = 0x4,
290 },
291 .c = {
292 .parent = &xo_a_clk_src.c,
293 .dbg_name = "a53ss_c1_pll",
294 .ops = &clk_ops_sr2_pll,
295 .vdd_class = &vdd_hf_pll,
296 .fmax = (unsigned long [VDD_HF_PLL_NUM]) {
297 [VDD_HF_PLL_SVS] = 1000000000,
298 [VDD_HF_PLL_NOM] = 2000000000,
299 },
300 .num_fmax = VDD_HF_PLL_NUM,
301 CLK_INIT(a53ss_c1_pll.c),
302 },
303};
304
305static struct pll_vote_clk gpll0_sleep_clk_src = {
306 .en_reg = (void __iomem *)APCS_CLOCK_SLEEP_ENA_VOTE,
307 .en_mask = BIT(23),
308 .status_reg = (void __iomem *)GPLL0_MODE,
309 .status_mask = BIT(30),
310 .base = &virt_bases[GCC_BASE],
311 .c = {
312 .parent = &xo_clk_src.c,
313 .rate = 800000000,
314 .dbg_name = "gpll0_sleep_clk_src",
315 .ops = &clk_ops_pll_sleep_vote,
316 CLK_INIT(gpll0_sleep_clk_src.c),
317 },
318};
319
320static unsigned int soft_vote_gpll0;
321
322/* PLL_ACTIVE_FLAG bit of GCC_GPLL0_MODE register
323 * gets set from PLL voting FSM.It indicates when
324 * FSM has enabled the PLL and PLL should be locked.
325 */
326static struct pll_vote_clk gpll0_clk_src_8952 = {
327 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
328 .en_mask = BIT(0),
329 .status_reg = (void __iomem *)GPLL0_STATUS,
330 .status_mask = BIT(17),
331 .soft_vote = &soft_vote_gpll0,
332 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
333 .base = &virt_bases[GCC_BASE],
334 .c = {
335 .parent = &xo_clk_src.c,
336 .rate = 800000000,
337 .dbg_name = "gpll0_clk_src_8952",
338 .ops = &clk_ops_pll_acpu_vote,
339 CLK_INIT(gpll0_clk_src_8952.c),
340 },
341};
342
343static struct pll_vote_clk gpll0_clk_src_8937 = {
344 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
345 .en_mask = BIT(0),
346 .status_reg = (void __iomem *)GPLL0_MODE,
347 .status_mask = BIT(30),
348 .soft_vote = &soft_vote_gpll0,
349 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
350 .base = &virt_bases[GCC_BASE],
351 .c = {
352 .parent = &gpll0_sleep_clk_src.c,
353 .rate = 800000000,
354 .dbg_name = "gpll0_clk_src_8937",
355 .ops = &clk_ops_pll_acpu_vote,
356 CLK_INIT(gpll0_clk_src_8937.c),
357 },
358};
359
360DEFINE_EXT_CLK(gpll0_clk_src, NULL);
361DEFINE_EXT_CLK(gpll0_ao_clk_src, NULL);
362DEFINE_EXT_CLK(gpll0_out_aux_clk_src, &gpll0_clk_src.c);
363DEFINE_EXT_CLK(gpll0_out_main_clk_src, &gpll0_clk_src.c);
364DEFINE_EXT_CLK(ext_pclk0_clk_src, NULL);
365DEFINE_EXT_CLK(ext_byte0_clk_src, NULL);
366DEFINE_EXT_CLK(ext_pclk1_clk_src, NULL);
367DEFINE_EXT_CLK(ext_byte1_clk_src, NULL);
368
369/* Don't vote for xo if using this clock to allow xo shutdown */
370static struct pll_vote_clk gpll0_ao_clk_src_8952 = {
371 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
372 .en_mask = BIT(0),
373 .status_reg = (void __iomem *)GPLL0_STATUS,
374 .status_mask = BIT(17),
375 .soft_vote = &soft_vote_gpll0,
376 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
377 .base = &virt_bases[GCC_BASE],
378 .c = {
379 .parent = &xo_a_clk_src.c,
380 .rate = 800000000,
381 .dbg_name = "gpll0_ao_clk_src_8952",
382 .ops = &clk_ops_pll_acpu_vote,
383 CLK_INIT(gpll0_ao_clk_src_8952.c),
384 },
385};
386
387static struct pll_vote_clk gpll0_ao_clk_src_8937 = {
388 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
389 .en_mask = BIT(0),
390 .status_reg = (void __iomem *)GPLL0_MODE,
391 .status_mask = BIT(30),
392 .soft_vote = &soft_vote_gpll0,
393 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
394 .base = &virt_bases[GCC_BASE],
395 .c = {
396 .parent = &xo_a_clk_src.c,
397 .rate = 800000000,
398 .dbg_name = "gpll0_ao_clk_src_8937",
399 .ops = &clk_ops_pll_acpu_vote,
400 CLK_INIT(gpll0_ao_clk_src_8937.c),
401 },
402};
403
404static struct pll_vote_clk gpll6_clk_src = {
405 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
406 .en_mask = BIT(7),
407 .status_reg = (void __iomem *)GPLL6_STATUS,
408 .status_mask = BIT(17),
409 .base = &virt_bases[GCC_BASE],
410 .c = {
411 .parent = &xo_clk_src.c,
412 .rate = 1080000000,
413 .dbg_name = "gpll6_clk_src",
414 .ops = &clk_ops_pll_vote,
415 CLK_INIT(gpll6_clk_src.c),
416 },
417};
418
419DEFINE_EXT_CLK(gpll6_aux_clk_src, &gpll6_clk_src.c);
420DEFINE_EXT_CLK(gpll6_out_main_clk_src, &gpll6_clk_src.c);
421
422static struct alpha_pll_masks pll_masks_p = {
423 .lock_mask = BIT(31),
424 .active_mask = BIT(30),
425 .vco_mask = BM(21, 20) >> 20,
426 .vco_shift = 20,
427 .alpha_en_mask = BIT(24),
428 .output_mask = 0xf,
429 .update_mask = BIT(22),
430 .post_div_mask = BM(11, 8),
431 .test_ctl_lo_mask = BM(31, 0),
432 .test_ctl_hi_mask = BM(31, 0),
433};
434
435/* Slewing plls won't allow to change vco_sel.
436 * Hence will have only one vco table entry
437 */
438static struct alpha_pll_vco_tbl p_vco[] = {
439 VCO(0, 700000000, 1400000000),
440};
441
442/* Slewing plls won't allow to change vco_sel.
443 * Hence will have only one vco table entry
444 */
445static struct alpha_pll_vco_tbl p_vco_8937[] = {
446 VCO(1, 525000000, 1066000000),
447};
448
449static struct alpha_pll_clk gpll3_clk_src = {
450 .masks = &pll_masks_p,
451 .base = &virt_bases[GCC_BASE],
452 .offset = GPLL3_MODE,
453 .vco_tbl = p_vco,
454 .num_vco = ARRAY_SIZE(p_vco),
455 .enable_config = 1,
456 /*
457 * gpll3 is dedicated to oxili and has a fuse implementation for
458 * post divider to limit frequency. HW with fuse blown has a divider
459 * value set to 2. So lets stick to divide by 2 in software to avoid
460 * conflicts.
461 */
462 .post_div_config = 1 << 8,
463 .slew = true,
464 .config_ctl_val = 0x4001055b,
465 .test_ctl_hi_val = 0x40000600,
466 .c = {
467 .rate = 1050000000,
468 .parent = &xo_clk_src.c,
469 .dbg_name = "gpll3_clk_src",
470 .ops = &clk_ops_dyna_alpha_pll,
471 VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),
472 CLK_INIT(gpll3_clk_src.c),
473 },
474};
475
476static struct pll_vote_clk gpll4_clk_src = {
477 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
478 .en_mask = BIT(5),
479 .status_reg = (void __iomem *)GPLL4_MODE,
480 .status_mask = BIT(30),
481 .base = &virt_bases[GCC_BASE],
482 .c = {
483 .rate = 1152000000,
484 .parent = &xo_clk_src.c,
485 .dbg_name = "gpll4_clk_src",
486 .ops = &clk_ops_pll_vote,
487 VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),
488 CLK_INIT(gpll4_clk_src.c),
489 },
490};
491DEFINE_EXT_CLK(gpll4_out_clk_src, &gpll4_clk_src.c);
492
493static struct clk_freq_tbl ftbl_gcc_camss_top_ahb_clk[] = {
494 F( 40000000, gpll0, 10, 1, 2),
495 F( 61540000, gpll0, 13, 0, 0),
496 F( 80000000, gpll0, 10, 0, 0),
497 F_END
498};
499
500static struct rcg_clk camss_top_ahb_clk_src = {
501 .cmd_rcgr_reg = CAMSS_TOP_AHB_CMD_RCGR,
502 .set_rate = set_rate_mnd,
503 .freq_tbl = ftbl_gcc_camss_top_ahb_clk,
504 .current_freq = &rcg_dummy_freq,
505 .base = &virt_bases[GCC_BASE],
506 .c = {
507 .dbg_name = "camss_top_ahb_clk_src",
508 .ops = &clk_ops_rcg_mnd,
509 VDD_DIG_FMAX_MAP3(LOWER, 40000000, LOW, 61540000,
510 NOMINAL, 80000000),
511 CLK_INIT(camss_top_ahb_clk_src.c),
512 },
513};
514
515static struct clk_freq_tbl ftbl_gcc_apss_ahb_clk[] = {
516 F( 19200000, xo_a, 1, 0, 0),
517 F( 50000000, gpll0, 16, 0, 0),
518 F( 100000000, gpll0, 8, 0, 0),
519 F( 133330000, gpll0, 6, 0, 0),
520 F_END
521};
522
523static struct rcg_clk apss_ahb_clk_src = {
524 .cmd_rcgr_reg = APSS_AHB_CMD_RCGR,
525 .set_rate = set_rate_hid,
526 .freq_tbl = ftbl_gcc_apss_ahb_clk,
527 .current_freq = &rcg_dummy_freq,
528 .base = &virt_bases[GCC_BASE],
529 .c = {
530 .dbg_name = "apss_ahb_clk_src",
531 .ops = &clk_ops_rcg,
532 CLK_INIT(apss_ahb_clk_src.c),
533 },
534};
535
536static struct clk_freq_tbl ftbl_gcc_camss_csi0_2_clk[] = {
537 F( 100000000, gpll0, 8, 0, 0),
538 F( 160000000, gpll0, 5, 0, 0),
539 F( 200000000, gpll0, 4, 0, 0),
540 F_END
541};
542
543static struct clk_freq_tbl ftbl_gcc_camss_csi0_2_clk_8937[] = {
544 F( 100000000, gpll0, 8, 0, 0),
545 F( 160000000, gpll0, 5, 0, 0),
546 F( 200000000, gpll0, 4, 0, 0),
547 F( 266670000, gpll0, 3, 0, 0),
548 F_END
549};
550
551
552static struct rcg_clk csi0_clk_src = {
553 .cmd_rcgr_reg = CSI0_CMD_RCGR,
554 .set_rate = set_rate_hid,
555 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
556 .current_freq = &rcg_dummy_freq,
557 .base = &virt_bases[GCC_BASE],
558 .c = {
559 .dbg_name = "csi0_clk_src",
560 .ops = &clk_ops_rcg,
561 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
562 NOMINAL, 200000000),
563 CLK_INIT(csi0_clk_src.c),
564 },
565};
566
567static struct rcg_clk csi1_clk_src = {
568 .cmd_rcgr_reg = CSI1_CMD_RCGR,
569 .set_rate = set_rate_hid,
570 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
571 .current_freq = &rcg_dummy_freq,
572 .base = &virt_bases[GCC_BASE],
573 .c = {
574 .dbg_name = "csi1_clk_src",
575 .ops = &clk_ops_rcg,
576 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
577 NOMINAL, 200000000),
578 CLK_INIT(csi1_clk_src.c),
579 },
580};
581
582static struct rcg_clk csi2_clk_src = {
583 .cmd_rcgr_reg = CSI2_CMD_RCGR,
584 .set_rate = set_rate_hid,
585 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
586 .current_freq = &rcg_dummy_freq,
587 .base = &virt_bases[GCC_BASE],
588 .c = {
589 .dbg_name = "csi2_clk_src",
590 .ops = &clk_ops_rcg,
591 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
592 NOMINAL, 200000000),
593 CLK_INIT(csi2_clk_src.c),
594 },
595};
596
597static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
598 F( 133330000, gpll0, 6, 0, 0),
599 F( 180000000, gpll6, 6, 0, 0),
600 F( 228570000, gpll0, 3.5, 0, 0),
601 F( 266670000, gpll0, 3, 0, 0),
602 F( 308570000, gpll6, 3.5, 0, 0),
603 F_END
604};
605
606static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk_8937[] = {
607 F( 166150000, gpll6, 6.5, 0, 0),
608 F( 240000000, gpll6, 4.5, 0, 0),
609 F( 308570000, gpll6, 3.5, 0, 0),
610 F( 320000000, gpll0, 2.5, 0, 0),
611 F( 360000000, gpll6, 3, 0, 0),
612 F_END
613};
614
615static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk_8917[] = {
616 F( 160000000, gpll0, 5, 0, 0),
617 F( 200000000, gpll0, 4, 0, 0),
618 F( 270000000, gpll6, 4, 0, 0),
619 F( 308570000, gpll6, 3.5, 0, 0),
620 F( 329140000, gpll4_out, 3.5, 0, 0),
621 F( 360000000, gpll6, 3, 0, 0),
622 F_END
623};
624
625static struct rcg_clk vcodec0_clk_src = {
626 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
627 .set_rate = set_rate_mnd,
628 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
629 .current_freq = &rcg_dummy_freq,
630 .base = &virt_bases[GCC_BASE],
631 .c = {
632 .dbg_name = "vcodec0_clk_src",
633 .ops = &clk_ops_rcg_mnd,
634 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 180000000,
635 NOMINAL, 228570000, NOM_PLUS, 266670000,
636 HIGH, 308570000),
637 CLK_INIT(vcodec0_clk_src.c),
638 },
639};
640
641static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk[] = {
642 F( 50000000, gpll0, 16, 0, 0),
643 F( 80000000, gpll0, 10, 0, 0),
644 F( 100000000, gpll0, 8, 0, 0),
645 F( 133330000, gpll0, 6, 0, 0),
646 F( 160000000, gpll0, 5, 0, 0),
647 F( 177780000, gpll0, 4.5, 0, 0),
648 F( 200000000, gpll0, 4, 0, 0),
649 F( 266670000, gpll0, 3, 0, 0),
650 F( 308570000, gpll6, 3.5, 0, 0),
651 F( 320000000, gpll0, 2.5, 0, 0),
652 F( 360000000, gpll6, 3, 0, 0),
653 F_END
654};
655
656static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk_8937[] = {
657 F( 50000000, gpll0, 16, 0, 0),
658 F( 80000000, gpll0, 10, 0, 0),
659 F( 100000000, gpll0, 8, 0, 0),
660 F( 133333333, gpll0, 6, 0, 0),
661 F( 160000000, gpll0, 5, 0, 0),
662 F( 177780000, gpll0, 4.5, 0, 0),
663 F( 200000000, gpll0, 4, 0, 0),
664 F( 266670000, gpll0, 3, 0, 0),
665 F( 308570000, gpll6, 3.5, 0, 0),
666 F( 320000000, gpll0, 2.5, 0, 0),
667 F( 360000000, gpll6, 3, 0, 0),
668 F( 400000000, gpll0, 2, 0, 0),
669 F( 432000000, gpll6, 2.5, 0, 0),
670 F_END
671};
672
673static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk_8917[] = {
674 F( 50000000, gpll0, 16, 0, 0),
675 F( 80000000, gpll0, 10, 0, 0),
676 F( 100000000, gpll0, 8, 0, 0),
677 F( 133333333, gpll0, 6, 0, 0),
678 F( 160000000, gpll0, 5, 0, 0),
679 F( 177780000, gpll0, 4.5, 0, 0),
680 F( 200000000, gpll0, 4, 0, 0),
681 F( 266670000, gpll0, 3, 0, 0),
682 F( 308570000, gpll6, 3.5, 0, 0),
683 F( 320000000, gpll0, 2.5, 0, 0),
684 F( 329140000, gpll4_out, 3.5, 0, 0),
685 F( 360000000, gpll6, 3, 0, 0),
686 F_END
687};
688
689static struct rcg_clk vfe0_clk_src = {
690 .cmd_rcgr_reg = VFE0_CMD_RCGR,
691 .set_rate = set_rate_hid,
692 .freq_tbl = ftbl_gcc_camss_vfe0_1_clk,
693 .current_freq = &rcg_dummy_freq,
694 .base = &virt_bases[GCC_BASE],
695 .c = {
696 .dbg_name = "vfe0_clk_src",
697 .ops = &clk_ops_rcg,
698 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 266670000,
699 NOMINAL, 308570000, NOM_PLUS, 320000000,
700 HIGH, 360000000),
701 CLK_INIT(vfe0_clk_src.c),
702 },
703};
704
705static struct rcg_clk vfe1_clk_src = {
706 .cmd_rcgr_reg = VFE1_CMD_RCGR,
707 .set_rate = set_rate_hid,
708 .freq_tbl = ftbl_gcc_camss_vfe0_1_clk,
709 .current_freq = &rcg_dummy_freq,
710 .base = &virt_bases[GCC_BASE],
711 .c = {
712 .dbg_name = "vfe1_clk_src",
713 .ops = &clk_ops_rcg,
714 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 266670000,
715 NOMINAL, 308570000, NOM_PLUS, 320000000,
716 HIGH, 360000000),
717 CLK_INIT(vfe1_clk_src.c),
718 },
719};
720
721static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
722 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
723 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
724 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
725 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
726 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
727 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
728 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
729 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
730 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
731 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
732 F_SLEW( 465000000, 930000000, gpll3, 1, 0, 0),
733 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
734 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
735 F_END
736};
737
738static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937[] = {
739 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
740 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
741 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
742 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
743 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
744 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
745 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
746 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
747 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
748 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
749 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
750 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
751 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
752 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
753 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
754 F_END
755};
756
757static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937_475MHz[] = {
758 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
759 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
760 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
761 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
762 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
763 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
764 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
765 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
766 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
767 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
768 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
769 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
770 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
771 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
772 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
773 F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0),
774 F_END
775};
776
777static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8940_500MHz[] = {
778 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
779 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
780 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
781 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
782 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
783 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
784 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
785 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
786 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
787 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
788 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
789 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
790 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
791 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
792 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
793 F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0),
794 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
795 F_END
796};
797
798static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917[] = {
799 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
800 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
801 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
802 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
803 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
804 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
805 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
806 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
807 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
808 F_SLEW( 270000000, FIXED_CLK_SRC, gpll6_aux, 4, 0, 0),
809 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
810 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
811 F_SLEW( 484800000, 969600000, gpll3, 1, 0, 0),
812 F_SLEW( 523200000, 1046400000, gpll3, 1, 0, 0),
813 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
814 F_SLEW( 598000000, 1196000000, gpll3, 1, 0, 0),
815 F_END
816};
817
818static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917_650MHz[] = {
819 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
820 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
821 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
822 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
823 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
824 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
825 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
826 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
827 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
828 F_SLEW( 270000000, FIXED_CLK_SRC, gpll6_aux, 4, 0, 0),
829 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
830 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
831 F_SLEW( 484800000, 969600000, gpll3, 1, 0, 0),
832 F_SLEW( 523200000, 1046400000, gpll3, 1, 0, 0),
833 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
834 F_SLEW( 598000000, 1196000000, gpll3, 1, 0, 0),
835 F_SLEW( 650000000, 1300000000, gpll3, 1, 0, 0),
836 F_END
837};
838
839static struct rcg_clk gfx3d_clk_src = {
840 .cmd_rcgr_reg = GFX3D_CMD_RCGR,
841 .set_rate = set_rate_hid,
842 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
843 .current_freq = &rcg_dummy_freq,
844 .base = &virt_bases[GCC_BASE],
845 .c = {
846 .dbg_name = "gfx3d_clk_src",
847 .ops = &clk_ops_rcg,
848 VDD_DIG_FMAX_MAP5(LOWER, 240000000, LOW, 400000000,
849 NOMINAL, 465000000, NOM_PLUS, 500000000,
850 HIGH, 550000000),
851 CLK_INIT(gfx3d_clk_src.c),
852 },
853};
854
855static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk[] = {
856 F( 19200000, xo, 1, 0, 0),
857 F( 50000000, gpll0, 16, 0, 0),
858 F_END
859};
860
861static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
862 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
863 .set_rate = set_rate_hid,
864 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
865 .current_freq = &rcg_dummy_freq,
866 .base = &virt_bases[GCC_BASE],
867 .c = {
868 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
869 .ops = &clk_ops_rcg,
870 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
871 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
872 },
873};
874
875static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk[] = {
876 F( 960000, xo, 10, 1, 2),
877 F( 4800000, xo, 4, 0, 0),
878 F( 9600000, xo, 2, 0, 0),
879 F( 16000000, gpll0, 10, 1, 5),
880 F( 19200000, xo, 1, 0, 0),
881 F( 25000000, gpll0, 16, 1, 2),
882 F( 50000000, gpll0, 16, 0, 0),
883 F_END
884};
885
886static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917[] = {
887 F( 960000, xo, 10, 1, 2),
888 F( 4800000, xo, 4, 0, 0),
889 F( 9600000, xo, 2, 0, 0),
890 F( 16000000, gpll0, 10, 1, 5),
891 F( 19200000, xo, 1, 0, 0),
892 F( 25000000, gpll0, 16, 1, 2),
893 F( 40000000, gpll0, 10, 1, 2),
894 F( 50000000, gpll0, 16, 0, 0),
895 F_END
896};
897
898static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
899 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
900 .set_rate = set_rate_mnd,
901 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
902 .current_freq = &rcg_dummy_freq,
903 .base = &virt_bases[GCC_BASE],
904 .c = {
905 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
906 .ops = &clk_ops_rcg_mnd,
907 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
908 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
909 },
910};
911
912static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
913 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
914 .set_rate = set_rate_hid,
915 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
916 .current_freq = &rcg_dummy_freq,
917 .base = &virt_bases[GCC_BASE],
918 .c = {
919 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
920 .ops = &clk_ops_rcg,
921 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
922 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
923 },
924};
925
926static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
927 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
928 .set_rate = set_rate_mnd,
929 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
930 .current_freq = &rcg_dummy_freq,
931 .base = &virt_bases[GCC_BASE],
932 .c = {
933 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
934 .ops = &clk_ops_rcg_mnd,
935 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
936 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
937 },
938};
939
940static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
941 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
942 .set_rate = set_rate_hid,
943 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
944 .current_freq = &rcg_dummy_freq,
945 .base = &virt_bases[GCC_BASE],
946 .c = {
947 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
948 .ops = &clk_ops_rcg,
949 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
950 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
951 },
952};
953
954static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
955 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
956 .set_rate = set_rate_mnd,
957 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
958 .current_freq = &rcg_dummy_freq,
959 .base = &virt_bases[GCC_BASE],
960 .c = {
961 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
962 .ops = &clk_ops_rcg_mnd,
963 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
964 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
965 },
966};
967
968static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
969 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
970 .set_rate = set_rate_hid,
971 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
972 .current_freq = &rcg_dummy_freq,
973 .base = &virt_bases[GCC_BASE],
974 .c = {
975 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
976 .ops = &clk_ops_rcg,
977 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
978 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
979 },
980};
981
982static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
983 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
984 .set_rate = set_rate_mnd,
985 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
986 .current_freq = &rcg_dummy_freq,
987 .base = &virt_bases[GCC_BASE],
988 .c = {
989 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
990 .ops = &clk_ops_rcg_mnd,
991 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
992 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
993 },
994};
995
996static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] = {
997 F( 3686400, gpll0, 1, 72, 15625),
998 F( 7372800, gpll0, 1, 144, 15625),
999 F( 14745600, gpll0, 1, 288, 15625),
1000 F( 16000000, gpll0, 10, 1, 5),
1001 F( 19200000, xo, 1, 0, 0),
1002 F( 24000000, gpll0, 1, 3, 100),
1003 F( 25000000, gpll0, 16, 1, 2),
1004 F( 32000000, gpll0, 1, 1, 25),
1005 F( 40000000, gpll0, 1, 1, 20),
1006 F( 46400000, gpll0, 1, 29, 500),
1007 F( 48000000, gpll0, 1, 3, 50),
1008 F( 51200000, gpll0, 1, 8, 125),
1009 F( 56000000, gpll0, 1, 7, 100),
1010 F( 58982400, gpll0, 1, 1152, 15625),
1011 F( 60000000, gpll0, 1, 3, 40),
1012 F( 64000000, gpll0, 1, 2, 25),
1013 F_END
1014};
1015
1016static struct rcg_clk blsp1_uart1_apps_clk_src = {
1017 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
1018 .set_rate = set_rate_mnd,
1019 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1020 .current_freq = &rcg_dummy_freq,
1021 .base = &virt_bases[GCC_BASE],
1022 .c = {
1023 .dbg_name = "blsp1_uart1_apps_clk_src",
1024 .ops = &clk_ops_rcg_mnd,
1025 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1026 CLK_INIT(blsp1_uart1_apps_clk_src.c),
1027 },
1028};
1029
1030static struct rcg_clk blsp1_uart2_apps_clk_src = {
1031 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
1032 .set_rate = set_rate_mnd,
1033 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1034 .current_freq = &rcg_dummy_freq,
1035 .base = &virt_bases[GCC_BASE],
1036 .c = {
1037 .dbg_name = "blsp1_uart2_apps_clk_src",
1038 .ops = &clk_ops_rcg_mnd,
1039 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1040 CLK_INIT(blsp1_uart2_apps_clk_src.c),
1041 },
1042};
1043
1044static struct rcg_clk blsp2_qup1_i2c_apps_clk_src = {
1045 .cmd_rcgr_reg = BLSP2_QUP1_I2C_APPS_CMD_RCGR,
1046 .set_rate = set_rate_hid,
1047 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1048 .current_freq = &rcg_dummy_freq,
1049 .base = &virt_bases[GCC_BASE],
1050 .c = {
1051 .dbg_name = "blsp2_qup1_i2c_apps_clk_src",
1052 .ops = &clk_ops_rcg,
1053 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1054 CLK_INIT(blsp2_qup1_i2c_apps_clk_src.c),
1055 },
1056};
1057
1058static struct rcg_clk blsp2_qup1_spi_apps_clk_src = {
1059 .cmd_rcgr_reg = BLSP2_QUP1_SPI_APPS_CMD_RCGR,
1060 .set_rate = set_rate_mnd,
1061 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1062 .current_freq = &rcg_dummy_freq,
1063 .base = &virt_bases[GCC_BASE],
1064 .c = {
1065 .dbg_name = "blsp2_qup1_spi_apps_clk_src",
1066 .ops = &clk_ops_rcg_mnd,
1067 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1068 CLK_INIT(blsp2_qup1_spi_apps_clk_src.c),
1069 },
1070};
1071
1072static struct rcg_clk blsp2_qup2_i2c_apps_clk_src = {
1073 .cmd_rcgr_reg = BLSP2_QUP2_I2C_APPS_CMD_RCGR,
1074 .set_rate = set_rate_hid,
1075 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1076 .current_freq = &rcg_dummy_freq,
1077 .base = &virt_bases[GCC_BASE],
1078 .c = {
1079 .dbg_name = "blsp2_qup2_i2c_apps_clk_src",
1080 .ops = &clk_ops_rcg,
1081 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1082 CLK_INIT(blsp2_qup2_i2c_apps_clk_src.c),
1083 },
1084};
1085
1086static struct rcg_clk blsp2_qup2_spi_apps_clk_src = {
1087 .cmd_rcgr_reg = BLSP2_QUP2_SPI_APPS_CMD_RCGR,
1088 .set_rate = set_rate_mnd,
1089 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1090 .current_freq = &rcg_dummy_freq,
1091 .base = &virt_bases[GCC_BASE],
1092 .c = {
1093 .dbg_name = "blsp2_qup2_spi_apps_clk_src",
1094 .ops = &clk_ops_rcg_mnd,
1095 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1096 CLK_INIT(blsp2_qup2_spi_apps_clk_src.c),
1097 },
1098};
1099
1100static struct rcg_clk blsp2_qup3_i2c_apps_clk_src = {
1101 .cmd_rcgr_reg = BLSP2_QUP3_I2C_APPS_CMD_RCGR,
1102 .set_rate = set_rate_hid,
1103 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1104 .current_freq = &rcg_dummy_freq,
1105 .base = &virt_bases[GCC_BASE],
1106 .c = {
1107 .dbg_name = "blsp2_qup3_i2c_apps_clk_src",
1108 .ops = &clk_ops_rcg,
1109 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1110 CLK_INIT(blsp2_qup3_i2c_apps_clk_src.c),
1111 },
1112};
1113
1114static struct rcg_clk blsp2_qup3_spi_apps_clk_src = {
1115 .cmd_rcgr_reg = BLSP2_QUP3_SPI_APPS_CMD_RCGR,
1116 .set_rate = set_rate_mnd,
1117 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1118 .current_freq = &rcg_dummy_freq,
1119 .base = &virt_bases[GCC_BASE],
1120 .c = {
1121 .dbg_name = "blsp2_qup3_spi_apps_clk_src",
1122 .ops = &clk_ops_rcg_mnd,
1123 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1124 CLK_INIT(blsp2_qup3_spi_apps_clk_src.c),
1125 },
1126};
1127
1128static struct rcg_clk blsp2_qup4_i2c_apps_clk_src = {
1129 .cmd_rcgr_reg = BLSP2_QUP4_I2C_APPS_CMD_RCGR,
1130 .set_rate = set_rate_hid,
1131 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1132 .current_freq = &rcg_dummy_freq,
1133 .base = &virt_bases[GCC_BASE],
1134 .c = {
1135 .dbg_name = "blsp2_qup4_i2c_apps_clk_src",
1136 .ops = &clk_ops_rcg,
1137 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1138 CLK_INIT(blsp2_qup4_i2c_apps_clk_src.c),
1139 },
1140};
1141
1142static struct rcg_clk blsp2_qup4_spi_apps_clk_src = {
1143 .cmd_rcgr_reg = BLSP2_QUP4_SPI_APPS_CMD_RCGR,
1144 .set_rate = set_rate_mnd,
1145 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1146 .current_freq = &rcg_dummy_freq,
1147 .base = &virt_bases[GCC_BASE],
1148 .c = {
1149 .dbg_name = "blsp2_qup4_spi_apps_clk_src",
1150 .ops = &clk_ops_rcg_mnd,
1151 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1152 CLK_INIT(blsp2_qup4_spi_apps_clk_src.c),
1153 },
1154};
1155
1156static struct rcg_clk blsp2_uart1_apps_clk_src = {
1157 .cmd_rcgr_reg = BLSP2_UART1_APPS_CMD_RCGR,
1158 .set_rate = set_rate_mnd,
1159 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1160 .current_freq = &rcg_dummy_freq,
1161 .base = &virt_bases[GCC_BASE],
1162 .c = {
1163 .dbg_name = "blsp2_uart1_apps_clk_src",
1164 .ops = &clk_ops_rcg_mnd,
1165 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1166 CLK_INIT(blsp2_uart1_apps_clk_src.c),
1167 },
1168};
1169
1170static struct rcg_clk blsp2_uart2_apps_clk_src = {
1171 .cmd_rcgr_reg = BLSP2_UART2_APPS_CMD_RCGR,
1172 .set_rate = set_rate_mnd,
1173 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1174 .current_freq = &rcg_dummy_freq,
1175 .base = &virt_bases[GCC_BASE],
1176 .c = {
1177 .dbg_name = "blsp2_uart2_apps_clk_src",
1178 .ops = &clk_ops_rcg_mnd,
1179 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1180 CLK_INIT(blsp2_uart2_apps_clk_src.c),
1181 },
1182};
1183
1184static struct clk_freq_tbl ftbl_gcc_camss_cci_clk[] = {
1185 F( 19200000, xo, 1, 0, 0),
1186 F( 37500000, gpll0_out_aux, 1, 3, 64),
1187 F_END
1188};
1189
1190static struct rcg_clk cci_clk_src = {
1191 .cmd_rcgr_reg = CCI_CMD_RCGR,
1192 .set_rate = set_rate_mnd,
1193 .freq_tbl = ftbl_gcc_camss_cci_clk,
1194 .current_freq = &rcg_dummy_freq,
1195 .base = &virt_bases[GCC_BASE],
1196 .c = {
1197 .dbg_name = "cci_clk_src",
1198 .ops = &clk_ops_rcg_mnd,
1199 VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 37500000),
1200 CLK_INIT(cci_clk_src.c),
1201 },
1202};
1203
1204static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk[] = {
1205 F( 133330000, gpll0, 6, 0, 0),
1206 F( 180000000, gpll6, 6, 0, 0),
1207 F( 266670000, gpll0, 3, 0, 0),
1208 F( 308570000, gpll6, 3.5, 0, 0),
1209 F( 320000000, gpll0, 2.5, 0, 0),
1210 F_END
1211};
1212
1213static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk_8937[] = {
1214 F( 133333333, gpll0, 6, 0, 0),
1215 F( 160000000, gpll0, 5, 0, 0),
1216 F( 200000000, gpll0, 4, 0, 0),
1217 F( 266666667, gpll0, 3, 0, 0),
1218 F( 308570000, gpll6, 3.5, 0, 0),
1219 F( 320000000, gpll0, 2.5, 0, 0),
1220 F( 360000000, gpll6, 3, 0, 0),
1221 F_END
1222};
1223
1224static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk_8917[] = {
1225 F( 133330000, gpll0, 6, 0, 0),
1226 F( 160000000, gpll0, 5, 0, 0),
1227 F( 266670000, gpll0, 3, 0, 0),
1228 F( 308570000, gpll6, 3.5, 0, 0),
1229 F( 320000000, gpll0, 2.5, 0, 0),
1230 F( 360000000, gpll6, 3, 0, 0),
1231 F_END
1232};
1233
1234static struct rcg_clk cpp_clk_src = {
1235 .cmd_rcgr_reg = CPP_CMD_RCGR,
1236 .set_rate = set_rate_hid,
1237 .freq_tbl = ftbl_gcc_camss_cpp_clk,
1238 .current_freq = &rcg_dummy_freq,
1239 .base = &virt_bases[GCC_BASE],
1240 .c = {
1241 .dbg_name = "cpp_clk_src",
1242 .ops = &clk_ops_rcg,
1243 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 180000000,
1244 NOMINAL, 266670000, NOM_PLUS, 308570000,
1245 HIGH, 320000000),
1246 CLK_INIT(cpp_clk_src.c),
1247 },
1248};
1249
1250static struct clk_freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
1251 F( 100000000, gpll0, 8, 0, 0),
1252 F( 160000000, gpll0, 5, 0, 0),
1253 F( 200000000, gpll0, 4, 0, 0),
1254 F_END
1255};
1256
1257static struct rcg_clk camss_gp0_clk_src = {
1258 .cmd_rcgr_reg = MM_GP0_CMD_RCGR,
1259 .set_rate = set_rate_mnd,
1260 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1261 .current_freq = &rcg_dummy_freq,
1262 .base = &virt_bases[GCC_BASE],
1263 .c = {
1264 .dbg_name = "camss_gp0_clk_src",
1265 .ops = &clk_ops_rcg_mnd,
1266 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1267 NOMINAL, 200000000),
1268 CLK_INIT(camss_gp0_clk_src.c),
1269 },
1270};
1271
1272static struct rcg_clk camss_gp1_clk_src = {
1273 .cmd_rcgr_reg = MM_GP1_CMD_RCGR,
1274 .set_rate = set_rate_mnd,
1275 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1276 .current_freq = &rcg_dummy_freq,
1277 .base = &virt_bases[GCC_BASE],
1278 .c = {
1279 .dbg_name = "camss_gp1_clk_src",
1280 .ops = &clk_ops_rcg_mnd,
1281 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1282 NOMINAL, 200000000),
1283 CLK_INIT(camss_gp1_clk_src.c),
1284 },
1285};
1286
1287static struct clk_freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
1288 F( 133330000, gpll0, 6, 0, 0),
1289 F( 266670000, gpll0, 3, 0, 0),
1290 F( 320000000, gpll0, 2.5, 0, 0),
1291 F_END
1292};
1293
1294static struct clk_freq_tbl ftbl_gcc_camss_jpeg0_clk_8937[] = {
1295 F( 133333333, gpll0, 6, 0, 0),
1296 F( 200000000, gpll0, 4, 0, 0),
1297 F( 266666667, gpll0, 3, 0, 0),
1298 F( 308570000, gpll6, 3.5, 0, 0),
1299 F( 320000000, gpll0, 2.5, 0, 0),
1300 F_END
1301};
1302
1303static struct rcg_clk jpeg0_clk_src = {
1304 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1305 .set_rate = set_rate_hid,
1306 .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
1307 .current_freq = &rcg_dummy_freq,
1308 .base = &virt_bases[GCC_BASE],
1309 .c = {
1310 .dbg_name = "jpeg0_clk_src",
1311 .ops = &clk_ops_rcg,
1312 VDD_DIG_FMAX_MAP3(LOWER, 133330000, NOMINAL, 266670000,
1313 HIGH, 320000000),
1314 CLK_INIT(jpeg0_clk_src.c),
1315 },
1316};
1317
1318static struct clk_freq_tbl ftbl_gcc_camss_mclk0_2_clk[] = {
1319 F( 19200000, xo, 1, 0, 0),
1320 F( 24000000, gpll6, 1, 1, 45),
1321 F( 66670000, gpll0, 12, 0, 0),
1322 F_END
1323};
1324
1325static struct rcg_clk mclk0_clk_src = {
1326 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1327 .set_rate = set_rate_mnd,
1328 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1329 .current_freq = &rcg_dummy_freq,
1330 .base = &virt_bases[GCC_BASE],
1331 .c = {
1332 .dbg_name = "mclk0_clk_src",
1333 .ops = &clk_ops_rcg_mnd,
1334 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1335 CLK_INIT(mclk0_clk_src.c),
1336 },
1337};
1338
1339static struct rcg_clk mclk1_clk_src = {
1340 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1341 .set_rate = set_rate_mnd,
1342 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1343 .current_freq = &rcg_dummy_freq,
1344 .base = &virt_bases[GCC_BASE],
1345 .c = {
1346 .dbg_name = "mclk1_clk_src",
1347 .ops = &clk_ops_rcg_mnd,
1348 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1349 CLK_INIT(mclk1_clk_src.c),
1350 },
1351};
1352
1353static struct rcg_clk mclk2_clk_src = {
1354 .cmd_rcgr_reg = MCLK2_CMD_RCGR,
1355 .set_rate = set_rate_mnd,
1356 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1357 .current_freq = &rcg_dummy_freq,
1358 .base = &virt_bases[GCC_BASE],
1359 .c = {
1360 .dbg_name = "mclk2_clk_src",
1361 .ops = &clk_ops_rcg_mnd,
1362 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1363 CLK_INIT(mclk2_clk_src.c),
1364 },
1365};
1366
1367static struct clk_freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
1368 F( 100000000, gpll0, 8, 0, 0),
1369 F( 160000000, gpll0, 5, 0, 0),
1370 F( 200000000, gpll0, 4, 0, 0),
1371 F_END
1372};
1373
1374static struct clk_freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk_8917[] = {
1375 F( 100000000, gpll0, 8, 0, 0),
1376 F( 160000000, gpll0, 5, 0, 0),
1377 F( 200000000, gpll0, 4, 0, 0),
1378 F( 266670000, gpll0, 3, 0, 0),
1379 F_END
1380};
1381
1382static struct rcg_clk csi0phytimer_clk_src = {
1383 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
1384 .set_rate = set_rate_hid,
1385 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1386 .current_freq = &rcg_dummy_freq,
1387 .base = &virt_bases[GCC_BASE],
1388 .c = {
1389 .dbg_name = "csi0phytimer_clk_src",
1390 .ops = &clk_ops_rcg,
1391 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1392 NOMINAL, 200000000),
1393 CLK_INIT(csi0phytimer_clk_src.c),
1394 },
1395};
1396
1397static struct rcg_clk csi1phytimer_clk_src = {
1398 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
1399 .set_rate = set_rate_hid,
1400 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1401 .current_freq = &rcg_dummy_freq,
1402 .base = &virt_bases[GCC_BASE],
1403 .c = {
1404 .dbg_name = "csi1phytimer_clk_src",
1405 .ops = &clk_ops_rcg,
1406 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1407 NOMINAL, 200000000),
1408 CLK_INIT(csi1phytimer_clk_src.c),
1409 },
1410};
1411
1412static struct clk_freq_tbl ftbl_gcc_crypto_clk[] = {
1413 F( 50000000, gpll0, 16, 0, 0),
1414 F( 80000000, gpll0, 10, 0, 0),
1415 F( 100000000, gpll0, 8, 0, 0),
1416 F( 160000000, gpll0, 5, 0, 0),
1417 F_END
1418};
1419
1420static struct rcg_clk crypto_clk_src = {
1421 .cmd_rcgr_reg = CRYPTO_CMD_RCGR,
1422 .set_rate = set_rate_hid,
1423 .freq_tbl = ftbl_gcc_crypto_clk,
1424 .current_freq = &rcg_dummy_freq,
1425 .base = &virt_bases[GCC_BASE],
1426 .c = {
1427 .dbg_name = "crypto_clk_src",
1428 .ops = &clk_ops_rcg,
1429 VDD_DIG_FMAX_MAP2(LOWER, 80000000, NOMINAL, 160000000),
1430 CLK_INIT(crypto_clk_src.c),
1431 },
1432};
1433
1434static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
1435 F( 19200000, xo, 1, 0, 0),
1436 F_END
1437};
1438
1439static struct rcg_clk gp1_clk_src = {
1440 .cmd_rcgr_reg = GP1_CMD_RCGR,
1441 .set_rate = set_rate_mnd,
1442 .freq_tbl = ftbl_gcc_gp1_3_clk,
1443 .current_freq = &rcg_dummy_freq,
1444 .base = &virt_bases[GCC_BASE],
1445 .c = {
1446 .dbg_name = "gp1_clk_src",
1447 .ops = &clk_ops_rcg_mnd,
1448 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1449 CLK_INIT(gp1_clk_src.c),
1450 },
1451};
1452
1453static struct rcg_clk gp2_clk_src = {
1454 .cmd_rcgr_reg = GP2_CMD_RCGR,
1455 .set_rate = set_rate_mnd,
1456 .freq_tbl = ftbl_gcc_gp1_3_clk,
1457 .current_freq = &rcg_dummy_freq,
1458 .base = &virt_bases[GCC_BASE],
1459 .c = {
1460 .dbg_name = "gp2_clk_src",
1461 .ops = &clk_ops_rcg_mnd,
1462 VDD_DIG_FMAX_MAP1(LOW, 19200000),
1463 CLK_INIT(gp2_clk_src.c),
1464 },
1465};
1466
1467static struct rcg_clk gp3_clk_src = {
1468 .cmd_rcgr_reg = GP3_CMD_RCGR,
1469 .set_rate = set_rate_mnd,
1470 .freq_tbl = ftbl_gcc_gp1_3_clk,
1471 .current_freq = &rcg_dummy_freq,
1472 .base = &virt_bases[GCC_BASE],
1473 .c = {
1474 .dbg_name = "gp3_clk_src",
1475 .ops = &clk_ops_rcg_mnd,
1476 VDD_DIG_FMAX_MAP1(LOW, 19200000),
1477 CLK_INIT(gp3_clk_src.c),
1478 },
1479};
1480
1481static struct clk_freq_tbl ftbl_gcc_mdss_byte0_clk[] = {
1482 {
1483 .div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
1484 | BVAL(4, 0, 0),
1485 .src_clk = &ext_byte0_clk_src.c,
1486 .freq_hz = 0,
1487 },
1488 F_END
1489};
1490
1491static struct clk_freq_tbl ftbl_gcc_mdss_byte0_clk_8937[] = {
1492 {
1493 .div_src_val = BVAL(10, 8, xo_source_val)
1494 | BVAL(4, 0, 0),
1495 .src_clk = &xo_clk_src.c,
1496 .freq_hz = 0,
1497 },
1498 {
1499 .div_src_val = BVAL(10, 8, dsi0_0phypll_source_val)
1500 | BVAL(4, 0, 0),
1501 .src_clk = &ext_byte0_clk_src.c,
1502 .freq_hz = 0,
1503 },
1504 {
1505 .div_src_val = BVAL(10, 8, dsi1_0phypll_source_val)
1506 | BVAL(4, 0, 0),
1507 .src_clk = &ext_byte1_clk_src.c,
1508 .freq_hz = 0,
1509 },
1510 F_END
1511};
1512
1513static struct rcg_clk byte0_clk_src = {
1514 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
1515 .set_rate = set_rate_hid,
1516 .current_freq = ftbl_gcc_mdss_byte0_clk,
1517 .freq_tbl = ftbl_gcc_mdss_byte0_clk,
1518 .base = &virt_bases[GCC_BASE],
1519 .c = {
1520 .dbg_name = "byte0_clk_src",
1521 .ops = &clk_ops_byte_multiparent,
1522 .flags = CLKFLAG_NO_RATE_CACHE,
1523 VDD_DIG_FMAX_MAP2(LOWER, 120000000, NOMINAL, 187500000),
1524 CLK_INIT(byte0_clk_src.c),
1525 },
1526};
1527
1528static struct clk_freq_tbl ftbl_gcc_mdss_byte1_clk[] = {
1529 {
1530 .div_src_val = BVAL(10, 8, xo_source_val)
1531 | BVAL(4, 0, 0),
1532 .src_clk = &xo_clk_src.c,
1533 .freq_hz = 0,
1534 },
1535 {
1536 .div_src_val = BVAL(10, 8, dsi1_1phypll_source_val)
1537 | BVAL(4, 0, 0),
1538 .src_clk = &ext_byte1_clk_src.c,
1539 .freq_hz = 0,
1540 },
1541 {
1542 .div_src_val = BVAL(10, 8, dsi0_1phypll_source_val)
1543 | BVAL(4, 0, 0),
1544 .src_clk = &ext_byte0_clk_src.c,
1545 .freq_hz = 0,
1546 },
1547 F_END
1548};
1549
1550static struct rcg_clk byte1_clk_src = {
1551 .cmd_rcgr_reg = BYTE1_CMD_RCGR,
1552 .set_rate = set_rate_hid,
1553 .current_freq = ftbl_gcc_mdss_byte1_clk,
1554 .freq_tbl = ftbl_gcc_mdss_byte1_clk,
1555 .base = &virt_bases[GCC_BASE],
1556 .c = {
1557 .dbg_name = "byte1_clk_src",
1558 .ops = &clk_ops_byte_multiparent,
1559 .flags = CLKFLAG_NO_RATE_CACHE,
1560 VDD_DIG_FMAX_MAP2(LOWER, 125000000, NOMINAL, 187500000),
1561 CLK_INIT(byte1_clk_src.c),
1562 },
1563};
1564
1565static struct clk_freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
1566 F( 19200000, xo, 1, 0, 0),
1567 F_END
1568};
1569
1570static struct rcg_clk esc0_clk_src = {
1571 .cmd_rcgr_reg = ESC0_CMD_RCGR,
1572 .set_rate = set_rate_hid,
1573 .freq_tbl = ftbl_gcc_mdss_esc0_clk,
1574 .current_freq = &rcg_dummy_freq,
1575 .base = &virt_bases[GCC_BASE],
1576 .c = {
1577 .dbg_name = "esc0_clk_src",
1578 .ops = &clk_ops_rcg,
1579 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1580 CLK_INIT(esc0_clk_src.c),
1581 },
1582};
1583
1584static struct clk_freq_tbl ftbl_esc1_clk_src[] = {
1585 F( 19200000, xo, 1, 0, 0),
1586 F_END
1587};
1588
1589static struct rcg_clk esc1_clk_src = {
1590 .cmd_rcgr_reg = ESC1_CMD_RCGR,
1591 .set_rate = set_rate_hid,
1592 .freq_tbl = ftbl_esc1_clk_src,
1593 .current_freq = &rcg_dummy_freq,
1594 .base = &virt_bases[GCC_BASE],
1595 .c = {
1596 .dbg_name = "esc1_clk_src",
1597 .ops = &clk_ops_rcg,
1598 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1599 CLK_INIT(esc1_clk_src.c),
1600 },
1601};
1602
1603static struct clk_freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1604 F( 50000000, gpll0, 16, 0, 0),
1605 F( 80000000, gpll0, 10, 0, 0),
1606 F( 100000000, gpll0, 8, 0, 0),
1607 F( 145450000, gpll0, 5.5, 0, 0),
1608 F( 160000000, gpll0, 5, 0, 0),
1609 F( 177780000, gpll0, 4.5, 0, 0),
1610 F( 200000000, gpll0, 4, 0, 0),
1611 F( 266670000, gpll0, 3, 0, 0),
1612 F( 320000000, gpll0, 2.5, 0, 0),
1613 F_END
1614};
1615
1616static struct rcg_clk mdp_clk_src = {
1617 .cmd_rcgr_reg = MDP_CMD_RCGR,
1618 .set_rate = set_rate_hid,
1619 .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1620 .current_freq = &rcg_dummy_freq,
1621 .base = &virt_bases[GCC_BASE],
1622 .c = {
1623 .dbg_name = "mdp_clk_src",
1624 .ops = &clk_ops_rcg,
1625 VDD_DIG_FMAX_MAP3(LOWER, 160000000, NOMINAL, 266670000,
1626 HIGH, 320000000),
1627 CLK_INIT(mdp_clk_src.c),
1628 },
1629};
1630
1631static struct clk_freq_tbl ftbl_gcc_mdss_pclk0_clk[] = {
1632 {
1633 .div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
1634 | BVAL(4, 0, 0),
1635 .src_clk = &ext_pclk0_clk_src.c,
1636 .freq_hz = 0,
1637 },
1638 F_END
1639};
1640
1641static struct clk_freq_tbl ftbl_gcc_mdss_pclk0_clk_8937[] = {
1642 {
1643 .div_src_val = BVAL(10, 8, xo_source_val)
1644 | BVAL(4, 0, 0),
1645 .src_clk = &xo_clk_src.c,
1646 .freq_hz = 0,
1647 },
1648 {
1649 .div_src_val = BVAL(10, 8, dsi0_0phypll_source_val)
1650 | BVAL(4, 0, 0),
1651 .src_clk = &ext_pclk0_clk_src.c,
1652 .freq_hz = 0,
1653 },
1654 {
1655 .div_src_val = BVAL(10, 8, dsi1_0phypll_source_val)
1656 | BVAL(4, 0, 0),
1657 .src_clk = &ext_pclk1_clk_src.c,
1658 .freq_hz = 0,
1659 },
1660 F_END
1661};
1662
1663static struct rcg_clk pclk0_clk_src = {
1664 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
1665 .set_rate = set_rate_mnd,
1666 .current_freq = ftbl_gcc_mdss_pclk0_clk,
1667 .freq_tbl = ftbl_gcc_mdss_pclk0_clk,
1668 .base = &virt_bases[GCC_BASE],
1669 .c = {
1670 .dbg_name = "pclk0_clk_src",
1671 .ops = &clk_ops_pixel_multiparent,
1672 VDD_DIG_FMAX_MAP2(LOWER, 160000000, NOMINAL, 250000000),
1673 .flags = CLKFLAG_NO_RATE_CACHE,
1674 CLK_INIT(pclk0_clk_src.c),
1675 },
1676};
1677
1678static struct clk_freq_tbl ftbl_gcc_mdss_pclk1_clk[] = {
1679 {
1680 .div_src_val = BVAL(10, 8, xo_source_val)
1681 | BVAL(4, 0, 0),
1682 .src_clk = &xo_clk_src.c,
1683 .freq_hz = 0,
1684 },
1685 {
1686 .div_src_val = BVAL(10, 8, dsi1_1phypll_source_val)
1687 | BVAL(4, 0, 0),
1688 .src_clk = &ext_pclk1_clk_src.c,
1689 .freq_hz = 0,
1690 },
1691 {
1692 .div_src_val = BVAL(10, 8, dsi0_1phypll_source_val)
1693 | BVAL(4, 0, 0),
1694 .src_clk = &ext_pclk0_clk_src.c,
1695 .freq_hz = 0,
1696 },
1697 F_END
1698};
1699
1700static struct rcg_clk pclk1_clk_src = {
1701 .cmd_rcgr_reg = PCLK1_CMD_RCGR,
1702 .set_rate = set_rate_mnd,
1703 .current_freq = ftbl_gcc_mdss_pclk1_clk,
1704 .freq_tbl = ftbl_gcc_mdss_pclk1_clk,
1705 .base = &virt_bases[GCC_BASE],
1706 .c = {
1707 .dbg_name = "pclk1_clk_src",
1708 .ops = &clk_ops_pixel_multiparent,
1709 .flags = CLKFLAG_NO_RATE_CACHE,
1710 VDD_DIG_FMAX_MAP2(LOWER, 166670000, NOMINAL, 250000000),
1711 CLK_INIT(pclk1_clk_src.c),
1712 },
1713};
1714
1715static struct clk_freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1716 F( 19200000, xo, 1, 0, 0),
1717 F_END
1718};
1719
1720static struct rcg_clk vsync_clk_src = {
1721 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
1722 .set_rate = set_rate_hid,
1723 .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1724 .current_freq = &rcg_dummy_freq,
1725 .base = &virt_bases[GCC_BASE],
1726 .c = {
1727 .dbg_name = "vsync_clk_src",
1728 .ops = &clk_ops_rcg,
1729 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1730 CLK_INIT(vsync_clk_src.c),
1731 },
1732};
1733
1734static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
1735 F( 64000000, gpll0, 12.5, 0, 0),
1736 F_END
1737};
1738
1739static struct rcg_clk pdm2_clk_src = {
1740 .cmd_rcgr_reg = PDM2_CMD_RCGR,
1741 .set_rate = set_rate_hid,
1742 .freq_tbl = ftbl_gcc_pdm2_clk,
1743 .current_freq = &rcg_dummy_freq,
1744 .base = &virt_bases[GCC_BASE],
1745 .c = {
1746 .dbg_name = "pdm2_clk_src",
1747 .ops = &clk_ops_rcg,
1748 VDD_DIG_FMAX_MAP1(LOWER, 64000000),
1749 CLK_INIT(pdm2_clk_src.c),
1750 },
1751};
1752
1753static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1754 F( 144000, xo, 16, 3, 25),
1755 F( 400000, xo, 12, 1, 4),
1756 F( 20000000, gpll0, 10, 1, 4),
1757 F( 25000000, gpll0, 16, 1, 2),
1758 F( 50000000, gpll0, 16, 0, 0),
1759 F( 100000000, gpll0, 8, 0, 0),
1760 F( 177770000, gpll0, 4.5, 0, 0),
1761 F( 192000000, gpll4, 6, 0, 0),
1762 F( 200000000, gpll0, 4, 0, 0),
1763 F( 384000000, gpll4, 3, 0, 0),
1764 F_END
1765};
1766
1767static struct rcg_clk sdcc1_apps_clk_src = {
1768 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
1769 .set_rate = set_rate_mnd,
1770 .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1771 .current_freq = &rcg_dummy_freq,
1772 .base = &virt_bases[GCC_BASE],
1773 .c = {
1774 .dbg_name = "sdcc1_apps_clk_src",
1775 .ops = &clk_ops_rcg_mnd,
1776 VDD_DIG_FMAX_MAP2(LOWER, 50000000, NOMINAL, 384000000),
1777 CLK_INIT(sdcc1_apps_clk_src.c),
1778 },
1779};
1780
1781static struct clk_freq_tbl ftbl_gcc_sdcc1_ice_core_clk[] = {
1782 F( 100000000, gpll0_out_main, 8, 0, 0),
1783 F( 200000000, gpll0_out_main, 4, 0, 0),
1784 F_END
1785};
1786
1787static struct rcg_clk sdcc1_ice_core_clk_src = {
1788 .cmd_rcgr_reg = SDCC1_ICE_CORE_CMD_RCGR,
1789 .set_rate = set_rate_mnd,
1790 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk,
1791 .current_freq = &rcg_dummy_freq,
1792 .base = &virt_bases[GCC_BASE],
1793 .c = {
1794 .dbg_name = "sdcc1_ice_core_clk_src",
1795 .ops = &clk_ops_rcg_mnd,
1796 VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),
1797 CLK_INIT(sdcc1_ice_core_clk_src.c),
1798 },
1799};
1800
1801static struct clk_freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1802 F( 144000, xo, 16, 3, 25),
1803 F( 400000, xo, 12, 1, 4),
1804 F( 20000000, gpll0, 10, 1, 4),
1805 F( 25000000, gpll0, 16, 1, 2),
1806 F( 50000000, gpll0, 16, 0, 0),
1807 F( 100000000, gpll0, 8, 0, 0),
1808 F( 177770000, gpll0, 4.5, 0, 0),
1809 F( 200000000, gpll0, 4, 0, 0),
1810 F_END
1811};
1812
1813static struct rcg_clk sdcc2_apps_clk_src = {
1814 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
1815 .set_rate = set_rate_mnd,
1816 .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1817 .current_freq = &rcg_dummy_freq,
1818 .base = &virt_bases[GCC_BASE],
1819 .c = {
1820 .dbg_name = "sdcc2_apps_clk_src",
1821 .ops = &clk_ops_rcg_mnd,
1822 VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),
1823 CLK_INIT(sdcc2_apps_clk_src.c),
1824 },
1825};
1826
1827static struct clk_freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
1828 F( 60000000, gpll6_out_main, 9, 1, 2),
1829 F_END
1830};
1831
1832static struct rcg_clk usb_fs_ic_clk_src = {
1833 .cmd_rcgr_reg = USB_FS_IC_CMD_RCGR,
1834 .set_rate = set_rate_mnd,
1835 .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
1836 .current_freq = &rcg_dummy_freq,
1837 .base = &virt_bases[GCC_BASE],
1838 .c = {
1839 .dbg_name = "usb_fs_ic_clk_src",
1840 .ops = &clk_ops_rcg_mnd,
1841 VDD_DIG_FMAX_MAP1(LOWER, 60000000),
1842 CLK_INIT(usb_fs_ic_clk_src.c),
1843 },
1844};
1845
1846static struct clk_freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
1847 F( 64000000, gpll0_out_aux, 12.5, 0, 0),
1848 F_END
1849};
1850
1851static struct rcg_clk usb_fs_system_clk_src = {
1852 .cmd_rcgr_reg = USB_FS_SYSTEM_CMD_RCGR,
1853 .set_rate = set_rate_mnd,
1854 .freq_tbl = ftbl_gcc_usb_fs_system_clk,
1855 .current_freq = &rcg_dummy_freq,
1856 .base = &virt_bases[GCC_BASE],
1857 .c = {
1858 .dbg_name = "usb_fs_system_clk_src",
1859 .ops = &clk_ops_rcg_mnd,
1860 VDD_DIG_FMAX_MAP1(LOWER, 64000000),
1861 CLK_INIT(usb_fs_system_clk_src.c),
1862 },
1863};
1864
1865static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1866 F( 57140000, gpll0, 14, 0, 0),
1867 F( 100000000, gpll0, 8, 0, 0),
1868 F( 133330000, gpll0, 6, 0, 0),
1869 F( 177780000, gpll0, 4.5, 0, 0),
1870 F_END
1871};
1872
1873static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk_8917[] = {
1874 F( 80000000, gpll0, 10, 0, 0),
1875 F( 100000000, gpll0, 8, 0, 0),
1876 F( 133330000, gpll0, 6, 0, 0),
1877 F( 177780000, gpll0, 4.5, 0, 0),
1878 F_END
1879};
1880
1881static struct rcg_clk usb_hs_system_clk_src = {
1882 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
1883 .set_rate = set_rate_hid,
1884 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1885 .current_freq = &rcg_dummy_freq,
1886 .base = &virt_bases[GCC_BASE],
1887 .c = {
1888 .dbg_name = "usb_hs_system_clk_src",
1889 .ops = &clk_ops_rcg,
1890 VDD_DIG_FMAX_MAP3(LOWER, 57140000, NOMINAL, 133330000,
1891 HIGH, 177780000),
1892 CLK_INIT(usb_hs_system_clk_src.c),
1893 },
1894};
1895
1896static struct branch_clk gcc_bimc_gpu_clk = {
1897 .cbcr_reg = BIMC_GPU_CBCR,
1898 .has_sibling = 1,
1899 .base = &virt_bases[GCC_BASE],
1900 .c = {
1901 .dbg_name = "gcc_bimc_gpu_clk",
1902 .ops = &clk_ops_branch,
1903 CLK_INIT(gcc_bimc_gpu_clk.c),
1904 },
1905};
1906
1907static struct branch_clk gcc_dcc_clk = {
1908 .cbcr_reg = DCC_CBCR,
1909 .has_sibling = 1,
1910 .base = &virt_bases[GCC_BASE],
1911 .c = {
1912 .dbg_name = "gcc_dcc_clk",
1913 .ops = &clk_ops_branch,
1914 CLK_INIT(gcc_dcc_clk.c),
1915 },
1916};
1917
1918static struct local_vote_clk gcc_blsp1_ahb_clk = {
1919 .cbcr_reg = BLSP1_AHB_CBCR,
1920 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1921 .en_mask = BIT(10),
1922 .base = &virt_bases[GCC_BASE],
1923 .c = {
1924 .dbg_name = "gcc_blsp1_ahb_clk",
1925 .ops = &clk_ops_vote,
1926 CLK_INIT(gcc_blsp1_ahb_clk.c),
1927 },
1928};
1929
1930static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1931 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1932 .has_sibling = 0,
1933 .base = &virt_bases[GCC_BASE],
1934 .c = {
1935 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1936 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1937 .ops = &clk_ops_branch,
1938 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
1939 },
1940};
1941
1942static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
1943 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
1944 .has_sibling = 0,
1945 .base = &virt_bases[GCC_BASE],
1946 .c = {
1947 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
1948 .parent = &blsp1_qup1_spi_apps_clk_src.c,
1949 .ops = &clk_ops_branch,
1950 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
1951 },
1952};
1953
1954static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
1955 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
1956 .has_sibling = 0,
1957 .base = &virt_bases[GCC_BASE],
1958 .c = {
1959 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
1960 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
1961 .ops = &clk_ops_branch,
1962 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
1963 },
1964};
1965
1966static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
1967 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
1968 .has_sibling = 0,
1969 .base = &virt_bases[GCC_BASE],
1970 .c = {
1971 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
1972 .parent = &blsp1_qup2_spi_apps_clk_src.c,
1973 .ops = &clk_ops_branch,
1974 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
1975 },
1976};
1977
1978static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
1979 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
1980 .has_sibling = 0,
1981 .base = &virt_bases[GCC_BASE],
1982 .c = {
1983 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
1984 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
1985 .ops = &clk_ops_branch,
1986 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
1987 },
1988};
1989
1990static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
1991 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
1992 .has_sibling = 0,
1993 .base = &virt_bases[GCC_BASE],
1994 .c = {
1995 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
1996 .parent = &blsp1_qup3_spi_apps_clk_src.c,
1997 .ops = &clk_ops_branch,
1998 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
1999 },
2000};
2001
2002static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
2003 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
2004 .has_sibling = 0,
2005 .base = &virt_bases[GCC_BASE],
2006 .c = {
2007 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
2008 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
2009 .ops = &clk_ops_branch,
2010 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
2011 },
2012};
2013
2014static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
2015 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
2016 .has_sibling = 0,
2017 .base = &virt_bases[GCC_BASE],
2018 .c = {
2019 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
2020 .parent = &blsp1_qup4_spi_apps_clk_src.c,
2021 .ops = &clk_ops_branch,
2022 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
2023 },
2024};
2025
2026static struct branch_clk gcc_blsp1_uart1_apps_clk = {
2027 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
2028 .has_sibling = 0,
2029 .base = &virt_bases[GCC_BASE],
2030 .c = {
2031 .dbg_name = "gcc_blsp1_uart1_apps_clk",
2032 .parent = &blsp1_uart1_apps_clk_src.c,
2033 .ops = &clk_ops_branch,
2034 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
2035 },
2036};
2037
2038static struct branch_clk gcc_blsp1_uart2_apps_clk = {
2039 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
2040 .has_sibling = 0,
2041 .base = &virt_bases[GCC_BASE],
2042 .c = {
2043 .dbg_name = "gcc_blsp1_uart2_apps_clk",
2044 .parent = &blsp1_uart2_apps_clk_src.c,
2045 .ops = &clk_ops_branch,
2046 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
2047 },
2048};
2049
2050static struct local_vote_clk gcc_blsp2_ahb_clk = {
2051 .cbcr_reg = BLSP2_AHB_CBCR,
2052 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2053 .en_mask = BIT(20),
2054 .base = &virt_bases[GCC_BASE],
2055 .c = {
2056 .dbg_name = "gcc_blsp2_ahb_clk",
2057 .ops = &clk_ops_vote,
2058 CLK_INIT(gcc_blsp2_ahb_clk.c),
2059 },
2060};
2061
2062static struct branch_clk gcc_blsp2_qup1_i2c_apps_clk = {
2063 .cbcr_reg = BLSP2_QUP1_I2C_APPS_CBCR,
2064 .has_sibling = 0,
2065 .base = &virt_bases[GCC_BASE],
2066 .c = {
2067 .dbg_name = "gcc_blsp2_qup1_i2c_apps_clk",
2068 .parent = &blsp2_qup1_i2c_apps_clk_src.c,
2069 .ops = &clk_ops_branch,
2070 CLK_INIT(gcc_blsp2_qup1_i2c_apps_clk.c),
2071 },
2072};
2073
2074static struct branch_clk gcc_blsp2_qup1_spi_apps_clk = {
2075 .cbcr_reg = BLSP2_QUP1_SPI_APPS_CBCR,
2076 .has_sibling = 0,
2077 .base = &virt_bases[GCC_BASE],
2078 .c = {
2079 .dbg_name = "gcc_blsp2_qup1_spi_apps_clk",
2080 .parent = &blsp2_qup1_spi_apps_clk_src.c,
2081 .ops = &clk_ops_branch,
2082 CLK_INIT(gcc_blsp2_qup1_spi_apps_clk.c),
2083 },
2084};
2085
2086static struct branch_clk gcc_blsp2_qup2_i2c_apps_clk = {
2087 .cbcr_reg = BLSP2_QUP2_I2C_APPS_CBCR,
2088 .has_sibling = 0,
2089 .base = &virt_bases[GCC_BASE],
2090 .c = {
2091 .dbg_name = "gcc_blsp2_qup2_i2c_apps_clk",
2092 .parent = &blsp2_qup2_i2c_apps_clk_src.c,
2093 .ops = &clk_ops_branch,
2094 CLK_INIT(gcc_blsp2_qup2_i2c_apps_clk.c),
2095 },
2096};
2097
2098static struct branch_clk gcc_blsp2_qup2_spi_apps_clk = {
2099 .cbcr_reg = BLSP2_QUP2_SPI_APPS_CBCR,
2100 .has_sibling = 0,
2101 .base = &virt_bases[GCC_BASE],
2102 .c = {
2103 .dbg_name = "gcc_blsp2_qup2_spi_apps_clk",
2104 .parent = &blsp2_qup2_spi_apps_clk_src.c,
2105 .ops = &clk_ops_branch,
2106 CLK_INIT(gcc_blsp2_qup2_spi_apps_clk.c),
2107 },
2108};
2109
2110static struct branch_clk gcc_blsp2_qup3_i2c_apps_clk = {
2111 .cbcr_reg = BLSP2_QUP3_I2C_APPS_CBCR,
2112 .has_sibling = 0,
2113 .base = &virt_bases[GCC_BASE],
2114 .c = {
2115 .dbg_name = "gcc_blsp2_qup3_i2c_apps_clk",
2116 .parent = &blsp2_qup3_i2c_apps_clk_src.c,
2117 .ops = &clk_ops_branch,
2118 CLK_INIT(gcc_blsp2_qup3_i2c_apps_clk.c),
2119 },
2120};
2121
2122static struct branch_clk gcc_blsp2_qup3_spi_apps_clk = {
2123 .cbcr_reg = BLSP2_QUP3_SPI_APPS_CBCR,
2124 .has_sibling = 0,
2125 .base = &virt_bases[GCC_BASE],
2126 .c = {
2127 .dbg_name = "gcc_blsp2_qup3_spi_apps_clk",
2128 .parent = &blsp2_qup3_spi_apps_clk_src.c,
2129 .ops = &clk_ops_branch,
2130 CLK_INIT(gcc_blsp2_qup3_spi_apps_clk.c),
2131 },
2132};
2133
2134static struct branch_clk gcc_blsp2_qup4_i2c_apps_clk = {
2135 .cbcr_reg = BLSP2_QUP4_I2C_APPS_CBCR,
2136 .has_sibling = 0,
2137 .base = &virt_bases[GCC_BASE],
2138 .c = {
2139 .dbg_name = "gcc_blsp2_qup4_i2c_apps_clk",
2140 .parent = &blsp2_qup4_i2c_apps_clk_src.c,
2141 .ops = &clk_ops_branch,
2142 CLK_INIT(gcc_blsp2_qup4_i2c_apps_clk.c),
2143 },
2144};
2145
2146static struct branch_clk gcc_blsp2_qup4_spi_apps_clk = {
2147 .cbcr_reg = BLSP2_QUP4_SPI_APPS_CBCR,
2148 .has_sibling = 0,
2149 .base = &virt_bases[GCC_BASE],
2150 .c = {
2151 .dbg_name = "gcc_blsp2_qup4_spi_apps_clk",
2152 .parent = &blsp2_qup4_spi_apps_clk_src.c,
2153 .ops = &clk_ops_branch,
2154 CLK_INIT(gcc_blsp2_qup4_spi_apps_clk.c),
2155 },
2156};
2157
2158static struct branch_clk gcc_blsp2_uart1_apps_clk = {
2159 .cbcr_reg = BLSP2_UART1_APPS_CBCR,
2160 .has_sibling = 0,
2161 .base = &virt_bases[GCC_BASE],
2162 .c = {
2163 .dbg_name = "gcc_blsp2_uart1_apps_clk",
2164 .parent = &blsp2_uart1_apps_clk_src.c,
2165 .ops = &clk_ops_branch,
2166 CLK_INIT(gcc_blsp2_uart1_apps_clk.c),
2167 },
2168};
2169
2170static struct branch_clk gcc_blsp2_uart2_apps_clk = {
2171 .cbcr_reg = BLSP2_UART2_APPS_CBCR,
2172 .has_sibling = 0,
2173 .base = &virt_bases[GCC_BASE],
2174 .c = {
2175 .dbg_name = "gcc_blsp2_uart2_apps_clk",
2176 .parent = &blsp2_uart2_apps_clk_src.c,
2177 .ops = &clk_ops_branch,
2178 CLK_INIT(gcc_blsp2_uart2_apps_clk.c),
2179 },
2180};
2181
2182static struct local_vote_clk gcc_boot_rom_ahb_clk = {
2183 .cbcr_reg = BOOT_ROM_AHB_CBCR,
2184 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2185 .en_mask = BIT(7),
2186 .base = &virt_bases[GCC_BASE],
2187 .c = {
2188 .dbg_name = "gcc_boot_rom_ahb_clk",
2189 .ops = &clk_ops_vote,
2190 CLK_INIT(gcc_boot_rom_ahb_clk.c),
2191 },
2192};
2193
2194static struct branch_clk gcc_camss_cci_ahb_clk = {
2195 .cbcr_reg = CAMSS_CCI_AHB_CBCR,
2196 .has_sibling = 1,
2197 .base = &virt_bases[GCC_BASE],
2198 .c = {
2199 .dbg_name = "gcc_camss_cci_ahb_clk",
2200 .parent = &camss_top_ahb_clk_src.c,
2201 .ops = &clk_ops_branch,
2202 CLK_INIT(gcc_camss_cci_ahb_clk.c),
2203 },
2204};
2205
2206static struct branch_clk gcc_camss_cci_clk = {
2207 .cbcr_reg = CAMSS_CCI_CBCR,
2208 .has_sibling = 0,
2209 .base = &virt_bases[GCC_BASE],
2210 .c = {
2211 .dbg_name = "gcc_camss_cci_clk",
2212 .parent = &cci_clk_src.c,
2213 .ops = &clk_ops_branch,
2214 CLK_INIT(gcc_camss_cci_clk.c),
2215 },
2216};
2217
2218static struct branch_clk gcc_camss_cpp_ahb_clk = {
2219 .cbcr_reg = CAMSS_CPP_AHB_CBCR,
2220 .has_sibling = 1,
2221 .base = &virt_bases[GCC_BASE],
2222 .c = {
2223 .dbg_name = "gcc_camss_cpp_ahb_clk",
2224 .parent = &camss_top_ahb_clk_src.c,
2225 .ops = &clk_ops_branch,
2226 CLK_INIT(gcc_camss_cpp_ahb_clk.c),
2227 },
2228};
2229
2230static struct branch_clk gcc_camss_cpp_axi_clk = {
2231 .cbcr_reg = CAMSS_CPP_AXI_CBCR,
2232 .has_sibling = 1,
2233 .base = &virt_bases[GCC_BASE],
2234 .c = {
2235 .dbg_name = "gcc_camss_cpp_axi_clk",
2236 .ops = &clk_ops_branch,
2237 CLK_INIT(gcc_camss_cpp_axi_clk.c),
2238 },
2239};
2240
2241static struct branch_clk gcc_camss_cpp_clk = {
2242 .cbcr_reg = CAMSS_CPP_CBCR,
2243 .has_sibling = 0,
2244 .base = &virt_bases[GCC_BASE],
2245 .c = {
2246 .dbg_name = "gcc_camss_cpp_clk",
2247 .parent = &cpp_clk_src.c,
2248 .ops = &clk_ops_branch,
2249 CLK_INIT(gcc_camss_cpp_clk.c),
2250 },
2251};
2252
2253static struct branch_clk gcc_camss_csi0_ahb_clk = {
2254 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2255 .has_sibling = 1,
2256 .base = &virt_bases[GCC_BASE],
2257 .c = {
2258 .dbg_name = "gcc_camss_csi0_ahb_clk",
2259 .parent = &camss_top_ahb_clk_src.c,
2260 .ops = &clk_ops_branch,
2261 CLK_INIT(gcc_camss_csi0_ahb_clk.c),
2262 },
2263};
2264
2265static struct branch_clk gcc_camss_csi0_clk = {
2266 .cbcr_reg = CAMSS_CSI0_CBCR,
2267 .has_sibling = 1,
2268 .base = &virt_bases[GCC_BASE],
2269 .c = {
2270 .dbg_name = "gcc_camss_csi0_clk",
2271 .parent = &csi0_clk_src.c,
2272 .ops = &clk_ops_branch,
2273 CLK_INIT(gcc_camss_csi0_clk.c),
2274 },
2275};
2276
2277static struct branch_clk gcc_camss_csi0phy_clk = {
2278 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2279 .has_sibling = 1,
2280 .base = &virt_bases[GCC_BASE],
2281 .c = {
2282 .dbg_name = "gcc_camss_csi0phy_clk",
2283 .parent = &csi0_clk_src.c,
2284 .ops = &clk_ops_branch,
2285 CLK_INIT(gcc_camss_csi0phy_clk.c),
2286 },
2287};
2288
2289static struct branch_clk gcc_camss_csi0pix_clk = {
2290 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2291 .has_sibling = 1,
2292 .base = &virt_bases[GCC_BASE],
2293 .c = {
2294 .dbg_name = "gcc_camss_csi0pix_clk",
2295 .parent = &csi0_clk_src.c,
2296 .ops = &clk_ops_branch,
2297 CLK_INIT(gcc_camss_csi0pix_clk.c),
2298 },
2299};
2300
2301static struct branch_clk gcc_camss_csi0rdi_clk = {
2302 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2303 .has_sibling = 1,
2304 .base = &virt_bases[GCC_BASE],
2305 .c = {
2306 .dbg_name = "gcc_camss_csi0rdi_clk",
2307 .parent = &csi0_clk_src.c,
2308 .ops = &clk_ops_branch,
2309 CLK_INIT(gcc_camss_csi0rdi_clk.c),
2310 },
2311};
2312
2313static struct branch_clk gcc_camss_csi1_ahb_clk = {
2314 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2315 .has_sibling = 1,
2316 .base = &virt_bases[GCC_BASE],
2317 .c = {
2318 .dbg_name = "gcc_camss_csi1_ahb_clk",
2319 .parent = &camss_top_ahb_clk_src.c,
2320 .ops = &clk_ops_branch,
2321 CLK_INIT(gcc_camss_csi1_ahb_clk.c),
2322 },
2323};
2324
2325static struct branch_clk gcc_camss_csi1_clk = {
2326 .cbcr_reg = CAMSS_CSI1_CBCR,
2327 .has_sibling = 1,
2328 .base = &virt_bases[GCC_BASE],
2329 .c = {
2330 .dbg_name = "gcc_camss_csi1_clk",
2331 .parent = &csi1_clk_src.c,
2332 .ops = &clk_ops_branch,
2333 CLK_INIT(gcc_camss_csi1_clk.c),
2334 },
2335};
2336
2337static struct branch_clk gcc_camss_csi1phy_clk = {
2338 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2339 .has_sibling = 1,
2340 .base = &virt_bases[GCC_BASE],
2341 .c = {
2342 .dbg_name = "gcc_camss_csi1phy_clk",
2343 .parent = &csi1_clk_src.c,
2344 .ops = &clk_ops_branch,
2345 CLK_INIT(gcc_camss_csi1phy_clk.c),
2346 },
2347};
2348
2349static struct branch_clk gcc_camss_csi1pix_clk = {
2350 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2351 .has_sibling = 1,
2352 .base = &virt_bases[GCC_BASE],
2353 .c = {
2354 .dbg_name = "gcc_camss_csi1pix_clk",
2355 .parent = &csi1_clk_src.c,
2356 .ops = &clk_ops_branch,
2357 CLK_INIT(gcc_camss_csi1pix_clk.c),
2358 },
2359};
2360
2361static struct branch_clk gcc_camss_csi1rdi_clk = {
2362 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2363 .has_sibling = 1,
2364 .base = &virt_bases[GCC_BASE],
2365 .c = {
2366 .dbg_name = "gcc_camss_csi1rdi_clk",
2367 .parent = &csi1_clk_src.c,
2368 .ops = &clk_ops_branch,
2369 CLK_INIT(gcc_camss_csi1rdi_clk.c),
2370 },
2371};
2372
2373static struct branch_clk gcc_camss_csi2_ahb_clk = {
2374 .cbcr_reg = CAMSS_CSI2_AHB_CBCR,
2375 .has_sibling = 1,
2376 .base = &virt_bases[GCC_BASE],
2377 .c = {
2378 .dbg_name = "gcc_camss_csi2_ahb_clk",
2379 .parent = &camss_top_ahb_clk_src.c,
2380 .ops = &clk_ops_branch,
2381 CLK_INIT(gcc_camss_csi2_ahb_clk.c),
2382 },
2383};
2384
2385static struct branch_clk gcc_camss_csi2_clk = {
2386 .cbcr_reg = CAMSS_CSI2_CBCR,
2387 .has_sibling = 1,
2388 .base = &virt_bases[GCC_BASE],
2389 .c = {
2390 .dbg_name = "gcc_camss_csi2_clk",
2391 .parent = &csi2_clk_src.c,
2392 .ops = &clk_ops_branch,
2393 CLK_INIT(gcc_camss_csi2_clk.c),
2394 },
2395};
2396
2397static struct branch_clk gcc_camss_csi2phy_clk = {
2398 .cbcr_reg = CAMSS_CSI2PHY_CBCR,
2399 .has_sibling = 1,
2400 .base = &virt_bases[GCC_BASE],
2401 .c = {
2402 .dbg_name = "gcc_camss_csi2phy_clk",
2403 .parent = &csi2_clk_src.c,
2404 .ops = &clk_ops_branch,
2405 CLK_INIT(gcc_camss_csi2phy_clk.c),
2406 },
2407};
2408
2409static struct branch_clk gcc_camss_csi2pix_clk = {
2410 .cbcr_reg = CAMSS_CSI2PIX_CBCR,
2411 .has_sibling = 1,
2412 .base = &virt_bases[GCC_BASE],
2413 .c = {
2414 .dbg_name = "gcc_camss_csi2pix_clk",
2415 .parent = &csi2_clk_src.c,
2416 .ops = &clk_ops_branch,
2417 CLK_INIT(gcc_camss_csi2pix_clk.c),
2418 },
2419};
2420
2421static struct branch_clk gcc_camss_csi2rdi_clk = {
2422 .cbcr_reg = CAMSS_CSI2RDI_CBCR,
2423 .has_sibling = 1,
2424 .base = &virt_bases[GCC_BASE],
2425 .c = {
2426 .dbg_name = "gcc_camss_csi2rdi_clk",
2427 .parent = &csi2_clk_src.c,
2428 .ops = &clk_ops_branch,
2429 CLK_INIT(gcc_camss_csi2rdi_clk.c),
2430 },
2431};
2432
2433static struct branch_clk gcc_camss_csi_vfe0_clk = {
2434 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
2435 .has_sibling = 1,
2436 .base = &virt_bases[GCC_BASE],
2437 .c = {
2438 .dbg_name = "gcc_camss_csi_vfe0_clk",
2439 .parent = &vfe0_clk_src.c,
2440 .ops = &clk_ops_branch,
2441 CLK_INIT(gcc_camss_csi_vfe0_clk.c),
2442 },
2443};
2444
2445static struct branch_clk gcc_camss_csi_vfe1_clk = {
2446 .cbcr_reg = CAMSS_CSI_VFE1_CBCR,
2447 .has_sibling = 1,
2448 .base = &virt_bases[GCC_BASE],
2449 .c = {
2450 .dbg_name = "gcc_camss_csi_vfe1_clk",
2451 .parent = &vfe1_clk_src.c,
2452 .ops = &clk_ops_branch,
2453 CLK_INIT(gcc_camss_csi_vfe1_clk.c),
2454 },
2455};
2456
2457static struct branch_clk gcc_camss_gp0_clk = {
2458 .cbcr_reg = CAMSS_GP0_CBCR,
2459 .has_sibling = 0,
2460 .base = &virt_bases[GCC_BASE],
2461 .c = {
2462 .dbg_name = "gcc_camss_gp0_clk",
2463 .parent = &camss_gp0_clk_src.c,
2464 .ops = &clk_ops_branch,
2465 CLK_INIT(gcc_camss_gp0_clk.c),
2466 },
2467};
2468
2469static struct branch_clk gcc_camss_gp1_clk = {
2470 .cbcr_reg = CAMSS_GP1_CBCR,
2471 .has_sibling = 0,
2472 .base = &virt_bases[GCC_BASE],
2473 .c = {
2474 .dbg_name = "gcc_camss_gp1_clk",
2475 .parent = &camss_gp1_clk_src.c,
2476 .ops = &clk_ops_branch,
2477 CLK_INIT(gcc_camss_gp1_clk.c),
2478 },
2479};
2480
2481static struct branch_clk gcc_camss_ispif_ahb_clk = {
2482 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2483 .has_sibling = 0,
2484 .base = &virt_bases[GCC_BASE],
2485 .c = {
2486 .dbg_name = "gcc_camss_ispif_ahb_clk",
2487 .parent = &camss_top_ahb_clk_src.c,
2488 .ops = &clk_ops_branch,
2489 CLK_INIT(gcc_camss_ispif_ahb_clk.c),
2490 },
2491};
2492
2493static struct branch_clk gcc_camss_jpeg0_clk = {
2494 .cbcr_reg = CAMSS_JPEG0_CBCR,
2495 .has_sibling = 0,
2496 .base = &virt_bases[GCC_BASE],
2497 .c = {
2498 .dbg_name = "gcc_camss_jpeg0_clk",
2499 .parent = &jpeg0_clk_src.c,
2500 .ops = &clk_ops_branch,
2501 CLK_INIT(gcc_camss_jpeg0_clk.c),
2502 },
2503};
2504
2505static struct branch_clk gcc_camss_jpeg_ahb_clk = {
2506 .cbcr_reg = CAMSS_JPEG_AHB_CBCR,
2507 .has_sibling = 1,
2508 .base = &virt_bases[GCC_BASE],
2509 .c = {
2510 .dbg_name = "gcc_camss_jpeg_ahb_clk",
2511 .parent = &camss_top_ahb_clk_src.c,
2512 .ops = &clk_ops_branch,
2513 CLK_INIT(gcc_camss_jpeg_ahb_clk.c),
2514 },
2515};
2516
2517static struct branch_clk gcc_camss_jpeg_axi_clk = {
2518 .cbcr_reg = CAMSS_JPEG_AXI_CBCR,
2519 .has_sibling = 1,
2520 .base = &virt_bases[GCC_BASE],
2521 .c = {
2522 .dbg_name = "gcc_camss_jpeg_axi_clk",
2523 .ops = &clk_ops_branch,
2524 CLK_INIT(gcc_camss_jpeg_axi_clk.c),
2525 },
2526};
2527
2528static struct branch_clk gcc_camss_mclk0_clk = {
2529 .cbcr_reg = CAMSS_MCLK0_CBCR,
2530 .has_sibling = 0,
2531 .base = &virt_bases[GCC_BASE],
2532 .c = {
2533 .dbg_name = "gcc_camss_mclk0_clk",
2534 .parent = &mclk0_clk_src.c,
2535 .ops = &clk_ops_branch,
2536 CLK_INIT(gcc_camss_mclk0_clk.c),
2537 },
2538};
2539
2540static struct branch_clk gcc_camss_mclk1_clk = {
2541 .cbcr_reg = CAMSS_MCLK1_CBCR,
2542 .has_sibling = 0,
2543 .base = &virt_bases[GCC_BASE],
2544 .c = {
2545 .dbg_name = "gcc_camss_mclk1_clk",
2546 .parent = &mclk1_clk_src.c,
2547 .ops = &clk_ops_branch,
2548 CLK_INIT(gcc_camss_mclk1_clk.c),
2549 },
2550};
2551
2552static struct branch_clk gcc_camss_mclk2_clk = {
2553 .cbcr_reg = CAMSS_MCLK2_CBCR,
2554 .has_sibling = 0,
2555 .base = &virt_bases[GCC_BASE],
2556 .c = {
2557 .dbg_name = "gcc_camss_mclk2_clk",
2558 .parent = &mclk2_clk_src.c,
2559 .ops = &clk_ops_branch,
2560 CLK_INIT(gcc_camss_mclk2_clk.c),
2561 },
2562};
2563
2564static struct branch_clk gcc_camss_micro_ahb_clk = {
2565 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2566 .bcr_reg = CAMSS_MICRO_BCR,
2567 .has_sibling = 1,
2568 .base = &virt_bases[GCC_BASE],
2569 .c = {
2570 .dbg_name = "gcc_camss_micro_ahb_clk",
2571 .parent = &camss_top_ahb_clk_src.c,
2572 .ops = &clk_ops_branch,
2573 CLK_INIT(gcc_camss_micro_ahb_clk.c),
2574 },
2575};
2576
2577static struct branch_clk gcc_camss_csi0phytimer_clk = {
2578 .cbcr_reg = CAMSS_CSI0PHYTIMER_CBCR,
2579 .has_sibling = 0,
2580 .base = &virt_bases[GCC_BASE],
2581 .c = {
2582 .dbg_name = "gcc_camss_csi0phytimer_clk",
2583 .parent = &csi0phytimer_clk_src.c,
2584 .ops = &clk_ops_branch,
2585 CLK_INIT(gcc_camss_csi0phytimer_clk.c),
2586 },
2587};
2588
2589static struct branch_clk gcc_camss_csi1phytimer_clk = {
2590 .cbcr_reg = CAMSS_CSI1PHYTIMER_CBCR,
2591 .has_sibling = 0,
2592 .base = &virt_bases[GCC_BASE],
2593 .c = {
2594 .dbg_name = "gcc_camss_csi1phytimer_clk",
2595 .parent = &csi1phytimer_clk_src.c,
2596 .ops = &clk_ops_branch,
2597 CLK_INIT(gcc_camss_csi1phytimer_clk.c),
2598 },
2599};
2600
2601static struct branch_clk gcc_camss_ahb_clk = {
2602 .cbcr_reg = CAMSS_AHB_CBCR,
2603 .has_sibling = 1,
2604 .base = &virt_bases[GCC_BASE],
2605 .c = {
2606 .dbg_name = "gcc_camss_ahb_clk",
2607 .ops = &clk_ops_branch,
2608 CLK_INIT(gcc_camss_ahb_clk.c),
2609 },
2610};
2611
2612static struct branch_clk gcc_camss_top_ahb_clk = {
2613 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2614 .has_sibling = 1,
2615 .base = &virt_bases[GCC_BASE],
2616 .c = {
2617 .dbg_name = "gcc_camss_top_ahb_clk",
2618 .parent = &camss_top_ahb_clk_src.c,
2619 .ops = &clk_ops_branch,
2620 CLK_INIT(gcc_camss_top_ahb_clk.c),
2621 },
2622};
2623
2624static struct branch_clk gcc_camss_vfe0_clk = {
2625 .cbcr_reg = CAMSS_VFE0_CBCR,
2626 .has_sibling = 1,
2627 .base = &virt_bases[GCC_BASE],
2628 .c = {
2629 .dbg_name = "gcc_camss_vfe0_clk",
2630 .parent = &vfe0_clk_src.c,
2631 .ops = &clk_ops_branch,
2632 CLK_INIT(gcc_camss_vfe0_clk.c),
2633 },
2634};
2635
2636static struct branch_clk gcc_camss_vfe_ahb_clk = {
2637 .cbcr_reg = CAMSS_VFE_AHB_CBCR,
2638 .has_sibling = 1,
2639 .base = &virt_bases[GCC_BASE],
2640 .c = {
2641 .dbg_name = "gcc_camss_vfe_ahb_clk",
2642 .ops = &clk_ops_branch,
2643 CLK_INIT(gcc_camss_vfe_ahb_clk.c),
2644 },
2645};
2646
2647static struct branch_clk gcc_camss_vfe_axi_clk = {
2648 .cbcr_reg = CAMSS_VFE_AXI_CBCR,
2649 .has_sibling = 1,
2650 .base = &virt_bases[GCC_BASE],
2651 .c = {
2652 .dbg_name = "gcc_camss_vfe_axi_clk",
2653 .ops = &clk_ops_branch,
2654 CLK_INIT(gcc_camss_vfe_axi_clk.c),
2655 },
2656};
2657
2658static struct branch_clk gcc_camss_vfe1_ahb_clk = {
2659 .cbcr_reg = CAMSS_VFE1_AHB_CBCR,
2660 .has_sibling = 1,
2661 .base = &virt_bases[GCC_BASE],
2662 .c = {
2663 .dbg_name = "gcc_camss_vfe1_ahb_clk",
2664 .parent = &camss_top_ahb_clk_src.c,
2665 .ops = &clk_ops_branch,
2666 CLK_INIT(gcc_camss_vfe1_ahb_clk.c),
2667 },
2668};
2669
2670static struct branch_clk gcc_camss_vfe1_axi_clk = {
2671 .cbcr_reg = CAMSS_VFE1_AXI_CBCR,
2672 .has_sibling = 1,
2673 .base = &virt_bases[GCC_BASE],
2674 .c = {
2675 .dbg_name = "gcc_camss_vfe1_axi_clk",
2676 .ops = &clk_ops_branch,
2677 CLK_INIT(gcc_camss_vfe1_axi_clk.c),
2678 },
2679};
2680
2681static struct branch_clk gcc_camss_vfe1_clk = {
2682 .cbcr_reg = CAMSS_VFE1_CBCR,
2683 .has_sibling = 1,
2684 .base = &virt_bases[GCC_BASE],
2685 .c = {
2686 .dbg_name = "gcc_camss_vfe1_clk",
2687 .parent = &vfe1_clk_src.c,
2688 .ops = &clk_ops_branch,
2689 CLK_INIT(gcc_camss_vfe1_clk.c),
2690 },
2691};
2692
2693static struct local_vote_clk gcc_crypto_ahb_clk = {
2694 .cbcr_reg = CRYPTO_AHB_CBCR,
2695 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2696 .en_mask = BIT(0),
2697 .base = &virt_bases[GCC_BASE],
2698 .c = {
2699 .dbg_name = "gcc_crypto_ahb_clk",
2700 .parent = &crypto_clk_src.c,
2701 .ops = &clk_ops_vote,
2702 CLK_INIT(gcc_crypto_ahb_clk.c),
2703 },
2704};
2705
2706static struct local_vote_clk gcc_crypto_axi_clk = {
2707 .cbcr_reg = CRYPTO_AXI_CBCR,
2708 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2709 .en_mask = BIT(1),
2710 .base = &virt_bases[GCC_BASE],
2711 .c = {
2712 .dbg_name = "gcc_crypto_axi_clk",
2713 .ops = &clk_ops_vote,
2714 CLK_INIT(gcc_crypto_axi_clk.c),
2715 },
2716};
2717
2718static struct local_vote_clk gcc_crypto_clk = {
2719 .cbcr_reg = CRYPTO_CBCR,
2720 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2721 .en_mask = BIT(2),
2722 .base = &virt_bases[GCC_BASE],
2723 .c = {
2724 .dbg_name = "gcc_crypto_clk",
2725 .parent = &crypto_clk_src.c,
2726 .ops = &clk_ops_vote,
2727 CLK_INIT(gcc_crypto_clk.c),
2728 },
2729};
2730
2731static struct gate_clk gcc_oxili_gmem_clk = {
2732 .en_reg = OXILI_GMEM_CBCR,
2733 .en_mask = BIT(0),
2734 .delay_us = 50,
2735 .base = &virt_bases[GCC_BASE],
2736 .c = {
2737 .dbg_name = "gcc_oxili_gmem_clk",
2738 .parent = &gfx3d_clk_src.c,
2739 .ops = &clk_ops_gate,
2740 CLK_INIT(gcc_oxili_gmem_clk.c),
2741 },
2742};
2743
2744static struct branch_clk gcc_gp1_clk = {
2745 .cbcr_reg = GP1_CBCR,
2746 .has_sibling = 0,
2747 .base = &virt_bases[GCC_BASE],
2748 .c = {
2749 .dbg_name = "gcc_gp1_clk",
2750 .parent = &gp1_clk_src.c,
2751 .ops = &clk_ops_branch,
2752 CLK_INIT(gcc_gp1_clk.c),
2753 },
2754};
2755
2756static struct branch_clk gcc_gp2_clk = {
2757 .cbcr_reg = GP2_CBCR,
2758 .has_sibling = 0,
2759 .base = &virt_bases[GCC_BASE],
2760 .c = {
2761 .dbg_name = "gcc_gp2_clk",
2762 .parent = &gp2_clk_src.c,
2763 .ops = &clk_ops_branch,
2764 CLK_INIT(gcc_gp2_clk.c),
2765 },
2766};
2767
2768static struct branch_clk gcc_gp3_clk = {
2769 .cbcr_reg = GP3_CBCR,
2770 .has_sibling = 0,
2771 .base = &virt_bases[GCC_BASE],
2772 .c = {
2773 .dbg_name = "gcc_gp3_clk",
2774 .parent = &gp3_clk_src.c,
2775 .ops = &clk_ops_branch,
2776 CLK_INIT(gcc_gp3_clk.c),
2777 },
2778};
2779
2780static struct branch_clk gcc_mdss_ahb_clk = {
2781 .cbcr_reg = MDSS_AHB_CBCR,
2782 .has_sibling = 1,
2783 .base = &virt_bases[GCC_BASE],
2784 .c = {
2785 .dbg_name = "gcc_mdss_ahb_clk",
2786 .ops = &clk_ops_branch,
2787 CLK_INIT(gcc_mdss_ahb_clk.c),
2788 },
2789};
2790
2791static struct branch_clk gcc_mdss_axi_clk = {
2792 .cbcr_reg = MDSS_AXI_CBCR,
2793 .has_sibling = 1,
2794 .base = &virt_bases[GCC_BASE],
2795 .c = {
2796 .dbg_name = "gcc_mdss_axi_clk",
2797 .ops = &clk_ops_branch,
2798 CLK_INIT(gcc_mdss_axi_clk.c),
2799 },
2800};
2801
2802static struct branch_clk gcc_mdss_byte0_clk = {
2803 .cbcr_reg = MDSS_BYTE0_CBCR,
2804 .has_sibling = 0,
2805 .base = &virt_bases[GCC_BASE],
2806 .c = {
2807 .dbg_name = "gcc_mdss_byte0_clk",
2808 .parent = &byte0_clk_src.c,
2809 .ops = &clk_ops_branch,
2810 .flags = CLKFLAG_NO_RATE_CACHE,
2811 CLK_INIT(gcc_mdss_byte0_clk.c),
2812 },
2813};
2814
2815static struct branch_clk gcc_mdss_byte1_clk = {
2816 .cbcr_reg = MDSS_BYTE1_CBCR,
2817 .has_sibling = 0,
2818 .base = &virt_bases[GCC_BASE],
2819 .c = {
2820 .dbg_name = "gcc_mdss_byte1_clk",
2821 .parent = &byte1_clk_src.c,
2822 .ops = &clk_ops_branch,
2823 .flags = CLKFLAG_NO_RATE_CACHE,
2824 CLK_INIT(gcc_mdss_byte1_clk.c),
2825 },
2826};
2827
2828static struct branch_clk gcc_mdss_esc0_clk = {
2829 .cbcr_reg = MDSS_ESC0_CBCR,
2830 .has_sibling = 0,
2831 .base = &virt_bases[GCC_BASE],
2832 .c = {
2833 .dbg_name = "gcc_mdss_esc0_clk",
2834 .parent = &esc0_clk_src.c,
2835 .ops = &clk_ops_branch,
2836 CLK_INIT(gcc_mdss_esc0_clk.c),
2837 },
2838};
2839
2840static struct branch_clk gcc_mdss_esc1_clk = {
2841 .cbcr_reg = MDSS_ESC1_CBCR,
2842 .has_sibling = 0,
2843 .base = &virt_bases[GCC_BASE],
2844 .c = {
2845 .dbg_name = "gcc_mdss_esc1_clk",
2846 .parent = &esc1_clk_src.c,
2847 .ops = &clk_ops_branch,
2848 CLK_INIT(gcc_mdss_esc1_clk.c),
2849 },
2850};
2851
2852static struct branch_clk gcc_mdss_mdp_clk = {
2853 .cbcr_reg = MDSS_MDP_CBCR,
2854 .has_sibling = 0,
2855 .base = &virt_bases[GCC_BASE],
2856 .c = {
2857 .dbg_name = "gcc_mdss_mdp_clk",
2858 .parent = &mdp_clk_src.c,
2859 .ops = &clk_ops_branch,
2860 CLK_INIT(gcc_mdss_mdp_clk.c),
2861 },
2862};
2863
2864static DEFINE_CLK_VOTER(mdss_mdp_vote_clk, &gcc_mdss_mdp_clk.c, 0);
2865static DEFINE_CLK_VOTER(mdss_rotator_vote_clk, &gcc_mdss_mdp_clk.c, 0);
2866
2867static struct branch_clk gcc_mdss_pclk0_clk = {
2868 .cbcr_reg = MDSS_PCLK0_CBCR,
2869 .has_sibling = 0,
2870 .base = &virt_bases[GCC_BASE],
2871 .c = {
2872 .dbg_name = "gcc_mdss_pclk0_clk",
2873 .parent = &pclk0_clk_src.c,
2874 .ops = &clk_ops_branch,
2875 .flags = CLKFLAG_NO_RATE_CACHE,
2876 CLK_INIT(gcc_mdss_pclk0_clk.c),
2877 },
2878};
2879
2880static struct branch_clk gcc_mdss_pclk1_clk = {
2881 .cbcr_reg = MDSS_PCLK1_CBCR,
2882 .has_sibling = 0,
2883 .base = &virt_bases[GCC_BASE],
2884 .c = {
2885 .dbg_name = "gcc_mdss_pclk1_clk",
2886 .parent = &pclk1_clk_src.c,
2887 .ops = &clk_ops_branch,
2888 .flags = CLKFLAG_NO_RATE_CACHE,
2889 CLK_INIT(gcc_mdss_pclk1_clk.c),
2890 },
2891};
2892
2893static struct branch_clk gcc_mdss_vsync_clk = {
2894 .cbcr_reg = MDSS_VSYNC_CBCR,
2895 .has_sibling = 0,
2896 .base = &virt_bases[GCC_BASE],
2897 .c = {
2898 .dbg_name = "gcc_mdss_vsync_clk",
2899 .parent = &vsync_clk_src.c,
2900 .ops = &clk_ops_branch,
2901 CLK_INIT(gcc_mdss_vsync_clk.c),
2902 },
2903};
2904
2905static struct branch_clk gcc_mss_cfg_ahb_clk = {
2906 .cbcr_reg = MSS_CFG_AHB_CBCR,
2907 .has_sibling = 1,
2908 .base = &virt_bases[GCC_BASE],
2909 .c = {
2910 .dbg_name = "gcc_mss_cfg_ahb_clk",
2911 .ops = &clk_ops_branch,
2912 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
2913 },
2914};
2915
2916static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
2917 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
2918 .has_sibling = 1,
2919 .base = &virt_bases[GCC_BASE],
2920 .c = {
2921 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
2922 .ops = &clk_ops_branch,
2923 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
2924 },
2925};
2926
2927static struct local_vote_clk gcc_apss_tcu_clk;
2928static struct branch_clk gcc_bimc_gfx_clk = {
2929 .cbcr_reg = BIMC_GFX_CBCR,
2930 .has_sibling = 1,
2931 .base = &virt_bases[GCC_BASE],
2932 .c = {
2933 .dbg_name = "gcc_bimc_gfx_clk",
2934 .ops = &clk_ops_branch,
2935 CLK_INIT(gcc_bimc_gfx_clk.c),
2936 .depends = &gcc_apss_tcu_clk.c,
2937 },
2938};
2939
2940static struct branch_clk gcc_oxili_ahb_clk = {
2941 .cbcr_reg = OXILI_AHB_CBCR,
2942 .has_sibling = 1,
2943 .base = &virt_bases[GCC_BASE],
2944 .c = {
2945 .dbg_name = "gcc_oxili_ahb_clk",
2946 .ops = &clk_ops_branch,
2947 CLK_INIT(gcc_oxili_ahb_clk.c),
2948 },
2949};
2950
2951static struct branch_clk gcc_oxili_gfx3d_clk = {
2952 .cbcr_reg = OXILI_GFX3D_CBCR,
2953 .has_sibling = 0,
2954 .base = &virt_bases[GCC_BASE],
2955 .c = {
2956 .dbg_name = "gcc_oxili_gfx3d_clk",
2957 .parent = &gfx3d_clk_src.c,
2958 .ops = &clk_ops_branch,
2959 CLK_INIT(gcc_oxili_gfx3d_clk.c),
2960 },
2961};
2962
2963static struct branch_clk gcc_oxili_timer_clk = {
2964 .cbcr_reg = OXILI_TIMER_CBCR,
2965 .has_sibling = 0,
2966 .base = &virt_bases[GCC_BASE],
2967 .c = {
2968 .dbg_name = "gcc_oxili_timer_clk",
2969 .parent = &xo_clk_src.c,
2970 .ops = &clk_ops_branch,
2971 CLK_INIT(gcc_oxili_timer_clk.c),
2972 },
2973};
2974
2975static struct branch_clk gcc_oxili_aon_clk = {
2976 .cbcr_reg = OXILI_AON_CBCR,
2977 .has_sibling = 0,
2978 .base = &virt_bases[GCC_BASE],
2979 .c = {
2980 .dbg_name = "gcc_oxili_aon_clk",
2981 .parent = &gfx3d_clk_src.c,
2982 .ops = &clk_ops_branch,
2983 CLK_INIT(gcc_oxili_aon_clk.c),
2984 },
2985};
2986
2987static struct branch_clk gcc_pdm2_clk = {
2988 .cbcr_reg = PDM2_CBCR,
2989 .has_sibling = 0,
2990 .base = &virt_bases[GCC_BASE],
2991 .c = {
2992 .dbg_name = "gcc_pdm2_clk",
2993 .parent = &pdm2_clk_src.c,
2994 .ops = &clk_ops_branch,
2995 CLK_INIT(gcc_pdm2_clk.c),
2996 },
2997};
2998
2999static struct branch_clk gcc_pdm_ahb_clk = {
3000 .cbcr_reg = PDM_AHB_CBCR,
3001 .has_sibling = 1,
3002 .base = &virt_bases[GCC_BASE],
3003 .c = {
3004 .dbg_name = "gcc_pdm_ahb_clk",
3005 .ops = &clk_ops_branch,
3006 CLK_INIT(gcc_pdm_ahb_clk.c),
3007 },
3008};
3009
3010static struct local_vote_clk gcc_prng_ahb_clk = {
3011 .cbcr_reg = PRNG_AHB_CBCR,
3012 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
3013 .en_mask = BIT(8),
3014 .base = &virt_bases[GCC_BASE],
3015 .c = {
3016 .dbg_name = "gcc_prng_ahb_clk",
3017 .ops = &clk_ops_vote,
3018 CLK_INIT(gcc_prng_ahb_clk.c),
3019 },
3020};
3021
3022static struct local_vote_clk gcc_qdss_dap_clk = {
3023 .cbcr_reg = QDSS_DAP_CBCR,
3024 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
3025 .en_mask = BIT(21),
3026 .base = &virt_bases[GCC_BASE],
3027 .c = {
3028 .dbg_name = "gcc_qdss_dap_clk",
3029 .ops = &clk_ops_vote,
3030 CLK_INIT(gcc_qdss_dap_clk.c),
3031 },
3032};
3033
3034static struct branch_clk gcc_sdcc1_ahb_clk = {
3035 .cbcr_reg = SDCC1_AHB_CBCR,
3036 .has_sibling = 1,
3037 .base = &virt_bases[GCC_BASE],
3038 .c = {
3039 .dbg_name = "gcc_sdcc1_ahb_clk",
3040 .ops = &clk_ops_branch,
3041 CLK_INIT(gcc_sdcc1_ahb_clk.c),
3042 },
3043};
3044
3045static struct branch_clk gcc_sdcc1_apps_clk = {
3046 .cbcr_reg = SDCC1_APPS_CBCR,
3047 .has_sibling = 0,
3048 .base = &virt_bases[GCC_BASE],
3049 .c = {
3050 .dbg_name = "gcc_sdcc1_apps_clk",
3051 .parent = &sdcc1_apps_clk_src.c,
3052 .ops = &clk_ops_branch,
3053 CLK_INIT(gcc_sdcc1_apps_clk.c),
3054 },
3055};
3056
3057static struct branch_clk gcc_sdcc1_ice_core_clk = {
3058 .cbcr_reg = SDCC1_ICE_CORE_CBCR,
3059 .has_sibling = 0,
3060 .base = &virt_bases[GCC_BASE],
3061 .c = {
3062 .dbg_name = "gcc_sdcc1_ice_core_clk",
3063 .parent = &sdcc1_ice_core_clk_src.c,
3064 .ops = &clk_ops_branch,
3065 CLK_INIT(gcc_sdcc1_ice_core_clk.c),
3066 }
3067};
3068
3069static struct branch_clk gcc_sdcc2_ahb_clk = {
3070 .cbcr_reg = SDCC2_AHB_CBCR,
3071 .has_sibling = 1,
3072 .base = &virt_bases[GCC_BASE],
3073 .c = {
3074 .dbg_name = "gcc_sdcc2_ahb_clk",
3075 .ops = &clk_ops_branch,
3076 CLK_INIT(gcc_sdcc2_ahb_clk.c),
3077 },
3078};
3079
3080static struct branch_clk gcc_sdcc2_apps_clk = {
3081 .cbcr_reg = SDCC2_APPS_CBCR,
3082 .has_sibling = 0,
3083 .base = &virt_bases[GCC_BASE],
3084 .c = {
3085 .dbg_name = "gcc_sdcc2_apps_clk",
3086 .parent = &sdcc2_apps_clk_src.c,
3087 .ops = &clk_ops_branch,
3088 CLK_INIT(gcc_sdcc2_apps_clk.c),
3089 },
3090};
3091
3092static struct local_vote_clk gcc_cpp_tbu_clk = {
3093 .cbcr_reg = CPP_TBU_CBCR,
3094 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3095 .en_mask = BIT(14),
3096 .base = &virt_bases[GCC_BASE],
3097 .c = {
3098 .dbg_name = "gcc_cpp_tbu_clk",
3099 .ops = &clk_ops_vote,
3100 CLK_INIT(gcc_cpp_tbu_clk.c),
3101 },
3102};
3103
3104static struct local_vote_clk gcc_gfx_tbu_clk = {
3105 .cbcr_reg = GFX_TBU_CBCR,
3106 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3107 .en_mask = BIT(3),
3108 .base = &virt_bases[GCC_BASE],
3109 .c = {
3110 .dbg_name = "gcc_gfx_tbu_clk",
3111 .ops = &clk_ops_vote,
3112 CLK_INIT(gcc_gfx_tbu_clk.c),
3113 },
3114};
3115
3116static struct local_vote_clk gcc_gfx_tcu_clk = {
3117 .cbcr_reg = GFX_TCU_CBCR,
3118 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3119 .en_mask = BIT(2),
3120 .base = &virt_bases[GCC_BASE],
3121 .c = {
3122 .dbg_name = "gcc_gfx_tcu_clk",
3123 .ops = &clk_ops_vote,
3124 CLK_INIT(gcc_gfx_tcu_clk.c),
3125 },
3126};
3127
3128static struct local_vote_clk gcc_apss_tcu_clk = {
3129 .cbcr_reg = APSS_TCU_CBCR,
3130 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3131 .en_mask = BIT(1),
3132 .base = &virt_bases[GCC_BASE],
3133 .c = {
3134 .dbg_name = "gcc_apss_tcu_clk",
3135 .ops = &clk_ops_vote,
3136 CLK_INIT(gcc_apss_tcu_clk.c),
3137 },
3138};
3139
3140static struct local_vote_clk gcc_gtcu_ahb_clk = {
3141 .cbcr_reg = GTCU_AHB_CBCR,
3142 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3143 .en_mask = BIT(13),
3144 .base = &virt_bases[GCC_BASE],
3145 .c = {
3146 .dbg_name = "gcc_gtcu_ahb_clk",
3147 .ops = &clk_ops_vote,
3148 CLK_INIT(gcc_gtcu_ahb_clk.c),
3149 },
3150};
3151
3152static struct local_vote_clk gcc_ipa_tbu_clk = {
3153 .cbcr_reg = IPA_TBU_CBCR,
3154 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3155 .en_mask = BIT(16),
3156 .base = &virt_bases[GCC_BASE],
3157 .c = {
3158 .dbg_name = "gcc_ipa_tbu_clk",
3159 .ops = &clk_ops_vote,
3160 CLK_INIT(gcc_ipa_tbu_clk.c),
3161 },
3162};
3163
3164static struct local_vote_clk gcc_jpeg_tbu_clk = {
3165 .cbcr_reg = JPEG_TBU_CBCR,
3166 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3167 .en_mask = BIT(10),
3168 .base = &virt_bases[GCC_BASE],
3169 .c = {
3170 .dbg_name = "gcc_jpeg_tbu_clk",
3171 .ops = &clk_ops_vote,
3172 CLK_INIT(gcc_jpeg_tbu_clk.c),
3173 },
3174};
3175
3176static struct local_vote_clk gcc_mdp_tbu_clk = {
3177 .cbcr_reg = MDP_TBU_CBCR,
3178 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3179 .en_mask = BIT(4),
3180 .base = &virt_bases[GCC_BASE],
3181 .c = {
3182 .dbg_name = "gcc_mdp_tbu_clk",
3183 .ops = &clk_ops_vote,
3184 CLK_INIT(gcc_mdp_tbu_clk.c),
3185 },
3186};
3187
3188static struct local_vote_clk gcc_smmu_cfg_clk = {
3189 .cbcr_reg = SMMU_CFG_CBCR,
3190 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3191 .en_mask = BIT(12),
3192 .base = &virt_bases[GCC_BASE],
3193 .c = {
3194 .dbg_name = "gcc_smmu_cfg_clk",
3195 .ops = &clk_ops_vote,
3196 CLK_INIT(gcc_smmu_cfg_clk.c),
3197 },
3198};
3199
3200static struct local_vote_clk gcc_venus_tbu_clk = {
3201 .cbcr_reg = VENUS_TBU_CBCR,
3202 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3203 .en_mask = BIT(5),
3204 .base = &virt_bases[GCC_BASE],
3205 .c = {
3206 .dbg_name = "gcc_venus_tbu_clk",
3207 .ops = &clk_ops_vote,
3208 CLK_INIT(gcc_venus_tbu_clk.c),
3209 },
3210};
3211
3212static struct local_vote_clk gcc_vfe1_tbu_clk = {
3213 .cbcr_reg = VFE1_TBU_CBCR,
3214 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3215 .en_mask = BIT(17),
3216 .base = &virt_bases[GCC_BASE],
3217 .c = {
3218 .dbg_name = "gcc_vfe1_tbu_clk",
3219 .ops = &clk_ops_vote,
3220 CLK_INIT(gcc_vfe1_tbu_clk.c),
3221 },
3222};
3223
3224static struct local_vote_clk gcc_vfe_tbu_clk = {
3225 .cbcr_reg = VFE_TBU_CBCR,
3226 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3227 .en_mask = BIT(9),
3228 .base = &virt_bases[GCC_BASE],
3229 .c = {
3230 .dbg_name = "gcc_vfe_tbu_clk",
3231 .ops = &clk_ops_vote,
3232 CLK_INIT(gcc_vfe_tbu_clk.c),
3233 },
3234};
3235
3236static struct branch_clk gcc_usb2a_phy_sleep_clk = {
3237 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
3238 .has_sibling = 1,
3239 .base = &virt_bases[GCC_BASE],
3240 .c = {
3241 .dbg_name = "gcc_usb2a_phy_sleep_clk",
3242 .ops = &clk_ops_branch,
3243 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
3244 },
3245};
3246
3247static struct branch_clk gcc_usb_hs_phy_cfg_ahb_clk = {
3248 .cbcr_reg = USB_HS_PHY_CFG_AHB_CBCR,
3249 .has_sibling = 1,
3250 .base = &virt_bases[GCC_BASE],
3251 .c = {
3252 .dbg_name = "gcc_usb_hs_phy_cfg_ahb_clk",
3253 .ops = &clk_ops_branch,
3254 CLK_INIT(gcc_usb_hs_phy_cfg_ahb_clk.c),
3255 },
3256};
3257
3258static struct branch_clk gcc_usb_fs_ahb_clk = {
3259 .cbcr_reg = USB_FS_AHB_CBCR,
3260 .has_sibling = 1,
3261 .base = &virt_bases[GCC_BASE],
3262 .c = {
3263 .dbg_name = "gcc_usb_fs_ahb_clk",
3264 .ops = &clk_ops_branch,
3265 CLK_INIT(gcc_usb_fs_ahb_clk.c),
3266 },
3267};
3268
3269static struct branch_clk gcc_usb_fs_ic_clk = {
3270 .cbcr_reg = USB_FS_IC_CBCR,
3271 .has_sibling = 0,
3272 .base = &virt_bases[GCC_BASE],
3273 .c = {
3274 .dbg_name = "gcc_usb_fs_ic_clk",
3275 .parent = &usb_fs_ic_clk_src.c,
3276 .ops = &clk_ops_branch,
3277 CLK_INIT(gcc_usb_fs_ic_clk.c),
3278 },
3279};
3280
3281static struct branch_clk gcc_usb_fs_system_clk = {
3282 .cbcr_reg = USB_FS_SYSTEM_CBCR,
3283 .bcr_reg = USB_FS_BCR,
3284 .has_sibling = 0,
3285 .base = &virt_bases[GCC_BASE],
3286 .c = {
3287 .dbg_name = "gcc_usb_fs_system_clk",
3288 .parent = &usb_fs_system_clk_src.c,
3289 .ops = &clk_ops_branch,
3290 CLK_INIT(gcc_usb_fs_system_clk.c),
3291 },
3292};
3293
3294static struct branch_clk gcc_usb_hs_ahb_clk = {
3295 .cbcr_reg = USB_HS_AHB_CBCR,
3296 .has_sibling = 1,
3297 .base = &virt_bases[GCC_BASE],
3298 .c = {
3299 .dbg_name = "gcc_usb_hs_ahb_clk",
3300 .ops = &clk_ops_branch,
3301 CLK_INIT(gcc_usb_hs_ahb_clk.c),
3302 },
3303};
3304
3305static struct branch_clk gcc_usb_hs_system_clk = {
3306 .cbcr_reg = USB_HS_SYSTEM_CBCR,
3307 .bcr_reg = USB_HS_BCR,
3308 .has_sibling = 0,
3309 .base = &virt_bases[GCC_BASE],
3310 .c = {
3311 .dbg_name = "gcc_usb_hs_system_clk",
3312 .parent = &usb_hs_system_clk_src.c,
3313 .ops = &clk_ops_branch,
3314 CLK_INIT(gcc_usb_hs_system_clk.c),
3315 },
3316};
3317
3318static struct reset_clk gcc_usb2_hs_phy_only_clk = {
3319 .reset_reg = USB2_HS_PHY_ONLY_BCR,
3320 .base = &virt_bases[GCC_BASE],
3321 .c = {
3322 .dbg_name = "gcc_usb2_hs_phy_only_clk",
3323 .ops = &clk_ops_rst,
3324 CLK_INIT(gcc_usb2_hs_phy_only_clk.c),
3325 },
3326};
3327
3328static struct reset_clk gcc_qusb2_phy_clk = {
3329 .reset_reg = QUSB2_PHY_BCR,
3330 .base = &virt_bases[GCC_BASE],
3331 .c = {
3332 .dbg_name = "gcc_qusb2_phy_clk",
3333 .ops = &clk_ops_rst,
3334 CLK_INIT(gcc_qusb2_phy_clk.c),
3335 },
3336};
3337
3338static struct branch_clk gcc_venus0_ahb_clk = {
3339 .cbcr_reg = VENUS0_AHB_CBCR,
3340 .has_sibling = 1,
3341 .base = &virt_bases[GCC_BASE],
3342 .c = {
3343 .dbg_name = "gcc_venus0_ahb_clk",
3344 .ops = &clk_ops_branch,
3345 CLK_INIT(gcc_venus0_ahb_clk.c),
3346 },
3347};
3348
3349static struct branch_clk gcc_venus0_axi_clk = {
3350 .cbcr_reg = VENUS0_AXI_CBCR,
3351 .has_sibling = 1,
3352 .base = &virt_bases[GCC_BASE],
3353 .c = {
3354 .dbg_name = "gcc_venus0_axi_clk",
3355 .ops = &clk_ops_branch,
3356 CLK_INIT(gcc_venus0_axi_clk.c),
3357 },
3358};
3359
3360static struct branch_clk gcc_venus0_core0_vcodec0_clk = {
3361 .cbcr_reg = VENUS0_CORE0_VCODEC0_CBCR,
3362 .has_sibling = 1,
3363 .base = &virt_bases[GCC_BASE],
3364 .c = {
3365 .dbg_name = "gcc_venus0_core0_vcodec0_clk",
3366 .parent = &vcodec0_clk_src.c,
3367 .ops = &clk_ops_branch,
3368 CLK_INIT(gcc_venus0_core0_vcodec0_clk.c),
3369 },
3370};
3371
3372static struct branch_clk gcc_venus0_core1_vcodec0_clk = {
3373 .cbcr_reg = VENUS0_CORE1_VCODEC0_CBCR,
3374 .has_sibling = 1,
3375 .base = &virt_bases[GCC_BASE],
3376 .c = {
3377 .dbg_name = "gcc_venus0_core1_vcodec0_clk",
3378 .parent = &vcodec0_clk_src.c,
3379 .ops = &clk_ops_branch,
3380 CLK_INIT(gcc_venus0_core1_vcodec0_clk.c),
3381 },
3382};
3383
3384static struct branch_clk gcc_venus0_vcodec0_clk = {
3385 .cbcr_reg = VENUS0_VCODEC0_CBCR,
3386 .has_sibling = 0,
3387 .base = &virt_bases[GCC_BASE],
3388 .c = {
3389 .dbg_name = "gcc_venus0_vcodec0_clk",
3390 .parent = &vcodec0_clk_src.c,
3391 .ops = &clk_ops_branch,
3392 CLK_INIT(gcc_venus0_vcodec0_clk.c),
3393 },
3394};
3395
3396static struct clk_ops clk_ops_debug_mux;
3397
3398static void __iomem *meas_base;
3399
3400static struct measure_clk apc0_m_clk = {
3401 .c = {
3402 .ops = &clk_ops_empty,
3403 .dbg_name = "apc0_m_clk",
3404 CLK_INIT(apc0_m_clk.c),
3405 },
3406};
3407
3408static struct measure_clk apc1_m_clk = {
3409 .c = {
3410 .ops = &clk_ops_empty,
3411 .dbg_name = "apc1_m_clk",
3412 CLK_INIT(apc1_m_clk.c),
3413 },
3414};
3415
3416static struct measure_clk cci_m_clk = {
3417 .c = {
3418 .ops = &clk_ops_empty,
3419 .dbg_name = "cci_m_clk",
3420 CLK_INIT(cci_m_clk.c),
3421 },
3422};
3423
3424static struct mux_clk apss_debug_ter_mux = {
3425 .ops = &mux_reg_ops,
3426 .mask = 0x3,
3427 .shift = 8,
3428 MUX_SRC_LIST(
3429 {&apc0_m_clk.c, 0},
3430 {&apc1_m_clk.c, 1},
3431 {&cci_m_clk.c, 2},
3432 ),
3433 .base = &meas_base,
3434 .c = {
3435 .dbg_name = "apss_debug_ter_mux",
3436 .ops = &clk_ops_gen_mux,
3437 CLK_INIT(apss_debug_ter_mux.c),
3438 },
3439};
3440
3441static struct mux_clk apss_debug_sec_mux = {
3442 .ops = &mux_reg_ops,
3443 .mask = 0x7,
3444 .shift = 12,
3445 MUX_SRC_LIST(
3446 {&apss_debug_ter_mux.c, 0},
3447 ),
3448 MUX_REC_SRC_LIST(
3449 &apss_debug_ter_mux.c,
3450 ),
3451 .base = &meas_base,
3452 .c = {
3453 .dbg_name = "apss_debug_sec_mux",
3454 .ops = &clk_ops_gen_mux,
3455 CLK_INIT(apss_debug_sec_mux.c),
3456 },
3457};
3458
3459static struct mux_clk apss_debug_pri_mux = {
3460 .ops = &mux_reg_ops,
3461 .mask = 0x3,
3462 .shift = 16,
3463 MUX_SRC_LIST(
3464 {&apss_debug_sec_mux.c, 0},
3465 ),
3466 MUX_REC_SRC_LIST(
3467 &apss_debug_sec_mux.c,
3468 ),
3469 .base = &meas_base,
3470 .c = {
3471 .dbg_name = "apss_debug_pri_mux",
3472 .ops = &clk_ops_gen_mux,
3473 CLK_INIT(apss_debug_pri_mux.c),
3474 },
3475};
3476
3477static struct measure_clk_data debug_mux_priv = {
3478 .cxo = &xo_clk_src.c,
3479 .plltest_reg = GCC_PLLTEST_PAD_CFG,
3480 .plltest_val = 0x51A00,
3481 .xo_div4_cbcr = GCC_XO_DIV4_CBCR,
3482 .ctl_reg = CLOCK_FRQ_MEASURE_CTL,
3483 .status_reg = CLOCK_FRQ_MEASURE_STATUS,
3484 .base = &virt_bases[GCC_BASE],
3485};
3486
3487static struct mux_clk gcc_debug_mux = {
3488 .priv = &debug_mux_priv,
3489 .ops = &mux_reg_ops,
3490 .offset = GCC_DEBUG_CLK_CTL,
3491 .mask = 0x1FF,
3492 .en_offset = GCC_DEBUG_CLK_CTL,
3493 .en_mask = BIT(16),
3494 .base = &virt_bases[GCC_BASE],
3495 MUX_REC_SRC_LIST(
3496 &apss_debug_pri_mux.c,
3497 ),
3498 MUX_SRC_LIST(
3499 { &apss_debug_pri_mux.c, 0x016A},
3500 { &snoc_clk.c, 0x0000 },
3501 { &sysmmnoc_clk.c, 0x0001 },
3502 { &pnoc_clk.c, 0x0008 },
3503 { &bimc_clk.c, 0x0154 },
3504 { &gcc_gp1_clk.c, 0x0010 },
3505 { &gcc_gp2_clk.c, 0x0011 },
3506 { &gcc_gp3_clk.c, 0x0012 },
3507 { &gcc_bimc_gfx_clk.c, 0x002d },
3508 { &gcc_mss_cfg_ahb_clk.c, 0x0030 },
3509 { &gcc_mss_q6_bimc_axi_clk.c, 0x0031 },
3510 { &gcc_apss_tcu_clk.c, 0x0050 },
3511 { &gcc_mdp_tbu_clk.c, 0x0051 },
3512 { &gcc_gfx_tbu_clk.c, 0x0052 },
3513 { &gcc_gfx_tcu_clk.c, 0x0053 },
3514 { &gcc_venus_tbu_clk.c, 0x0054 },
3515 { &gcc_gtcu_ahb_clk.c, 0x0058 },
3516 { &gcc_vfe_tbu_clk.c, 0x005a },
3517 { &gcc_smmu_cfg_clk.c, 0x005b },
3518 { &gcc_jpeg_tbu_clk.c, 0x005c },
3519 { &gcc_usb_hs_system_clk.c, 0x0060 },
3520 { &gcc_usb_hs_ahb_clk.c, 0x0061 },
3521 { &gcc_usb2a_phy_sleep_clk.c, 0x0063 },
3522 { &gcc_usb_hs_phy_cfg_ahb_clk.c, 0x0064 },
3523 { &gcc_sdcc1_apps_clk.c, 0x0068 },
3524 { &gcc_sdcc1_ahb_clk.c, 0x0069 },
3525 { &gcc_sdcc1_ice_core_clk.c, 0x006a },
3526 { &gcc_sdcc2_apps_clk.c, 0x0070 },
3527 { &gcc_sdcc2_ahb_clk.c, 0x0071 },
3528 { &gcc_blsp1_ahb_clk.c, 0x0088 },
3529 { &gcc_blsp1_qup1_spi_apps_clk.c, 0x008a },
3530 { &gcc_blsp1_qup1_i2c_apps_clk.c, 0x008b },
3531 { &gcc_blsp1_uart1_apps_clk.c, 0x008c },
3532 { &gcc_blsp1_qup2_spi_apps_clk.c, 0x008e },
3533 { &gcc_blsp1_qup2_i2c_apps_clk.c, 0x0090 },
3534 { &gcc_blsp1_uart2_apps_clk.c, 0x0091 },
3535 { &gcc_blsp1_qup3_spi_apps_clk.c, 0x0093 },
3536 { &gcc_blsp1_qup3_i2c_apps_clk.c, 0x0094 },
3537 { &gcc_blsp1_qup4_spi_apps_clk.c, 0x0095 },
3538 { &gcc_blsp1_qup4_i2c_apps_clk.c, 0x0096 },
3539 { &gcc_blsp2_ahb_clk.c, 0x0098 },
3540 { &gcc_blsp2_qup1_spi_apps_clk.c, 0x009a },
3541 { &gcc_blsp2_qup1_i2c_apps_clk.c, 0x009b },
3542 { &gcc_blsp2_uart1_apps_clk.c, 0x009c },
3543 { &gcc_blsp2_qup2_spi_apps_clk.c, 0x009e },
3544 { &gcc_blsp2_qup2_i2c_apps_clk.c, 0x00a0 },
3545 { &gcc_blsp2_uart2_apps_clk.c, 0x00a1 },
3546 { &gcc_blsp2_qup3_spi_apps_clk.c, 0x00a3 },
3547 { &gcc_blsp2_qup3_i2c_apps_clk.c, 0x00a4 },
3548 { &gcc_blsp2_qup4_spi_apps_clk.c, 0x00a5 },
3549 { &gcc_blsp2_qup4_i2c_apps_clk.c, 0x00a6 },
3550 { &gcc_camss_ahb_clk.c, 0x00a8 },
3551 { &gcc_camss_top_ahb_clk.c, 0x00a9 },
3552 { &gcc_camss_micro_ahb_clk.c, 0x00aa },
3553 { &gcc_camss_gp0_clk.c, 0x00ab },
3554 { &gcc_camss_gp1_clk.c, 0x00ac },
3555 { &gcc_camss_mclk0_clk.c, 0x00ad },
3556 { &gcc_camss_mclk1_clk.c, 0x00ae },
3557 { &gcc_camss_cci_clk.c, 0x00af },
3558 { &gcc_camss_cci_ahb_clk.c, 0x00b0 },
3559 { &gcc_camss_csi0phytimer_clk.c, 0x00b1 },
3560 { &gcc_camss_csi1phytimer_clk.c, 0x00b2 },
3561 { &gcc_camss_jpeg0_clk.c, 0x00b3 },
3562 { &gcc_camss_jpeg_ahb_clk.c, 0x00b4 },
3563 { &gcc_camss_jpeg_axi_clk.c, 0x00b5 },
3564 { &gcc_camss_vfe0_clk.c, 0x00b8 },
3565 { &gcc_camss_cpp_clk.c, 0x00b9 },
3566 { &gcc_camss_cpp_ahb_clk.c, 0x00ba },
3567 { &gcc_camss_vfe_ahb_clk.c, 0x00bb },
3568 { &gcc_camss_vfe_axi_clk.c, 0x00bc },
3569 { &gcc_camss_csi_vfe0_clk.c, 0x00bf },
3570 { &gcc_camss_csi0_clk.c, 0x00c0 },
3571 { &gcc_camss_csi0_ahb_clk.c, 0x00c1 },
3572 { &gcc_camss_csi0phy_clk.c, 0x00c2 },
3573 { &gcc_camss_csi0rdi_clk.c, 0x00c3 },
3574 { &gcc_camss_csi0pix_clk.c, 0x00c4 },
3575 { &gcc_camss_csi1_clk.c, 0x00c5 },
3576 { &gcc_camss_csi1_ahb_clk.c, 0x00c6 },
3577 { &gcc_camss_csi1phy_clk.c, 0x00c7 },
3578 { &gcc_pdm_ahb_clk.c, 0x00d0 },
3579 { &gcc_pdm2_clk.c, 0x00d2 },
3580 { &gcc_prng_ahb_clk.c, 0x00d8 },
3581 { &gcc_camss_csi1rdi_clk.c, 0x00e0 },
3582 { &gcc_camss_csi1pix_clk.c, 0x00e1 },
3583 { &gcc_camss_ispif_ahb_clk.c, 0x00e2 },
3584 { &gcc_camss_csi2_clk.c, 0x00e3 },
3585 { &gcc_camss_csi2_ahb_clk.c, 0x00e4 },
3586 { &gcc_camss_csi2phy_clk.c, 0x00e5 },
3587 { &gcc_camss_csi2rdi_clk.c, 0x00e6 },
3588 { &gcc_camss_csi2pix_clk.c, 0x00e7 },
3589 { &gcc_cpp_tbu_clk.c, 0x00e9 },
3590 { &gcc_boot_rom_ahb_clk.c, 0x00f8 },
3591 { &gcc_usb_fs_ahb_clk.c, 0x00f1 },
3592 { &gcc_usb_fs_ic_clk.c, 0x00f4 },
3593 { &gcc_crypto_clk.c, 0x0138 },
3594 { &gcc_crypto_axi_clk.c, 0x0139 },
3595 { &gcc_crypto_ahb_clk.c, 0x013a },
3596 { &gcc_bimc_gpu_clk.c, 0x0157 },
3597 { &gcc_ipa_tbu_clk.c, 0x0198 },
3598 { &gcc_vfe1_tbu_clk.c, 0x0199 },
3599 { &gcc_camss_csi_vfe1_clk.c, 0x01a0 },
3600 { &gcc_camss_vfe1_clk.c, 0x01a1 },
3601 { &gcc_camss_vfe1_ahb_clk.c, 0x01a2 },
3602 { &gcc_camss_vfe1_axi_clk.c, 0x01a3 },
3603 { &gcc_venus0_core0_vcodec0_clk.c, 0x01b8 },
3604 { &gcc_venus0_core1_vcodec0_clk.c, 0x01b9 },
3605 { &gcc_camss_mclk2_clk.c, 0x01bd },
3606 { &gcc_oxili_timer_clk.c, 0x01e9 },
3607 { &gcc_oxili_gfx3d_clk.c, 0x01ea },
3608 { &gcc_oxili_ahb_clk.c, 0x01eb },
3609 { &gcc_oxili_gmem_clk.c, 0x01f0 },
3610 { &gcc_venus0_vcodec0_clk.c, 0x01f1 },
3611 { &gcc_venus0_axi_clk.c, 0x01f2 },
3612 { &gcc_venus0_ahb_clk.c, 0x01f3 },
3613 { &gcc_mdss_ahb_clk.c, 0x01f6 },
3614 { &gcc_mdss_axi_clk.c, 0x01f7 },
3615 { &gcc_mdss_pclk0_clk.c, 0x01f8 },
3616 { &gcc_mdss_mdp_clk.c, 0x01f9 },
3617 { &gcc_mdss_vsync_clk.c, 0x01fb },
3618 { &gcc_mdss_byte0_clk.c, 0x01fc },
3619 { &gcc_mdss_esc0_clk.c, 0x01fd },
3620 { &wcnss_m_clk.c, 0x0ec },
3621 ),
3622 .c = {
3623 .dbg_name = "gcc_debug_mux",
3624 .ops = &clk_ops_debug_mux,
3625 .flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE,
3626 CLK_INIT(gcc_debug_mux.c),
3627 },
3628};
3629
3630static struct mux_clk gcc_debug_mux_8937 = {
3631 .priv = &debug_mux_priv,
3632 .ops = &mux_reg_ops,
3633 .offset = GCC_DEBUG_CLK_CTL,
3634 .mask = 0x1FF,
3635 .en_offset = GCC_DEBUG_CLK_CTL,
3636 .en_mask = BIT(16),
3637 .base = &virt_bases[GCC_BASE],
3638 MUX_REC_SRC_LIST(
3639 &apss_debug_pri_mux.c,
3640 ),
3641 MUX_SRC_LIST(
3642 { &apss_debug_pri_mux.c, 0x016A},
3643 { &snoc_clk.c, 0x0000 },
3644 { &sysmmnoc_clk.c, 0x0001 },
3645 { &pnoc_clk.c, 0x0008 },
3646 { &bimc_clk.c, 0x015A },
3647 { &ipa_clk.c, 0x1B0 },
3648 { &gcc_gp1_clk.c, 0x0010 },
3649 { &gcc_gp2_clk.c, 0x0011 },
3650 { &gcc_gp3_clk.c, 0x0012 },
3651 { &gcc_bimc_gfx_clk.c, 0x002d },
3652 { &gcc_mss_cfg_ahb_clk.c, 0x0030 },
3653 { &gcc_mss_q6_bimc_axi_clk.c, 0x0031 },
3654 { &gcc_qdss_dap_clk.c, 0x0049 },
3655 { &gcc_apss_tcu_clk.c, 0x0050 },
3656 { &gcc_mdp_tbu_clk.c, 0x0051 },
3657 { &gcc_gfx_tbu_clk.c, 0x0052 },
3658 { &gcc_gfx_tcu_clk.c, 0x0053 },
3659 { &gcc_venus_tbu_clk.c, 0x0054 },
3660 { &gcc_gtcu_ahb_clk.c, 0x0058 },
3661 { &gcc_vfe_tbu_clk.c, 0x005a },
3662 { &gcc_smmu_cfg_clk.c, 0x005b },
3663 { &gcc_jpeg_tbu_clk.c, 0x005c },
3664 { &gcc_usb_hs_system_clk.c, 0x0060 },
3665 { &gcc_usb_hs_ahb_clk.c, 0x0061 },
3666 { &gcc_usb2a_phy_sleep_clk.c, 0x0063 },
3667 { &gcc_usb_hs_phy_cfg_ahb_clk.c, 0x0064 },
3668 { &gcc_sdcc1_apps_clk.c, 0x0068 },
3669 { &gcc_sdcc1_ahb_clk.c, 0x0069 },
3670 { &gcc_sdcc1_ice_core_clk.c, 0x006a },
3671 { &gcc_sdcc2_apps_clk.c, 0x0070 },
3672 { &gcc_sdcc2_ahb_clk.c, 0x0071 },
3673 { &gcc_blsp1_ahb_clk.c, 0x0088 },
3674 { &gcc_blsp1_qup1_spi_apps_clk.c, 0x008a },
3675 { &gcc_blsp1_qup1_i2c_apps_clk.c, 0x008b },
3676 { &gcc_blsp1_uart1_apps_clk.c, 0x008c },
3677 { &gcc_blsp1_qup2_spi_apps_clk.c, 0x008e },
3678 { &gcc_blsp1_qup2_i2c_apps_clk.c, 0x0090 },
3679 { &gcc_blsp1_uart2_apps_clk.c, 0x0091 },
3680 { &gcc_blsp1_qup3_spi_apps_clk.c, 0x0093 },
3681 { &gcc_blsp1_qup3_i2c_apps_clk.c, 0x0094 },
3682 { &gcc_blsp1_qup4_spi_apps_clk.c, 0x0095 },
3683 { &gcc_blsp1_qup4_i2c_apps_clk.c, 0x0096 },
3684 { &gcc_blsp2_ahb_clk.c, 0x0098 },
3685 { &gcc_blsp2_qup1_spi_apps_clk.c, 0x009a },
3686 { &gcc_blsp2_qup1_i2c_apps_clk.c, 0x009b },
3687 { &gcc_blsp2_uart1_apps_clk.c, 0x009c },
3688 { &gcc_blsp2_qup2_spi_apps_clk.c, 0x009e },
3689 { &gcc_blsp2_qup2_i2c_apps_clk.c, 0x00a0 },
3690 { &gcc_blsp2_uart2_apps_clk.c, 0x00a1 },
3691 { &gcc_blsp2_qup3_spi_apps_clk.c, 0x00a3 },
3692 { &gcc_blsp2_qup3_i2c_apps_clk.c, 0x00a4 },
3693 { &gcc_blsp2_qup4_spi_apps_clk.c, 0x00a5 },
3694 { &gcc_blsp2_qup4_i2c_apps_clk.c, 0x00a6 },
3695 { &gcc_camss_ahb_clk.c, 0x00a8 },
3696 { &gcc_camss_top_ahb_clk.c, 0x00a9 },
3697 { &gcc_camss_micro_ahb_clk.c, 0x00aa },
3698 { &gcc_camss_gp0_clk.c, 0x00ab },
3699 { &gcc_camss_gp1_clk.c, 0x00ac },
3700 { &gcc_camss_mclk0_clk.c, 0x00ad },
3701 { &gcc_camss_mclk1_clk.c, 0x00ae },
3702 { &gcc_camss_cci_clk.c, 0x00af },
3703 { &gcc_camss_cci_ahb_clk.c, 0x00b0 },
3704 { &gcc_camss_csi0phytimer_clk.c, 0x00b1 },
3705 { &gcc_camss_csi1phytimer_clk.c, 0x00b2 },
3706 { &gcc_camss_jpeg0_clk.c, 0x00b3 },
3707 { &gcc_camss_jpeg_ahb_clk.c, 0x00b4 },
3708 { &gcc_camss_jpeg_axi_clk.c, 0x00b5 },
3709 { &gcc_camss_vfe0_clk.c, 0x00b8 },
3710 { &gcc_camss_cpp_clk.c, 0x00b9 },
3711 { &gcc_camss_cpp_ahb_clk.c, 0x00ba },
3712 { &gcc_camss_vfe_ahb_clk.c, 0x00bb },
3713 { &gcc_camss_vfe_axi_clk.c, 0x00bc },
3714 { &gcc_camss_csi_vfe0_clk.c, 0x00bf },
3715 { &gcc_camss_csi0_clk.c, 0x00c0 },
3716 { &gcc_camss_csi0_ahb_clk.c, 0x00c1 },
3717 { &gcc_camss_csi0phy_clk.c, 0x00c2 },
3718 { &gcc_camss_csi0rdi_clk.c, 0x00c3 },
3719 { &gcc_camss_csi0pix_clk.c, 0x00c4 },
3720 { &gcc_camss_csi1_clk.c, 0x00c5 },
3721 { &gcc_camss_csi1_ahb_clk.c, 0x00c6 },
3722 { &gcc_camss_csi1phy_clk.c, 0x00c7 },
3723 { &gcc_pdm_ahb_clk.c, 0x00d0 },
3724 { &gcc_pdm2_clk.c, 0x00d2 },
3725 { &gcc_prng_ahb_clk.c, 0x00d8 },
3726 { &gcc_camss_csi1rdi_clk.c, 0x00e0 },
3727 { &gcc_camss_csi1pix_clk.c, 0x00e1 },
3728 { &gcc_camss_ispif_ahb_clk.c, 0x00e2 },
3729 { &gcc_camss_csi2_clk.c, 0x00e3 },
3730 { &gcc_camss_csi2_ahb_clk.c, 0x00e4 },
3731 { &gcc_camss_csi2phy_clk.c, 0x00e5 },
3732 { &gcc_camss_csi2rdi_clk.c, 0x00e6 },
3733 { &gcc_camss_csi2pix_clk.c, 0x00e7 },
3734 { &gcc_cpp_tbu_clk.c, 0x00e9 },
3735 { &gcc_boot_rom_ahb_clk.c, 0x00f8 },
3736 { &gcc_crypto_clk.c, 0x0138 },
3737 { &gcc_crypto_axi_clk.c, 0x0139 },
3738 { &gcc_crypto_ahb_clk.c, 0x013a },
3739 { &gcc_bimc_gpu_clk.c, 0x0157 },
3740 { &gcc_ipa_tbu_clk.c, 0x0198 },
3741 { &gcc_vfe1_tbu_clk.c, 0x0199 },
3742 { &gcc_camss_csi_vfe1_clk.c, 0x01a0 },
3743 { &gcc_camss_vfe1_clk.c, 0x01a1 },
3744 { &gcc_camss_vfe1_ahb_clk.c, 0x01a2 },
3745 { &gcc_camss_vfe1_axi_clk.c, 0x01a3 },
3746 { &gcc_camss_cpp_axi_clk.c, 0x01a4 },
3747 { &gcc_venus0_core0_vcodec0_clk.c, 0x01b8 },
3748 { &gcc_dcc_clk.c, 0x01b9 },
3749 { &gcc_camss_mclk2_clk.c, 0x01bd },
3750 { &gcc_oxili_timer_clk.c, 0x01e9 },
3751 { &gcc_oxili_gfx3d_clk.c, 0x01ea },
3752 { &gcc_oxili_aon_clk.c, 0x00ee },
3753 { &gcc_oxili_ahb_clk.c, 0x01eb },
3754 { &gcc_venus0_vcodec0_clk.c, 0x01f1 },
3755 { &gcc_venus0_axi_clk.c, 0x01f2 },
3756 { &gcc_venus0_ahb_clk.c, 0x01f3 },
3757 { &gcc_mdss_ahb_clk.c, 0x01f6 },
3758 { &gcc_mdss_axi_clk.c, 0x01f7 },
3759 { &gcc_mdss_pclk0_clk.c, 0x01f8 },
3760 { &gcc_mdss_pclk1_clk.c, 0x01e3 },
3761 { &gcc_mdss_mdp_clk.c, 0x01f9 },
3762 { &gcc_mdss_vsync_clk.c, 0x01fb },
3763 { &gcc_mdss_byte0_clk.c, 0x01fc },
3764 { &gcc_mdss_byte1_clk.c, 0x01e4 },
3765 { &gcc_mdss_esc0_clk.c, 0x01fd },
3766 { &gcc_mdss_esc1_clk.c, 0x01e5 },
3767 { &wcnss_m_clk.c, 0x0ec },
3768 ),
3769 .c = {
3770 .dbg_name = "gcc_debug_mux_8937",
3771 .ops = &clk_ops_debug_mux,
3772 .flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE,
3773 CLK_INIT(gcc_debug_mux_8937.c),
3774 },
3775};
3776
3777/* Clock lookup */
3778static struct clk_lookup msm_clocks_lookup_common[] = {
3779 /* RPM clocks */
3780 CLK_LIST(xo_clk_src),
3781 CLK_LIST(xo_a_clk_src),
3782 CLK_LIST(xo_otg_clk),
3783 CLK_LIST(xo_lpm_clk),
3784 CLK_LIST(xo_pil_mss_clk),
3785 CLK_LIST(xo_pil_pronto_clk),
3786 CLK_LIST(xo_wlan_clk),
3787 CLK_LIST(xo_pil_lpass_clk),
3788
3789 CLK_LIST(sysmmnoc_msmbus_clk),
3790 CLK_LIST(snoc_msmbus_clk),
3791 CLK_LIST(snoc_msmbus_a_clk),
3792 CLK_LIST(sysmmnoc_msmbus_a_clk),
3793 CLK_LIST(pnoc_msmbus_clk),
3794 CLK_LIST(pnoc_msmbus_a_clk),
3795 CLK_LIST(bimc_msmbus_clk),
3796 CLK_LIST(bimc_msmbus_a_clk),
3797 CLK_LIST(pnoc_keepalive_a_clk),
3798
3799 CLK_LIST(pnoc_usb_a_clk),
3800 CLK_LIST(snoc_usb_a_clk),
3801 CLK_LIST(bimc_usb_a_clk),
3802 CLK_LIST(pnoc_usb_clk),
3803 CLK_LIST(snoc_usb_clk),
3804 CLK_LIST(bimc_usb_clk),
3805
3806 CLK_LIST(snoc_wcnss_a_clk),
3807 CLK_LIST(bimc_wcnss_a_clk),
3808
3809 CLK_LIST(qdss_clk),
3810 CLK_LIST(qdss_a_clk),
3811
3812 CLK_LIST(snoc_clk),
3813 CLK_LIST(sysmmnoc_clk),
3814 CLK_LIST(pnoc_clk),
3815 CLK_LIST(bimc_clk),
3816 CLK_LIST(snoc_a_clk),
3817 CLK_LIST(sysmmnoc_a_clk),
3818 CLK_LIST(pnoc_a_clk),
3819 CLK_LIST(bimc_a_clk),
3820
3821 CLK_LIST(bb_clk1),
3822 CLK_LIST(bb_clk1_a),
3823 CLK_LIST(bb_clk2),
3824 CLK_LIST(bb_clk2_a),
3825 CLK_LIST(rf_clk2),
3826 CLK_LIST(rf_clk2_a),
3827 CLK_LIST(div_clk2),
3828 CLK_LIST(div_clk2_a),
3829
3830 CLK_LIST(bb_clk1_pin),
3831 CLK_LIST(bb_clk1_a_pin),
3832 CLK_LIST(bb_clk2_pin),
3833 CLK_LIST(bb_clk2_a_pin),
3834
3835 CLK_LIST(gpll0_clk_src),
3836 CLK_LIST(gpll0_ao_clk_src),
3837 CLK_LIST(gpll6_clk_src),
3838 CLK_LIST(gpll4_clk_src),
3839 CLK_LIST(gpll3_clk_src),
3840 CLK_LIST(a53ss_c1_pll),
3841 CLK_LIST(gcc_blsp1_ahb_clk),
3842 CLK_LIST(gcc_blsp2_ahb_clk),
3843 CLK_LIST(gcc_boot_rom_ahb_clk),
3844 CLK_LIST(gcc_crypto_ahb_clk),
3845 CLK_LIST(gcc_crypto_axi_clk),
3846 CLK_LIST(gcc_crypto_clk),
3847 CLK_LIST(gcc_prng_ahb_clk),
3848 CLK_LIST(gcc_cpp_tbu_clk),
3849 CLK_LIST(gcc_apss_tcu_clk),
3850 CLK_LIST(gcc_jpeg_tbu_clk),
3851 CLK_LIST(gcc_mdp_tbu_clk),
3852 CLK_LIST(gcc_smmu_cfg_clk),
3853 CLK_LIST(gcc_venus_tbu_clk),
3854 CLK_LIST(gcc_vfe1_tbu_clk),
3855 CLK_LIST(gcc_vfe_tbu_clk),
3856 CLK_LIST(camss_top_ahb_clk_src),
3857 CLK_LIST(apss_ahb_clk_src),
3858 CLK_LIST(csi0_clk_src),
3859 CLK_LIST(csi1_clk_src),
3860 CLK_LIST(csi2_clk_src),
3861 CLK_LIST(vcodec0_clk_src),
3862 CLK_LIST(vfe0_clk_src),
3863 CLK_LIST(vfe1_clk_src),
3864 CLK_LIST(gfx3d_clk_src),
3865 CLK_LIST(blsp1_qup2_i2c_apps_clk_src),
3866 CLK_LIST(blsp1_qup2_spi_apps_clk_src),
3867 CLK_LIST(blsp1_qup3_i2c_apps_clk_src),
3868 CLK_LIST(blsp1_qup3_spi_apps_clk_src),
3869 CLK_LIST(blsp1_qup4_i2c_apps_clk_src),
3870 CLK_LIST(blsp1_qup4_spi_apps_clk_src),
3871 CLK_LIST(blsp1_uart1_apps_clk_src),
3872 CLK_LIST(blsp1_uart2_apps_clk_src),
3873 CLK_LIST(blsp2_qup1_i2c_apps_clk_src),
3874 CLK_LIST(blsp2_qup1_spi_apps_clk_src),
3875 CLK_LIST(blsp2_qup2_i2c_apps_clk_src),
3876 CLK_LIST(blsp2_qup2_spi_apps_clk_src),
3877 CLK_LIST(blsp2_qup3_i2c_apps_clk_src),
3878 CLK_LIST(blsp2_qup3_spi_apps_clk_src),
3879 CLK_LIST(blsp2_uart1_apps_clk_src),
3880 CLK_LIST(blsp2_uart2_apps_clk_src),
3881 CLK_LIST(cci_clk_src),
3882 CLK_LIST(cpp_clk_src),
3883 CLK_LIST(camss_gp0_clk_src),
3884 CLK_LIST(camss_gp1_clk_src),
3885 CLK_LIST(jpeg0_clk_src),
3886 CLK_LIST(mclk0_clk_src),
3887 CLK_LIST(mclk1_clk_src),
3888 CLK_LIST(mclk2_clk_src),
3889 CLK_LIST(csi0phytimer_clk_src),
3890 CLK_LIST(csi1phytimer_clk_src),
3891 CLK_LIST(crypto_clk_src),
3892 CLK_LIST(gp1_clk_src),
3893 CLK_LIST(gp2_clk_src),
3894 CLK_LIST(gp3_clk_src),
3895 CLK_LIST(esc0_clk_src),
3896 CLK_LIST(mdp_clk_src),
3897 CLK_LIST(vsync_clk_src),
3898 CLK_LIST(pdm2_clk_src),
3899 CLK_LIST(sdcc1_apps_clk_src),
3900 CLK_LIST(sdcc1_ice_core_clk_src),
3901 CLK_LIST(sdcc2_apps_clk_src),
3902 CLK_LIST(usb_hs_system_clk_src),
3903 CLK_LIST(gcc_bimc_gpu_clk),
3904 CLK_LIST(gcc_blsp1_qup2_i2c_apps_clk),
3905 CLK_LIST(gcc_blsp1_qup2_spi_apps_clk),
3906 CLK_LIST(gcc_blsp1_qup3_i2c_apps_clk),
3907 CLK_LIST(gcc_blsp1_qup3_spi_apps_clk),
3908 CLK_LIST(gcc_blsp1_qup4_i2c_apps_clk),
3909 CLK_LIST(gcc_blsp1_qup4_spi_apps_clk),
3910 CLK_LIST(gcc_blsp1_uart1_apps_clk),
3911 CLK_LIST(gcc_blsp1_uart2_apps_clk),
3912 CLK_LIST(gcc_blsp2_qup1_i2c_apps_clk),
3913 CLK_LIST(gcc_blsp2_qup1_spi_apps_clk),
3914 CLK_LIST(gcc_blsp2_qup2_i2c_apps_clk),
3915 CLK_LIST(gcc_blsp2_qup2_spi_apps_clk),
3916 CLK_LIST(gcc_blsp2_qup3_i2c_apps_clk),
3917 CLK_LIST(gcc_blsp2_qup3_spi_apps_clk),
3918 CLK_LIST(gcc_blsp2_uart1_apps_clk),
3919 CLK_LIST(gcc_blsp2_uart2_apps_clk),
3920 CLK_LIST(gcc_camss_cci_ahb_clk),
3921 CLK_LIST(gcc_camss_cci_clk),
3922 CLK_LIST(gcc_camss_cpp_ahb_clk),
3923 CLK_LIST(gcc_camss_cpp_axi_clk),
3924 CLK_LIST(gcc_camss_cpp_clk),
3925 CLK_LIST(gcc_camss_csi0_ahb_clk),
3926 CLK_LIST(gcc_camss_csi0_clk),
3927 CLK_LIST(gcc_camss_csi0phy_clk),
3928 CLK_LIST(gcc_camss_csi0pix_clk),
3929 CLK_LIST(gcc_camss_csi0rdi_clk),
3930 CLK_LIST(gcc_camss_csi1_ahb_clk),
3931 CLK_LIST(gcc_camss_csi1_clk),
3932 CLK_LIST(gcc_camss_csi1phy_clk),
3933 CLK_LIST(gcc_camss_csi1pix_clk),
3934 CLK_LIST(gcc_camss_csi1rdi_clk),
3935 CLK_LIST(gcc_camss_csi2_ahb_clk),
3936 CLK_LIST(gcc_camss_csi2_clk),
3937 CLK_LIST(gcc_camss_csi2phy_clk),
3938 CLK_LIST(gcc_camss_csi2pix_clk),
3939 CLK_LIST(gcc_camss_csi2rdi_clk),
3940 CLK_LIST(gcc_camss_csi_vfe0_clk),
3941 CLK_LIST(gcc_camss_csi_vfe1_clk),
3942 CLK_LIST(gcc_camss_gp0_clk),
3943 CLK_LIST(gcc_camss_gp1_clk),
3944 CLK_LIST(gcc_camss_ispif_ahb_clk),
3945 CLK_LIST(gcc_camss_jpeg0_clk),
3946 CLK_LIST(gcc_camss_jpeg_ahb_clk),
3947 CLK_LIST(gcc_camss_jpeg_axi_clk),
3948 CLK_LIST(gcc_camss_mclk0_clk),
3949 CLK_LIST(gcc_camss_mclk1_clk),
3950 CLK_LIST(gcc_camss_mclk2_clk),
3951 CLK_LIST(gcc_camss_micro_ahb_clk),
3952 CLK_LIST(gcc_camss_csi0phytimer_clk),
3953 CLK_LIST(gcc_camss_csi1phytimer_clk),
3954 CLK_LIST(gcc_camss_ahb_clk),
3955 CLK_LIST(gcc_camss_top_ahb_clk),
3956 CLK_LIST(gcc_camss_vfe0_clk),
3957 CLK_LIST(gcc_camss_vfe_ahb_clk),
3958 CLK_LIST(gcc_camss_vfe_axi_clk),
3959 CLK_LIST(gcc_camss_vfe1_ahb_clk),
3960 CLK_LIST(gcc_camss_vfe1_axi_clk),
3961 CLK_LIST(gcc_camss_vfe1_clk),
3962 CLK_LIST(gcc_gp1_clk),
3963 CLK_LIST(gcc_gp2_clk),
3964 CLK_LIST(gcc_gp3_clk),
3965 CLK_LIST(gcc_mdss_ahb_clk),
3966 CLK_LIST(gcc_mdss_axi_clk),
3967 CLK_LIST(gcc_mdss_esc0_clk),
3968 CLK_LIST(gcc_mdss_mdp_clk),
3969 CLK_LIST(gcc_mdss_vsync_clk),
3970 CLK_LIST(gcc_mss_cfg_ahb_clk),
3971 CLK_LIST(gcc_mss_q6_bimc_axi_clk),
3972 CLK_LIST(gcc_bimc_gfx_clk),
3973 CLK_LIST(gcc_oxili_ahb_clk),
3974 CLK_LIST(gcc_oxili_gfx3d_clk),
3975 CLK_LIST(gcc_pdm2_clk),
3976 CLK_LIST(gcc_pdm_ahb_clk),
3977 CLK_LIST(gcc_sdcc1_ahb_clk),
3978 CLK_LIST(gcc_sdcc1_apps_clk),
3979 CLK_LIST(gcc_sdcc1_ice_core_clk),
3980 CLK_LIST(gcc_sdcc2_ahb_clk),
3981 CLK_LIST(gcc_sdcc2_apps_clk),
3982 CLK_LIST(gcc_usb2a_phy_sleep_clk),
3983 CLK_LIST(gcc_usb_hs_phy_cfg_ahb_clk),
3984 CLK_LIST(gcc_usb_hs_ahb_clk),
3985 CLK_LIST(gcc_usb_hs_system_clk),
3986 CLK_LIST(gcc_venus0_ahb_clk),
3987 CLK_LIST(gcc_venus0_axi_clk),
3988 CLK_LIST(gcc_venus0_core0_vcodec0_clk),
3989 CLK_LIST(gcc_venus0_vcodec0_clk),
3990
3991 /* Reset clks */
3992 CLK_LIST(gcc_usb2_hs_phy_only_clk),
3993 CLK_LIST(gcc_qusb2_phy_clk),
3994
3995 /* WCNSS Debug */
3996 CLK_LIST(wcnss_m_clk),
3997};
3998
3999static struct clk_lookup msm_clocks_lookup_8952[] = {
4000 CLK_LIST(a53ss_c0_pll),
4001 CLK_LIST(a53ss_cci_pll),
4002 CLK_LIST(ipa_clk),
4003 CLK_LIST(ipa_a_clk),
4004 CLK_LIST(gpll0_clk_src_8952),
4005 CLK_LIST(gpll0_ao_clk_src_8952),
4006 CLK_LIST(gcc_oxili_gmem_clk),
4007 CLK_LIST(usb_fs_ic_clk_src),
4008 CLK_LIST(gcc_usb_fs_ic_clk),
4009 CLK_LIST(usb_fs_system_clk_src),
4010 CLK_LIST(gcc_usb_fs_system_clk),
4011 CLK_LIST(gcc_gfx_tcu_clk),
4012 CLK_LIST(gcc_gfx_tbu_clk),
4013 CLK_LIST(gcc_gtcu_ahb_clk),
4014 CLK_LIST(gcc_ipa_tbu_clk),
4015 CLK_LIST(gcc_usb_fs_ahb_clk),
4016 CLK_LIST(gcc_venus0_core1_vcodec0_clk),
4017 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4018 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4019 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4020 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4021 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4022 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4023 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4024 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4025 CLK_LIST(gcc_oxili_timer_clk),
4026};
4027
4028static struct clk_lookup msm_clocks_lookup_8937[] = {
4029 CLK_LIST(gpll0_clk_src_8937),
4030 CLK_LIST(gpll0_ao_clk_src_8937),
4031 CLK_LIST(gpll0_sleep_clk_src),
4032 CLK_LIST(a53ss_c0_pll),
4033 CLK_LIST(esc1_clk_src),
4034 CLK_LIST(gcc_mdss_esc1_clk),
4035 CLK_LIST(gcc_dcc_clk),
4036 CLK_LIST(gcc_oxili_aon_clk),
4037 CLK_LIST(gcc_qdss_dap_clk),
4038 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4039 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4040 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4041 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4042 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4043 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4044 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4045 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4046 CLK_LIST(gcc_oxili_timer_clk),
4047};
4048
4049static struct clk_lookup msm_clocks_lookup_8917[] = {
4050 CLK_LIST(gpll0_clk_src_8937),
4051 CLK_LIST(gpll0_ao_clk_src_8937),
4052 CLK_LIST(gpll0_sleep_clk_src),
4053 CLK_LIST(bimc_gpu_clk),
4054 CLK_LIST(bimc_gpu_a_clk),
4055 CLK_LIST(gcc_dcc_clk),
4056 CLK_LIST(gcc_qdss_dap_clk),
4057 CLK_LIST(gcc_gfx_tcu_clk),
4058 CLK_LIST(gcc_gfx_tbu_clk),
4059 CLK_LIST(gcc_gtcu_ahb_clk),
4060};
4061
4062static struct clk_lookup msm_clocks_lookup_8920[] = {
4063 CLK_LIST(gpll0_clk_src_8937),
4064 CLK_LIST(gpll0_ao_clk_src_8937),
4065 CLK_LIST(gpll0_sleep_clk_src),
4066 CLK_LIST(bimc_gpu_clk),
4067 CLK_LIST(bimc_gpu_a_clk),
4068 CLK_LIST(gcc_dcc_clk),
4069 CLK_LIST(gcc_qdss_dap_clk),
4070 CLK_LIST(gcc_gfx_tcu_clk),
4071 CLK_LIST(gcc_gfx_tbu_clk),
4072 CLK_LIST(gcc_gtcu_ahb_clk),
4073 CLK_LIST(ipa_clk),
4074 CLK_LIST(ipa_a_clk),
4075 CLK_LIST(gcc_ipa_tbu_clk),
4076};
4077
4078static struct clk_lookup msm_clocks_lookup_8940[] = {
4079 CLK_LIST(gpll0_clk_src_8937),
4080 CLK_LIST(gpll0_ao_clk_src_8937),
4081 CLK_LIST(gpll0_sleep_clk_src),
4082 CLK_LIST(a53ss_c0_pll),
4083 CLK_LIST(esc1_clk_src),
4084 CLK_LIST(gcc_mdss_esc1_clk),
4085 CLK_LIST(gcc_dcc_clk),
4086 CLK_LIST(gcc_oxili_aon_clk),
4087 CLK_LIST(gcc_qdss_dap_clk),
4088 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4089 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4090 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4091 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4092 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4093 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4094 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4095 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4096 CLK_LIST(gcc_oxili_timer_clk),
4097 CLK_LIST(ipa_clk),
4098 CLK_LIST(ipa_a_clk),
4099 CLK_LIST(gcc_ipa_tbu_clk),
4100};
4101
4102/* Please note that the order of reg-names is important */
4103static int get_mmio_addr(struct platform_device *pdev, u32 nbases)
4104{
4105 int i, count;
4106 const char *str;
4107 struct resource *res;
4108 struct device *dev = &pdev->dev;
4109
4110 count = of_property_count_strings(dev->of_node, "reg-names");
4111 if (count < nbases) {
4112 dev_err(dev, "missing reg-names property, expected %d strings\n",
4113 nbases);
4114 return -EINVAL;
4115 }
4116
4117 for (i = 0; i < nbases; i++) {
4118 of_property_read_string_index(dev->of_node, "reg-names", i,
4119 &str);
4120 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, str);
4121 if (!res) {
4122 dev_err(dev, "Unable to retrieve register base.\n");
4123 return -ENOMEM;
4124 }
4125
4126 virt_bases[i] = devm_ioremap(dev, res->start,
4127 resource_size(res));
4128 if (!virt_bases[i]) {
4129 dev_err(dev, "Failed to map in CC registers.\n");
4130 return -ENOMEM;
4131 }
4132 }
4133
4134 return 0;
4135}
4136
4137static const struct msm_reset_map gcc_8952_resets[] = {
4138 [GCC_CAMSS_MICRO_BCR] = {0x56008},
4139 [GCC_USB_FS_BCR] = {0x3F000},
4140 [GCC_USB_HS_BCR] = {0x41000},
4141 [GCC_USB2_HS_PHY_ONLY_BCR] = {0x41034},
4142 [GCC_QUSB2_PHY_BCR] = {0x4103C},
4143};
4144
4145static void override_for_8917(int speed_bin)
4146{
4147 gpll3_clk_src.c.rate = 930000000;
4148
4149 OVERRIDE_FMAX3(csi0,
4150 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4151 /* Frequency Table same as 8937 */
4152 OVERRIDE_FTABLE(csi0, ftbl_gcc_camss_csi0_2_clk, 8937);
4153 OVERRIDE_FMAX3(csi1,
4154 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4155 /* Frequency Table same as 8937 */
4156 OVERRIDE_FTABLE(csi1, ftbl_gcc_camss_csi0_2_clk, 8937);
4157 OVERRIDE_FMAX3(csi2,
4158 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4159 /* Frequency Table same as 8937 */
4160 OVERRIDE_FTABLE(csi2, ftbl_gcc_camss_csi0_2_clk, 8937);
4161
4162 OVERRIDE_FMAX5(vfe0,
4163 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4164 NOM_PLUS, 329140000, HIGH, 360000000);
4165 OVERRIDE_FTABLE(vfe0, ftbl_gcc_camss_vfe0_1_clk, 8917);
4166 OVERRIDE_FMAX5(vfe1,
4167 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4168 NOM_PLUS, 329140000, HIGH, 360000000);
4169 OVERRIDE_FTABLE(vfe1, ftbl_gcc_camss_vfe0_1_clk, 8917);
4170 OVERRIDE_FTABLE(vcodec0, ftbl_gcc_venus0_vcodec0_clk, 8917);
4171 OVERRIDE_FMAX5(vcodec0,
4172 LOWER, 200000000, LOW, 270000000, NOMINAL, 308570000,
4173 NOM_PLUS, 329140000, HIGH, 360000000);
4174 OVERRIDE_FMAX4(cpp,
4175 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4176 NOM_PLUS, 360000000);
4177 OVERRIDE_FTABLE(cpp, ftbl_gcc_camss_cpp_clk, 8917);
4178 OVERRIDE_FMAX5(jpeg0,
4179 LOWER, 133330000, LOW, 200000000, NOMINAL, 266670000,
4180 NOM_PLUS, 308570000, HIGH, 320000000);
4181 /* Frequency Table same as 8937 */
4182 OVERRIDE_FTABLE(jpeg0, ftbl_gcc_camss_jpeg0_clk, 8937);
4183
4184 if (speed_bin) {
4185 OVERRIDE_FMAX5(gfx3d,
4186 LOWER, 270000000, LOW, 400000000, NOMINAL, 484800000,
4187 NOM_PLUS, 523200000, HIGH, 650000000);
4188 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8917_650MHz);
4189 } else {
4190 OVERRIDE_FMAX5(gfx3d,
4191 LOWER, 270000000, LOW, 400000000, NOMINAL, 484800000,
4192 NOM_PLUS, 523200000, HIGH, 598000000);
4193 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8917);
4194 }
4195
4196 OVERRIDE_FMAX1(cci, LOWER, 37500000);
4197
4198 OVERRIDE_FTABLE(csi0phytimer, ftbl_gcc_camss_csi0_1phytimer_clk, 8917);
4199 OVERRIDE_FMAX3(csi0phytimer, LOWER, 100000000, LOW, 200000000,
4200 NOMINAL, 266670000);
4201 OVERRIDE_FTABLE(csi1phytimer, ftbl_gcc_camss_csi0_1phytimer_clk, 8917);
4202 OVERRIDE_FMAX3(csi1phytimer, LOWER, 100000000, LOW, 200000000,
4203 NOMINAL, 266670000);
4204 OVERRIDE_FMAX2(gp1, LOWER, 100000000, NOMINAL, 200000000);
4205 OVERRIDE_FMAX2(gp2, LOWER, 100000000, NOMINAL, 200000000);
4206 OVERRIDE_FMAX2(gp3, LOWER, 100000000, NOMINAL, 200000000);
4207
4208 OVERRIDE_FMAX2(byte0, LOWER, 125000000, NOMINAL, 187500000);
4209 /* Frequency Table same as 8937 */
4210 OVERRIDE_FTABLE(byte0, ftbl_gcc_mdss_byte0_clk, 8937);
4211 byte0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4212
4213 OVERRIDE_FMAX2(pclk0, LOWER, 166670000, NOMINAL, 250000000);
4214 /* Frequency Table same as 8937 */
4215 OVERRIDE_FTABLE(pclk0, ftbl_gcc_mdss_pclk0_clk, 8937);
4216 pclk0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4217
4218 OVERRIDE_FMAX2(sdcc1_apps, LOWER, 200000000, NOMINAL, 400000000);
4219 OVERRIDE_FTABLE(usb_hs_system, ftbl_gcc_usb_hs_system_clk, 8917);
4220 OVERRIDE_FMAX3(usb_hs_system, LOWER, 800000000, NOMINAL, 133333000,
4221 HIGH, 177780000);
4222}
4223
4224static void override_for_8937(int speed_bin)
4225{
4226 gpll3_clk_src.c.rate = 900000000;
4227 gpll3_clk_src.vco_tbl = p_vco_8937;
4228 gpll3_clk_src.num_vco = ARRAY_SIZE(p_vco_8937);
4229 OVERRIDE_FMAX2(gpll3, LOW, 800000000, NOMINAL, 1066000000);
4230
4231 OVERRIDE_FMAX1(cci, LOWER, 37500000);
4232 OVERRIDE_FMAX3(csi0,
4233 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4234 OVERRIDE_FTABLE(csi0, ftbl_gcc_camss_csi0_2_clk, 8937);
4235 OVERRIDE_FMAX3(csi1,
4236 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4237 OVERRIDE_FTABLE(csi1, ftbl_gcc_camss_csi0_2_clk, 8937);
4238 OVERRIDE_FMAX3(csi2,
4239 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4240 OVERRIDE_FTABLE(csi2, ftbl_gcc_camss_csi0_2_clk, 8937);
4241 OVERRIDE_FMAX4(vfe0,
4242 LOWER, 160000000, LOW, 308570000, NOMINAL, 400000000,
4243 NOM_PLUS, 432000000);
4244 OVERRIDE_FTABLE(vfe0, ftbl_gcc_camss_vfe0_1_clk, 8937);
4245 OVERRIDE_FMAX4(vfe1,
4246 LOWER, 160000000, LOW, 308570000, NOMINAL, 400000000,
4247 NOM_PLUS, 432000000);
4248 OVERRIDE_FTABLE(vfe1, ftbl_gcc_camss_vfe0_1_clk, 8937);
4249
4250 if (speed_bin) {
4251 OVERRIDE_FMAX6(gfx3d,
4252 LOWER, 216000000, LOW, 300000000,
4253 NOMINAL, 375000000, NOM_PLUS, 400000000,
4254 HIGH, 450000000, SUPER_TUR, 475000000);
4255 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8937_475MHz);
4256 } else {
4257 OVERRIDE_FMAX5(gfx3d,
4258 LOWER, 216000000, LOW, 300000000,
4259 NOMINAL, 375000000, NOM_PLUS, 400000000,
4260 HIGH, 450000000);
4261 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8937);
4262 }
4263
4264 OVERRIDE_FMAX5(cpp,
4265 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4266 NOM_PLUS, 342860000, HIGH, 360000000);
4267 OVERRIDE_FTABLE(cpp, ftbl_gcc_camss_cpp_clk, 8937);
4268 OVERRIDE_FMAX5(jpeg0,
4269 LOWER, 133330000, LOW, 200000000, NOMINAL, 266670000,
4270 NOM_PLUS, 308570000, HIGH, 320000000);
4271 OVERRIDE_FTABLE(jpeg0, ftbl_gcc_camss_jpeg0_clk, 8937);
4272 OVERRIDE_FMAX2(csi0phytimer, LOWER, 100000000, LOW, 200000000);
4273 OVERRIDE_FMAX2(csi1phytimer, LOWER, 100000000, LOW, 200000000);
4274 OVERRIDE_FMAX2(gp1, LOWER, 100000000, NOMINAL, 200000000);
4275 OVERRIDE_FMAX2(gp2, LOWER, 100000000, NOMINAL, 200000000);
4276 OVERRIDE_FMAX2(gp3, LOWER, 100000000, NOMINAL, 200000000);
4277 OVERRIDE_FMAX2(byte0, LOWER, 125000000, NOMINAL, 187500000);
4278 OVERRIDE_FTABLE(byte0, ftbl_gcc_mdss_byte0_clk, 8937);
4279 OVERRIDE_FMAX2(byte1, LOWER, 125000000, NOMINAL, 187500000);
4280 byte0_clk_src.current_freq = ftbl_gcc_mdss_byte0_clk_8937;
4281 OVERRIDE_FMAX2(pclk0, LOWER, 166670000, NOMINAL, 250000000);
4282 OVERRIDE_FTABLE(pclk0, ftbl_gcc_mdss_pclk0_clk, 8937);
4283 OVERRIDE_FMAX2(pclk1, LOWER, 166670000, NOMINAL, 250000000);
4284 pclk0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4285 OVERRIDE_FTABLE(vcodec0, ftbl_gcc_venus0_vcodec0_clk, 8937);
4286 OVERRIDE_FMAX5(vcodec0,
4287 LOWER, 166150000, LOW, 240000000, NOMINAL, 308570000,
4288 NOM_PLUS, 320000000, HIGH, 360000000);
4289 OVERRIDE_FMAX2(sdcc1_apps, LOWER, 100000000,
4290 NOMINAL, 400000000);
4291}
4292
4293static void get_speed_bin(struct platform_device *pdev, int *bin)
4294{
4295 struct resource *res;
4296 void __iomem *base;
4297 u32 config_efuse;
4298
4299 *bin = 0;
4300
4301 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "efuse");
4302 if (!res) {
4303 dev_info(&pdev->dev,
4304 "No GPU speed binning available. Defaulting to 0.\n");
4305 return;
4306 }
4307
4308 base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
4309 if (!base) {
4310 dev_warn(&pdev->dev,
4311 "Unable to ioremap efuse reg address. Defaulting to 0.\n");
4312 return;
4313 }
4314
4315 config_efuse = readl_relaxed(base);
4316 devm_iounmap(&pdev->dev, base);
4317 *bin = (config_efuse >> 31) & 0x1;
4318
4319 dev_info(&pdev->dev, "GPU speed bin: %d\n", *bin);
4320}
4321
4322static int msm_gcc_probe(struct platform_device *pdev)
4323{
4324 struct resource *res;
4325 int ret;
4326 int speed_bin;
4327 u32 regval, nbases = N_BASES;
4328 bool compat_bin = false;
4329 bool compat_bin2 = false;
4330 bool compat_bin3 = false;
4331 bool compat_bin4 = false;
4332
4333 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4334 "qcom,gcc-8937");
4335
4336 compat_bin2 = of_device_is_compatible(pdev->dev.of_node,
4337 "qcom,gcc-8917");
4338
4339 compat_bin3 = of_device_is_compatible(pdev->dev.of_node,
4340 "qcom,gcc-8940");
4341
4342 compat_bin4 = of_device_is_compatible(pdev->dev.of_node,
4343 "qcom,gcc-8920");
4344
4345 ret = vote_bimc(&bimc_clk, INT_MAX);
4346 if (ret < 0)
4347 return ret;
4348
4349 if (compat_bin2 || compat_bin4)
4350 nbases = APCS_C0_PLL_BASE;
4351
4352 ret = get_mmio_addr(pdev, nbases);
4353 if (ret)
4354 return ret;
4355
4356 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");
4357 if (!res) {
4358 dev_err(&pdev->dev, "Register base not defined\n");
4359 return -ENOMEM;
4360 }
4361
4362 virt_bases[GCC_BASE] = devm_ioremap(&pdev->dev, res->start,
4363 resource_size(res));
4364 if (!virt_bases[GCC_BASE]) {
4365 dev_err(&pdev->dev, "Failed to ioremap CC registers\n");
4366 return -ENOMEM;
4367 }
4368
4369 vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig");
4370 if (IS_ERR(vdd_dig.regulator[0])) {
4371 if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER))
4372 dev_err(&pdev->dev,
4373 "Unable to get vdd_dig regulator!!!\n");
4374 return PTR_ERR(vdd_dig.regulator[0]);
4375 }
4376
4377 if (!compat_bin2 && !compat_bin4) {
4378 vdd_sr2_pll.regulator[0] = devm_regulator_get(&pdev->dev,
4379 "vdd_sr2_pll");
4380 if (IS_ERR(vdd_sr2_pll.regulator[0])) {
4381 if (PTR_ERR(vdd_sr2_pll.regulator[0]) != -EPROBE_DEFER)
4382 dev_err(&pdev->dev,
4383 "Unable to get vdd_sr2_pll regulator!!!\n");
4384 return PTR_ERR(vdd_sr2_pll.regulator[0]);
4385 }
4386
4387 vdd_sr2_pll.regulator[1] = devm_regulator_get(&pdev->dev,
4388 "vdd_sr2_dig");
4389 if (IS_ERR(vdd_sr2_pll.regulator[1])) {
4390 if (PTR_ERR(vdd_sr2_pll.regulator[1]) != -EPROBE_DEFER)
4391 dev_err(&pdev->dev,
4392 "Unable to get vdd_sr2_dig regulator!!!\n");
4393 return PTR_ERR(vdd_sr2_pll.regulator[1]);
4394 }
4395 }
4396
4397 vdd_hf_pll.regulator[0] = devm_regulator_get(&pdev->dev,
4398 "vdd_hf_pll");
4399 if (IS_ERR(vdd_hf_pll.regulator[0])) {
4400 if (PTR_ERR(vdd_hf_pll.regulator[0]) != -EPROBE_DEFER)
4401 dev_err(&pdev->dev,
4402 "Unable to get vdd_sr2_pll regulator!!!\n");
4403 return PTR_ERR(vdd_hf_pll.regulator[0]);
4404 }
4405
4406 vdd_hf_pll.regulator[1] = devm_regulator_get(&pdev->dev,
4407 "vdd_hf_dig");
4408 if (IS_ERR(vdd_hf_pll.regulator[1])) {
4409 if (PTR_ERR(vdd_hf_pll.regulator[1]) != -EPROBE_DEFER)
4410 dev_err(&pdev->dev,
4411 "Unable to get vdd_hf_dig regulator!!!\n");
4412 return PTR_ERR(vdd_hf_pll.regulator[1]);
4413 }
4414
4415 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
4416 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
4417 regval |= BIT(0);
4418 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
4419
4420 if (compat_bin || compat_bin3) {
4421 gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;
4422 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;
4423 /* Oxili Ocmem in GX rail: OXILI_GMEM_CLAMP_IO */
4424 regval = readl_relaxed(GCC_REG_BASE(GX_DOMAIN_MISC));
4425 regval &= ~BIT(0);
4426 writel_relaxed(regval, GCC_REG_BASE(GX_DOMAIN_MISC));
4427 get_speed_bin(pdev, &speed_bin);
4428 override_for_8937(speed_bin);
4429
4430 if (compat_bin3) {
4431 if (speed_bin) {
4432 gfx3d_clk_src.freq_tbl =
4433 ftbl_gcc_oxili_gfx3d_clk_8940_500MHz;
4434 gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] =
4435 500000000;
4436 } else {
4437 gfx3d_clk_src.freq_tbl =
4438 ftbl_gcc_oxili_gfx3d_clk_8937_475MHz;
4439 gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] =
4440 475000000;
4441 }
4442 }
4443 } else if (compat_bin2 || compat_bin4) {
4444 gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;
4445 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;
4446 vdd_dig.num_levels = VDD_DIG_NUM_8917;
4447 vdd_dig.cur_level = VDD_DIG_NUM_8917;
4448 vdd_hf_pll.num_levels = VDD_HF_PLL_NUM_8917;
4449 vdd_hf_pll.cur_level = VDD_HF_PLL_NUM_8917;
4450 get_speed_bin(pdev, &speed_bin);
4451 override_for_8917(speed_bin);
4452
4453 if (compat_bin2) {
4454 blsp1_qup2_spi_apps_clk_src.freq_tbl =
4455 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4456 blsp1_qup3_spi_apps_clk_src.freq_tbl =
4457 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4458 blsp1_qup4_spi_apps_clk_src.freq_tbl =
4459 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4460 blsp2_qup1_spi_apps_clk_src.freq_tbl =
4461 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4462 blsp2_qup2_spi_apps_clk_src.freq_tbl =
4463 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4464 blsp2_qup3_spi_apps_clk_src.freq_tbl =
4465 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4466 }
4467 } else {
4468 gpll0_clk_src.c.parent = &gpll0_clk_src_8952.c;
4469 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8952.c;
4470 }
4471
4472 ret = of_msm_clock_register(pdev->dev.of_node,
4473 msm_clocks_lookup_common,
4474 ARRAY_SIZE(msm_clocks_lookup_common));
4475 if (ret)
4476 return ret;
4477
4478 if (compat_bin)
4479 ret = of_msm_clock_register(pdev->dev.of_node,
4480 msm_clocks_lookup_8937,
4481 ARRAY_SIZE(msm_clocks_lookup_8937));
4482 else if (compat_bin2)
4483 ret = of_msm_clock_register(pdev->dev.of_node,
4484 msm_clocks_lookup_8917,
4485 ARRAY_SIZE(msm_clocks_lookup_8917));
4486 else if (compat_bin3)
4487 ret = of_msm_clock_register(pdev->dev.of_node,
4488 msm_clocks_lookup_8940,
4489 ARRAY_SIZE(msm_clocks_lookup_8940));
4490 else if (compat_bin4)
4491 ret = of_msm_clock_register(pdev->dev.of_node,
4492 msm_clocks_lookup_8920,
4493 ARRAY_SIZE(msm_clocks_lookup_8920));
4494 else
4495 ret = of_msm_clock_register(pdev->dev.of_node,
4496 msm_clocks_lookup_8952,
4497 ARRAY_SIZE(msm_clocks_lookup_8952));
4498 if (ret)
4499 return ret;
4500
4501 ret = enable_rpm_scaling();
4502 if (ret)
4503 return ret;
4504
4505 clk_set_rate(&apss_ahb_clk_src.c, 19200000);
4506 clk_prepare_enable(&apss_ahb_clk_src.c);
4507
4508 /*
4509 * Hold an active set vote for PCNOC AHB source. Sleep set vote is 0.
4510 */
4511 clk_set_rate(&pnoc_keepalive_a_clk.c, 19200000);
4512 clk_prepare_enable(&pnoc_keepalive_a_clk.c);
4513
4514 clk_prepare_enable(&xo_a_clk_src.c);
4515 clk_prepare_enable(&gcc_blsp1_ahb_clk.c);
4516 clk_prepare_enable(&gcc_blsp2_ahb_clk.c);
4517 clk_prepare_enable(&gcc_blsp1_uart2_apps_clk.c);
4518 clk_prepare_enable(&gcc_blsp1_uart1_apps_clk.c);
4519 clk_prepare_enable(&gcc_bimc_gpu_clk.c);
4520 clk_prepare_enable(&sysmmnoc_msmbus_a_clk.c);
4521 clk_prepare_enable(&sysmmnoc_a_clk.c);
4522
4523 if (!compat_bin && !compat_bin3) {
4524 /* Configure Sleep and Wakeup cycles for GMEM clock */
4525 regval = readl_relaxed(GCC_REG_BASE(OXILI_GMEM_CBCR));
4526 regval ^= 0xFF0;
4527 regval |= CLKFLAG_WAKEUP_CYCLES << 8;
4528 regval |= CLKFLAG_SLEEP_CYCLES << 4;
4529 writel_relaxed(regval, GCC_REG_BASE(OXILI_GMEM_CBCR));
4530 } else {
4531 /* Configure Sleep and Wakeup cycles for OXILI clock */
4532 regval = readl_relaxed(GCC_REG_BASE(OXILI_GFX3D_CBCR));
4533 regval &= ~0xF0;
4534 regval |= CLKFLAG_SLEEP_CYCLES << 4;
4535 writel_relaxed(regval, GCC_REG_BASE(OXILI_GFX3D_CBCR));
4536 }
4537
4538 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
4539 if (ret)
4540 return ret;
4541
4542 msm_reset_controller_register(pdev, gcc_8952_resets,
4543 ARRAY_SIZE(gcc_8952_resets), virt_bases[GCC_BASE]);
4544
4545 dev_info(&pdev->dev, "Registered GCC clocks\n");
4546
4547 return 0;
4548}
4549
4550static const struct of_device_id msm_clock_gcc_match_table[] = {
4551 { .compatible = "qcom,gcc-8952" },
4552 { .compatible = "qcom,gcc-8937" },
4553 { .compatible = "qcom,gcc-8917" },
4554 { .compatible = "qcom,gcc-8940" },
4555 { .compatible = "qcom,gcc-8920" },
4556 {}
4557};
4558
4559static struct platform_driver msm_clock_gcc_driver = {
4560 .probe = msm_gcc_probe,
4561 .driver = {
4562 .name = "qcom,gcc-8952",
4563 .of_match_table = msm_clock_gcc_match_table,
4564 .owner = THIS_MODULE,
4565 },
4566};
4567
4568static int msm_gcc_spm_probe(struct platform_device *pdev)
4569{
4570 struct resource *res = NULL;
4571 bool compat_bin = false;
4572
4573 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4574 "qcom,spm-8952");
4575
4576 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c0_base");
4577 if (!res) {
4578 dev_err(&pdev->dev, "SPM register base not defined for c0\n");
4579 return -ENOMEM;
4580 }
4581
4582 a53ss_c0_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
4583 resource_size(res));
4584 if (!a53ss_c0_pll.spm_ctrl.spm_base) {
4585 dev_err(&pdev->dev, "Failed to ioremap c0 spm registers\n");
4586 return -ENOMEM;
4587 }
4588
4589 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c1_base");
4590 if (!res) {
4591 dev_err(&pdev->dev, "SPM register base not defined for c1\n");
4592 return -ENOMEM;
4593 }
4594
4595 a53ss_c1_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
4596 resource_size(res));
4597 if (!a53ss_c1_pll.spm_ctrl.spm_base) {
4598 dev_err(&pdev->dev, "Failed to ioremap c1 spm registers\n");
4599 return -ENOMEM;
4600 }
4601
4602 if (compat_bin) {
4603 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
4604 "spm_cci_base");
4605 if (!res) {
4606 dev_err(&pdev->dev, "SPM register base not defined for cci\n");
4607 return -ENOMEM;
4608 }
4609
4610 a53ss_cci_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev,
4611 res->start, resource_size(res));
4612 if (!a53ss_cci_pll.spm_ctrl.spm_base) {
4613 dev_err(&pdev->dev, "Failed to ioremap cci spm registers\n");
4614 return -ENOMEM;
4615 }
4616 }
4617
4618 dev_info(&pdev->dev, "Registered GCC SPM clocks\n");
4619
4620 return 0;
4621}
4622
4623static const struct of_device_id msm_clock_spm_match_table[] = {
4624 { .compatible = "qcom,gcc-spm-8952" },
4625 { .compatible = "qcom,gcc-spm-8937" },
4626 {}
4627};
4628
4629static struct platform_driver msm_clock_spm_driver = {
4630 .probe = msm_gcc_spm_probe,
4631 .driver = {
4632 .name = "qcom,gcc-spm-8952",
4633 .of_match_table = msm_clock_spm_match_table,
4634 .owner = THIS_MODULE,
4635 },
4636};
4637
4638static int __init msm_gcc_init(void)
4639{
4640 int ret;
4641
4642 ret = platform_driver_register(&msm_clock_gcc_driver);
4643 if (!ret)
4644 ret = platform_driver_register(&msm_clock_spm_driver);
4645
4646 return ret;
4647}
4648
4649static struct clk_lookup msm_clocks_measure[] = {
4650 CLK_LOOKUP_OF("measure", gcc_debug_mux, "debug"),
4651 CLK_LIST(apss_debug_pri_mux),
4652 CLK_LIST(apc0_m_clk),
4653 CLK_LIST(apc1_m_clk),
4654 CLK_LIST(cci_m_clk),
4655};
4656
4657static struct clk_lookup msm_clocks_measure_8937[] = {
4658 CLK_LOOKUP_OF("measure", gcc_debug_mux_8937, "debug"),
4659 CLK_LIST(apss_debug_pri_mux),
4660 CLK_LIST(apc0_m_clk),
4661 CLK_LIST(apc1_m_clk),
4662 CLK_LIST(cci_m_clk),
4663};
4664
4665static int msm_clock_debug_probe(struct platform_device *pdev)
4666{
4667 int ret;
4668 struct resource *res;
4669 bool compat_bin = false, compat_bin2 = false;
4670 bool compat_bin3 = false;
4671 bool compat_bin4 = false;
4672
4673 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4674 "qcom,cc-debug-8937");
4675
4676 compat_bin2 = of_device_is_compatible(pdev->dev.of_node,
4677 "qcom,cc-debug-8917");
4678
4679 compat_bin3 = of_device_is_compatible(pdev->dev.of_node,
4680 "qcom,cc-debug-8940");
4681
4682 compat_bin4 = of_device_is_compatible(pdev->dev.of_node,
4683 "qcom,cc-debug-8920");
4684
4685 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "meas");
4686 if (!res) {
4687 dev_err(&pdev->dev, "GLB clock diag base not defined.\n");
4688 return -EINVAL;
4689 }
4690
4691 meas_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
4692 if (!meas_base) {
4693 dev_err(&pdev->dev, "Unable to map GLB clock diag base.\n");
4694 return -ENOMEM;
4695 }
4696
4697 clk_ops_debug_mux = clk_ops_gen_mux;
4698 clk_ops_debug_mux.get_rate = measure_get_rate;
4699
4700 if (compat_bin2)
4701 gcc_debug_mux_8937.post_div = 0x3;
4702
4703 if (!compat_bin && !compat_bin2 && !compat_bin3 && !compat_bin4)
4704 ret = of_msm_clock_register(pdev->dev.of_node,
4705 msm_clocks_measure, ARRAY_SIZE(msm_clocks_measure));
4706 else
4707 ret = of_msm_clock_register(pdev->dev.of_node,
4708 msm_clocks_measure_8937,
4709 ARRAY_SIZE(msm_clocks_measure_8937));
4710 if (ret) {
4711 dev_err(&pdev->dev, "Failed to register debug Mux\n");
4712 return ret;
4713 }
4714
4715 dev_info(&pdev->dev, "Registered Debug Mux successfully\n");
4716 return ret;
4717}
4718
4719static const struct of_device_id msm_clock_debug_match_table[] = {
4720 { .compatible = "qcom,cc-debug-8952" },
4721 { .compatible = "qcom,cc-debug-8937" },
4722 { .compatible = "qcom,cc-debug-8917" },
4723 { .compatible = "qcom,cc-debug-8940" },
4724 { .compatible = "qcom,cc-debug-8920" },
4725 {}
4726};
4727
4728static struct platform_driver msm_clock_debug_driver = {
4729 .probe = msm_clock_debug_probe,
4730 .driver = {
4731 .name = "qcom,cc-debug-8952",
4732 .of_match_table = msm_clock_debug_match_table,
4733 .owner = THIS_MODULE,
4734 },
4735};
4736
4737static int __init msm_clock_debug_init(void)
4738{
4739 return platform_driver_register(&msm_clock_debug_driver);
4740}
4741
4742/* MDSS DSI_PHY_PLL */
4743static struct clk_lookup msm_clocks_gcc_mdss_common[] = {
4744 CLK_LIST(ext_pclk0_clk_src),
4745 CLK_LIST(ext_byte0_clk_src),
4746 CLK_LIST(byte0_clk_src),
4747 CLK_LIST(pclk0_clk_src),
4748 CLK_LIST(gcc_mdss_pclk0_clk),
4749 CLK_LIST(gcc_mdss_byte0_clk),
4750 CLK_LIST(mdss_mdp_vote_clk),
4751 CLK_LIST(mdss_rotator_vote_clk),
4752};
4753
4754static struct clk_lookup msm_clocks_gcc_mdss_8937[] = {
4755 CLK_LIST(ext_pclk1_clk_src),
4756 CLK_LIST(ext_byte1_clk_src),
4757 CLK_LIST(byte1_clk_src),
4758 CLK_LIST(pclk1_clk_src),
4759 CLK_LIST(gcc_mdss_pclk1_clk),
4760 CLK_LIST(gcc_mdss_byte1_clk),
4761};
4762
4763static int msm_gcc_mdss_probe(struct platform_device *pdev)
4764{
4765 int ret = 0;
4766 struct clk *curr_p;
4767 bool compat_bin = false;
4768
4769 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4770 "qcom,gcc-mdss-8937");
4771 if (!compat_bin)
4772 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4773 "qcom,gcc-mdss-8940");
4774
4775 curr_p = ext_pclk0_clk_src.c.parent = devm_clk_get(&pdev->dev,
4776 "pclk0_src");
4777 if (IS_ERR(curr_p)) {
4778 dev_err(&pdev->dev, "Failed to get pclk0 source.\n");
4779 return PTR_ERR(curr_p);
4780 }
4781
4782 curr_p = ext_byte0_clk_src.c.parent = devm_clk_get(&pdev->dev,
4783 "byte0_src");
4784 if (IS_ERR(curr_p)) {
4785 dev_err(&pdev->dev, "Failed to get byte source.\n");
4786 ret = PTR_ERR(curr_p);
4787 goto byte0_fail;
4788 }
4789
4790 ext_pclk0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4791 ext_byte0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4792
4793 if (compat_bin) {
4794 curr_p = ext_pclk1_clk_src.c.parent = devm_clk_get(&pdev->dev,
4795 "pclk1_src");
4796 if (IS_ERR(curr_p)) {
4797 dev_err(&pdev->dev, "Failed to get pclk1 source.\n");
4798 ret = PTR_ERR(curr_p);
4799 goto fail;
4800 }
4801
4802 curr_p = ext_byte1_clk_src.c.parent = devm_clk_get(&pdev->dev,
4803 "byte1_src");
4804 if (IS_ERR(curr_p)) {
4805 dev_err(&pdev->dev, "Failed to get byte1 source.\n");
4806 ret = PTR_ERR(curr_p);
4807 goto byte1_fail;
4808 }
4809
4810 ext_pclk1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4811 ext_byte1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4812 }
4813
4814 ret = of_msm_clock_register(pdev->dev.of_node,
4815 msm_clocks_gcc_mdss_common,
4816 ARRAY_SIZE(msm_clocks_gcc_mdss_common));
4817 if (ret)
4818 goto fail;
4819
4820 if (compat_bin) {
4821 ret = of_msm_clock_register(pdev->dev.of_node,
4822 msm_clocks_gcc_mdss_8937,
4823 ARRAY_SIZE(msm_clocks_gcc_mdss_8937));
4824 if (ret)
4825 goto fail_8937;
4826 }
4827
4828 dev_info(&pdev->dev, "Registered GCC MDSS clocks.\n");
4829
4830 return ret;
4831fail_8937:
4832 devm_clk_put(&pdev->dev, ext_byte1_clk_src.c.parent);
4833byte1_fail:
4834 devm_clk_put(&pdev->dev, ext_pclk1_clk_src.c.parent);
4835fail:
4836 devm_clk_put(&pdev->dev, ext_byte0_clk_src.c.parent);
4837byte0_fail:
4838 devm_clk_put(&pdev->dev, ext_pclk0_clk_src.c.parent);
4839 return ret;
4840
4841}
4842
4843static const struct of_device_id msm_clock_mdss_match_table[] = {
4844 { .compatible = "qcom,gcc-mdss-8952" },
4845 { .compatible = "qcom,gcc-mdss-8937" },
4846 { .compatible = "qcom,gcc-mdss-8917" },
4847 { .compatible = "qcom,gcc-mdss-8940" },
4848 { .compatible = "qcom,gcc-mdss-8920" },
4849 {}
4850};
4851
4852static struct platform_driver msm_clock_gcc_mdss_driver = {
4853 .probe = msm_gcc_mdss_probe,
4854 .driver = {
4855 .name = "gcc-mdss-8952",
4856 .of_match_table = msm_clock_mdss_match_table,
4857 .owner = THIS_MODULE,
4858 },
4859};
4860
4861static int __init msm_gcc_mdss_init(void)
4862{
4863 return platform_driver_register(&msm_clock_gcc_mdss_driver);
4864}
4865arch_initcall(msm_gcc_init);
4866fs_initcall_sync(msm_gcc_mdss_init);
4867late_initcall(msm_clock_debug_init);