blob: 6b1ebd964c108429f7feff86f74b17b124229f88 [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Arun Chandran92980402014-10-10 12:31:24 +01003 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01004 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Laura Abbott308c09f2014-08-08 14:23:25 -07005 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +01006 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +01007 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +02008 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +01009 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000010 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000011 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000012 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000013 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000014 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010015 select AUDIT_ARCH_COMPAT_GENERIC
Marc Zyngier021f6532014-06-30 16:01:31 +010016 select ARM_GIC_V3
Will Deaconadace892013-05-08 17:29:24 +010017 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000018 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070019 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000020 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000021 select DCACHE_WORD_ACCESS
Laura Abbottd4932f92014-10-09 15:26:44 -070022 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010023 select GENERIC_CLOCKEVENTS
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010024 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000025 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070026 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010027 select GENERIC_IRQ_PROBE
28 select GENERIC_IRQ_SHOW
Arnd Bergmanncb61f672014-11-19 14:09:07 +010029 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070030 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010031 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000032 select GENERIC_STRNCPY_FROM_USER
33 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010034 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010035 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010036 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010037 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010038 select HAVE_ARCH_AUDITSYSCALL
Jiang Liu9732caf2014-01-07 22:17:13 +080039 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000040 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000041 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010042 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070043 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010044 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010045 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010046 select HAVE_CMPXCHG_DOUBLE
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070047 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070048 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010049 select HAVE_DMA_API_DEBUG
50 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000051 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010052 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000053 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010054 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090055 select HAVE_FUNCTION_TRACER
56 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010057 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010058 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010059 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000060 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010061 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010062 select HAVE_PERF_REGS
63 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070064 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010065 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010066 select IRQ_DOMAIN
Catalin Marinasfea2aca2012-10-16 11:26:57 +010067 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010068 select NO_BOOTMEM
69 select OF
70 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010071 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010072 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000073 select POWER_RESET
74 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010075 select RTC_LIB
76 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070077 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070078 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010079 help
80 ARM 64-bit (AArch64) Linux support.
81
82config 64BIT
83 def_bool y
84
85config ARCH_PHYS_ADDR_T_64BIT
86 def_bool y
87
88config MMU
89 def_bool y
90
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070091config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +010092 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010093
94config STACKTRACE_SUPPORT
95 def_bool y
96
97config LOCKDEP_SUPPORT
98 def_bool y
99
100config TRACE_IRQFLAGS_SUPPORT
101 def_bool y
102
Will Deaconc209f792014-03-14 17:47:05 +0000103config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100104 def_bool y
105
106config GENERIC_HWEIGHT
107 def_bool y
108
109config GENERIC_CSUM
110 def_bool y
111
112config GENERIC_CALIBRATE_DELAY
113 def_bool y
114
Catalin Marinas19e76402014-02-27 12:09:22 +0000115config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100116 def_bool y
117
Steve Capper29e56942014-10-09 15:29:25 -0700118config HAVE_GENERIC_RCU_GUP
119 def_bool y
120
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100121config ARCH_DMA_ADDR_T_64BIT
122 def_bool y
123
124config NEED_DMA_MAP_STATE
125 def_bool y
126
127config NEED_SG_DMA_LENGTH
128 def_bool y
129
130config SWIOTLB
131 def_bool y
132
133config IOMMU_HELPER
134 def_bool SWIOTLB
135
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100136config KERNEL_MODE_NEON
137 def_bool y
138
Rob Herring92cc15f2014-04-18 17:19:59 -0500139config FIX_EARLYCON_MEM
140 def_bool y
141
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100142source "init/Kconfig"
143
144source "kernel/Kconfig.freezer"
145
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100146menu "Platform selection"
147
Suravee Suthikulpanit41904362014-11-26 11:51:09 +0700148config ARCH_SEATTLE
149 bool "AMD Seattle SoC Family"
150 help
151 This enables support for AMD Seattle SOC Family
152
Radha Mohan Chintakuntla28f74202014-04-08 18:47:51 +0530153config ARCH_THUNDER
154 bool "Cavium Inc. Thunder SoC Family"
155 help
156 This enables support for Cavium's Thunder Family of SoCs.
157
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100158config ARCH_VEXPRESS
159 bool "ARMv8 software model (Versatile Express)"
160 select ARCH_REQUIRE_GPIOLIB
161 select COMMON_CLK_VERSATILE
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000162 select POWER_RESET_VEXPRESS
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100163 select VEXPRESS_CONFIG
164 help
165 This enables support for the ARMv8 software model (Versatile
166 Express).
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100167
Vinayak Kale15942852013-04-24 10:06:57 +0100168config ARCH_XGENE
169 bool "AppliedMicro X-Gene SOC Family"
170 help
171 This enables support for AppliedMicro X-Gene SOC Family
172
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100173endmenu
174
175menu "Bus support"
176
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100177config PCI
178 bool "PCI support"
179 help
180 This feature enables support for PCI bus system. If you say Y
181 here, the kernel will include drivers and infrastructure code
182 to support PCI bus devices.
183
184config PCI_DOMAINS
185 def_bool PCI
186
187config PCI_DOMAINS_GENERIC
188 def_bool PCI
189
190config PCI_SYSCALL
191 def_bool PCI
192
193source "drivers/pci/Kconfig"
194source "drivers/pci/pcie/Kconfig"
195source "drivers/pci/hotplug/Kconfig"
196
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100197endmenu
198
199menu "Kernel Features"
200
Andre Przywarac0a01b82014-11-14 15:54:12 +0000201menu "ARM errata workarounds via the alternatives framework"
202
203config ARM64_ERRATUM_826319
204 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
205 default y
206 help
207 This option adds an alternative code sequence to work around ARM
208 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
209 AXI master interface and an L2 cache.
210
211 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
212 and is unable to accept a certain write via this interface, it will
213 not progress on read data presented on the read data channel and the
214 system can deadlock.
215
216 The workaround promotes data cache clean instructions to
217 data cache clean-and-invalidate.
218 Please note that this does not necessarily enable the workaround,
219 as it depends on the alternative framework, which will only patch
220 the kernel if an affected CPU is detected.
221
222 If unsure, say Y.
223
224config ARM64_ERRATUM_827319
225 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
226 default y
227 help
228 This option adds an alternative code sequence to work around ARM
229 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
230 master interface and an L2 cache.
231
232 Under certain conditions this erratum can cause a clean line eviction
233 to occur at the same time as another transaction to the same address
234 on the AMBA 5 CHI interface, which can cause data corruption if the
235 interconnect reorders the two transactions.
236
237 The workaround promotes data cache clean instructions to
238 data cache clean-and-invalidate.
239 Please note that this does not necessarily enable the workaround,
240 as it depends on the alternative framework, which will only patch
241 the kernel if an affected CPU is detected.
242
243 If unsure, say Y.
244
245config ARM64_ERRATUM_824069
246 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
247 default y
248 help
249 This option adds an alternative code sequence to work around ARM
250 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
251 to a coherent interconnect.
252
253 If a Cortex-A53 processor is executing a store or prefetch for
254 write instruction at the same time as a processor in another
255 cluster is executing a cache maintenance operation to the same
256 address, then this erratum might cause a clean cache line to be
257 incorrectly marked as dirty.
258
259 The workaround promotes data cache clean instructions to
260 data cache clean-and-invalidate.
261 Please note that this option does not necessarily enable the
262 workaround, as it depends on the alternative framework, which will
263 only patch the kernel if an affected CPU is detected.
264
265 If unsure, say Y.
266
267config ARM64_ERRATUM_819472
268 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
269 default y
270 help
271 This option adds an alternative code sequence to work around ARM
272 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
273 present when it is connected to a coherent interconnect.
274
275 If the processor is executing a load and store exclusive sequence at
276 the same time as a processor in another cluster is executing a cache
277 maintenance operation to the same address, then this erratum might
278 cause data corruption.
279
280 The workaround promotes data cache clean instructions to
281 data cache clean-and-invalidate.
282 Please note that this does not necessarily enable the workaround,
283 as it depends on the alternative framework, which will only patch
284 the kernel if an affected CPU is detected.
285
286 If unsure, say Y.
287
288config ARM64_ERRATUM_832075
289 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
290 default y
291 help
292 This option adds an alternative code sequence to work around ARM
293 erratum 832075 on Cortex-A57 parts up to r1p2.
294
295 Affected Cortex-A57 parts might deadlock when exclusive load/store
296 instructions to Write-Back memory are mixed with Device loads.
297
298 The workaround is to promote device loads to use Load-Acquire
299 semantics.
300 Please note that this does not necessarily enable the workaround,
301 as it depends on the alternative framework, which will only patch
302 the kernel if an affected CPU is detected.
303
304 If unsure, say Y.
305
306endmenu
307
308
Jungseok Leee41ceed2014-05-12 10:40:38 +0100309choice
310 prompt "Page size"
311 default ARM64_4K_PAGES
312 help
313 Page size (translation granule) configuration.
314
315config ARM64_4K_PAGES
316 bool "4KB"
317 help
318 This feature enables 4KB pages support.
319
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100320config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100321 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100322 help
323 This feature enables 64KB pages support (4KB by default)
324 allowing only two levels of page tables and faster TLB
325 look-up. AArch32 emulation is not available when this feature
326 is enabled.
327
Jungseok Leee41ceed2014-05-12 10:40:38 +0100328endchoice
329
330choice
331 prompt "Virtual address space size"
332 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
333 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
334 help
335 Allows choosing one of multiple possible virtual address
336 space sizes. The level of translation table is determined by
337 a combination of page size and virtual address space size.
338
339config ARM64_VA_BITS_39
340 bool "39-bit"
341 depends on ARM64_4K_PAGES
342
343config ARM64_VA_BITS_42
344 bool "42-bit"
345 depends on ARM64_64K_PAGES
346
Jungseok Leec79b9542014-05-12 18:40:51 +0900347config ARM64_VA_BITS_48
348 bool "48-bit"
Christoffer Dall04f905a2014-10-10 11:14:30 +0100349 depends on !ARM_SMMU
Jungseok Leec79b9542014-05-12 18:40:51 +0900350
Jungseok Leee41ceed2014-05-12 10:40:38 +0100351endchoice
352
353config ARM64_VA_BITS
354 int
355 default 39 if ARM64_VA_BITS_39
356 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900357 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100358
Catalin Marinasabe669d2014-07-15 15:37:21 +0100359config ARM64_PGTABLE_LEVELS
360 int
361 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
Catalin Marinas383c2792014-07-21 15:54:50 +0100362 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
Catalin Marinasabe669d2014-07-15 15:37:21 +0100363 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
364 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
Jungseok Leec79b9542014-05-12 18:40:51 +0900365
Will Deacona8720132013-10-11 14:52:19 +0100366config CPU_BIG_ENDIAN
367 bool "Build big-endian kernel"
368 help
369 Say Y if you plan on running a kernel in big-endian mode.
370
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100371config SMP
372 bool "Symmetric Multi-Processing"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100373 help
374 This enables support for systems with more than one CPU. If
375 you say N here, the kernel will run on single and
376 multiprocessor machines, but will use only one CPU of a
377 multiprocessor machine. If you say Y here, the kernel will run
378 on many, but not all, single processor machines. On a single
379 processor machine, the kernel will run faster if you say N
380 here.
381
382 If you don't know what to do here, say N.
383
Mark Brownf6e763b2014-03-04 07:51:17 +0000384config SCHED_MC
385 bool "Multi-core scheduler support"
386 depends on SMP
387 help
388 Multi-core scheduler support improves the CPU scheduler's decision
389 making when dealing with multi-core CPU chips at a cost of slightly
390 increased overhead in some places. If unsure say N here.
391
392config SCHED_SMT
393 bool "SMT scheduler support"
394 depends on SMP
395 help
396 Improves the CPU scheduler's decision making when dealing with
397 MultiThreading at a cost of slightly increased overhead in some
398 places. If unsure say N here.
399
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100400config NR_CPUS
Robert Richtere3672642014-09-08 12:44:48 +0100401 int "Maximum number of CPUs (2-64)"
402 range 2 64
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100403 depends on SMP
Vinayak Kale15942852013-04-24 10:06:57 +0100404 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100405 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100406
Mark Rutland9327e2c2013-10-24 20:30:18 +0100407config HOTPLUG_CPU
408 bool "Support for hot-pluggable CPUs"
409 depends on SMP
410 help
411 Say Y here to experiment with turning CPUs off and on. CPUs
412 can be controlled through /sys/devices/system/cpu.
413
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100414source kernel/Kconfig.preempt
415
416config HZ
417 int
418 default 100
419
420config ARCH_HAS_HOLES_MEMORYMODEL
421 def_bool y if SPARSEMEM
422
423config ARCH_SPARSEMEM_ENABLE
424 def_bool y
425 select SPARSEMEM_VMEMMAP_ENABLE
426
427config ARCH_SPARSEMEM_DEFAULT
428 def_bool ARCH_SPARSEMEM_ENABLE
429
430config ARCH_SELECT_MEMORY_MODEL
431 def_bool ARCH_SPARSEMEM_ENABLE
432
433config HAVE_ARCH_PFN_VALID
434 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
435
436config HW_PERF_EVENTS
437 bool "Enable hardware performance counter support for perf events"
438 depends on PERF_EVENTS
439 default y
440 help
441 Enable hardware performance counter support for perf events. If
442 disabled, perf events will use software events only.
443
Steve Capper084bd292013-04-10 13:48:00 +0100444config SYS_SUPPORTS_HUGETLBFS
445 def_bool y
446
447config ARCH_WANT_GENERAL_HUGETLB
448 def_bool y
449
450config ARCH_WANT_HUGE_PMD_SHARE
451 def_bool y if !ARM64_64K_PAGES
452
Steve Capperaf074842013-04-19 16:23:57 +0100453config HAVE_ARCH_TRANSPARENT_HUGEPAGE
454 def_bool y
455
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100456config ARCH_HAS_CACHE_LINE_SIZE
457 def_bool y
458
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100459source "mm/Kconfig"
460
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000461config SECCOMP
462 bool "Enable seccomp to safely compute untrusted bytecode"
463 ---help---
464 This kernel feature is useful for number crunching applications
465 that may need to compute untrusted bytecode during their
466 execution. By using pipes or other transports made available to
467 the process as file descriptors supporting the read/write
468 syscalls, it's possible to isolate those applications in
469 their own address space using seccomp. Once seccomp is
470 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
471 and the task is only allowed to execute a few safe syscalls
472 defined by each seccomp mode.
473
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000474config XEN_DOM0
475 def_bool y
476 depends on XEN
477
478config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700479 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000480 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000481 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000482 help
483 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
484
Steve Capperd03bb142013-04-25 15:19:21 +0100485config FORCE_MAX_ZONEORDER
486 int
487 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
488 default "11"
489
Will Deacon1b907f42014-11-20 16:51:10 +0000490menuconfig ARMV8_DEPRECATED
491 bool "Emulate deprecated/obsolete ARMv8 instructions"
492 depends on COMPAT
493 help
494 Legacy software support may require certain instructions
495 that have been deprecated or obsoleted in the architecture.
496
497 Enable this config to enable selective emulation of these
498 features.
499
500 If unsure, say Y
501
502if ARMV8_DEPRECATED
503
504config SWP_EMULATION
505 bool "Emulate SWP/SWPB instructions"
506 help
507 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
508 they are always undefined. Say Y here to enable software
509 emulation of these instructions for userspace using LDXR/STXR.
510
511 In some older versions of glibc [<=2.8] SWP is used during futex
512 trylock() operations with the assumption that the code will not
513 be preempted. This invalid assumption may be more likely to fail
514 with SWP emulation enabled, leading to deadlock of the user
515 application.
516
517 NOTE: when accessing uncached shared regions, LDXR/STXR rely
518 on an external transaction monitoring block called a global
519 monitor to maintain update atomicity. If your system does not
520 implement a global monitor, this option can cause programs that
521 perform SWP operations to uncached memory to deadlock.
522
523 If unsure, say Y
524
525config CP15_BARRIER_EMULATION
526 bool "Emulate CP15 Barrier instructions"
527 help
528 The CP15 barrier instructions - CP15ISB, CP15DSB, and
529 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
530 strongly recommended to use the ISB, DSB, and DMB
531 instructions instead.
532
533 Say Y here to enable software emulation of these
534 instructions for AArch32 userspace code. When this option is
535 enabled, CP15 barrier usage is traced which can help
536 identify software that needs updating.
537
538 If unsure, say Y
539
540endif
541
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100542endmenu
543
544menu "Boot options"
545
546config CMDLINE
547 string "Default kernel command string"
548 default ""
549 help
550 Provide a set of default command-line options at build time by
551 entering them here. As a minimum, you should specify the the
552 root device (e.g. root=/dev/nfs).
553
554config CMDLINE_FORCE
555 bool "Always use the default kernel command string"
556 help
557 Always use the default kernel command string, even if the boot
558 loader passes other arguments to the kernel.
559 This is useful if you cannot or don't want to change the
560 command-line options your boot loader passes to the kernel.
561
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200562config EFI_STUB
563 bool
564
Mark Salterf84d0272014-04-15 21:59:30 -0400565config EFI
566 bool "UEFI runtime support"
567 depends on OF && !CPU_BIG_ENDIAN
568 select LIBFDT
569 select UCS2_STRING
570 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200571 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200572 select EFI_STUB
573 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400574 default y
575 help
576 This option provides support for runtime services provided
577 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400578 clock, and platform reset). A UEFI stub is also provided to
579 allow the kernel to be booted as an EFI application. This
580 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400581
Yi Lid1ae8c02014-10-04 23:46:43 +0800582config DMI
583 bool "Enable support for SMBIOS (DMI) tables"
584 depends on EFI
585 default y
586 help
587 This enables SMBIOS/DMI feature for systems.
588
589 This option is only useful on systems that have UEFI firmware.
590 However, even with this option, the resultant kernel should
591 continue to boot on existing non-UEFI platforms.
592
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100593endmenu
594
595menu "Userspace binary formats"
596
597source "fs/Kconfig.binfmt"
598
599config COMPAT
600 bool "Kernel support for 32-bit EL0"
601 depends on !ARM64_64K_PAGES
602 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700603 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500604 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500605 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100606 help
607 This option enables support for a 32-bit EL0 running under a 64-bit
608 kernel at EL1. AArch32-specific components such as system calls,
609 the user helper functions, VFP support and the ptrace interface are
610 handled appropriately by the kernel.
611
612 If you want to execute 32-bit userspace applications, say Y.
613
614config SYSVIPC_COMPAT
615 def_bool y
616 depends on COMPAT && SYSVIPC
617
618endmenu
619
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000620menu "Power management options"
621
622source "kernel/power/Kconfig"
623
624config ARCH_SUSPEND_POSSIBLE
625 def_bool y
626
627config ARM64_CPU_SUSPEND
628 def_bool PM_SLEEP
629
630endmenu
631
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100632menu "CPU Power Management"
633
634source "drivers/cpuidle/Kconfig"
635
Rob Herring52e7e812014-02-24 11:27:57 +0900636source "drivers/cpufreq/Kconfig"
637
638endmenu
639
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100640source "net/Kconfig"
641
642source "drivers/Kconfig"
643
Mark Salterf84d0272014-04-15 21:59:30 -0400644source "drivers/firmware/Kconfig"
645
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100646source "fs/Kconfig"
647
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100648source "arch/arm64/kvm/Kconfig"
649
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100650source "arch/arm64/Kconfig.debug"
651
652source "security/Kconfig"
653
654source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800655if CRYPTO
656source "arch/arm64/crypto/Kconfig"
657endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100658
659source "lib/Kconfig"