Blame - drivers/mfd/wcd9335-regmap.c - SHIFTPHONES/android_kernel_shift_sdm845

Banajit Goswami

de8271c

2017-01-18 00:28:59 -0800

[diff] [blame]

/*

*

* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License version 2 and

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* only version 2 as published by the Free Software Foundation.

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*

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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*/

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#include <linux/mfd/wcd9xxx/core.h>

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#include <linux/mfd/wcd9335/registers.h>

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#include <linux/regmap.h>

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#include <linux/device.h>

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#include "wcd9xxx-regmap.h"

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static const struct reg_sequence wcd9335_1_x_defaults[] = {

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{ WCD9335_CODEC_RPM_CLK_GATE, 0x03, 0x00 },

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{ WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN, 0x1f, 0x00 },

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{ WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 0x00, 0x00 },

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{ WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 0x00, 0x00 },

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{ WCD9335_DATA_HUB_DATA_HUB_RX0_INP_CFG, 0x00, 0x00 },

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{ WCD9335_DATA_HUB_DATA_HUB_RX1_INP_CFG, 0x00, 0x00 },

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{ WCD9335_DATA_HUB_DATA_HUB_RX2_INP_CFG, 0x00, 0x00 },

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{ WCD9335_DATA_HUB_DATA_HUB_RX3_INP_CFG, 0x00, 0x00 },

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{ WCD9335_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD, 0x14, 0x00 },

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{ WCD9335_CPE_SS_SS_ERROR_INT_MASK, 0x3f, 0x00 },

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{ WCD9335_SOC_MAD_AUDIO_IIR_CTL_VAL, 0x00, 0x00 },

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{ WCD9335_BIAS_VBG_FINE_ADJ, 0x55, 0x00 },

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{ WCD9335_SIDO_SIDO_CCL_2, 0x6c, 0x00 },

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{ WCD9335_SIDO_SIDO_CCL_3, 0x2d, 0x00 },

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{ WCD9335_SIDO_SIDO_CCL_8, 0x6c, 0x00 },

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{ WCD9335_SIDO_SIDO_CCL_10, 0x6c, 0x00 },

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{ WCD9335_SIDO_SIDO_DRIVER_2, 0x77, 0x00 },

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{ WCD9335_SIDO_SIDO_DRIVER_3, 0x77, 0x00 },

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{ WCD9335_SIDO_SIDO_TEST_2, 0x00, 0x00 },

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{ WCD9335_MBHC_ZDET_ANA_CTL, 0x00, 0x00 },

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{ WCD9335_MBHC_FSM_DEBUG, 0xc0, 0x00 },

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{ WCD9335_TX_1_2_ATEST_REFCTL, 0x08, 0x00 },

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{ WCD9335_TX_3_4_ATEST_REFCTL, 0x08, 0x00 },

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{ WCD9335_TX_5_6_ATEST_REFCTL, 0x08, 0x00 },

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{ WCD9335_FLYBACK_VNEG_CTRL_1, 0x67, 0x00 },

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{ WCD9335_FLYBACK_VNEG_CTRL_4, 0x5f, 0x00 },

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{ WCD9335_FLYBACK_VNEG_CTRL_9, 0x50, 0x00 },

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{ WCD9335_FLYBACK_VNEG_DAC_CTRL_1, 0x65, 0x00 },

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{ WCD9335_FLYBACK_VNEG_DAC_CTRL_4, 0x40, 0x00 },

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{ WCD9335_RX_BIAS_HPH_PA, 0xaa, 0x00 },

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{ WCD9335_RX_BIAS_HPH_LOWPOWER, 0x62, 0x00 },

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{ WCD9335_HPH_PA_CTL2, 0x40, 0x00 },

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{ WCD9335_HPH_L_EN, 0x00, 0x00 },

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{ WCD9335_HPH_R_EN, 0x00, 0x00 },

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{ WCD9335_HPH_R_ATEST, 0x50, 0x00 },

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{ WCD9335_HPH_RDAC_LDO_CTL, 0x00, 0x00 },

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{ WCD9335_CDC_TX0_TX_PATH_CFG0, 0x00, 0x00 },

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{ WCD9335_CDC_TX0_TX_PATH_CFG1, 0x00, 0x00 },

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{ WCD9335_CDC_TX0_TX_PATH_SEC2, 0x00, 0x00 },

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{ WCD9335_CDC_TX0_TX_PATH_SEC3, 0x0c, 0x00 },

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{ WCD9335_CDC_TX1_TX_PATH_CFG0, 0x00, 0x00 },

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{ WCD9335_CDC_TX1_TX_PATH_CFG1, 0x00, 0x00 },

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{ WCD9335_CDC_TX1_TX_PATH_SEC2, 0x00, 0x00 },

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{ WCD9335_CDC_TX1_TX_PATH_SEC3, 0x0c, 0x00 },

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{ WCD9335_CDC_TX2_TX_PATH_CFG0, 0x00, 0x00 },

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{ WCD9335_CDC_TX3_TX_PATH_CFG0, 0x00, 0x00 },

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{ WCD9335_CDC_TX4_TX_PATH_CFG0, 0x00, 0x00 },

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{ WCD9335_CDC_TX5_TX_PATH_CFG0, 0x00, 0x00 },

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{ WCD9335_CDC_TX6_TX_PATH_CFG0, 0x00, 0x00 },

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{ WCD9335_CDC_TX7_TX_PATH_CFG0, 0x00, 0x00 },

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{ WCD9335_CDC_TX8_TX_PATH_CFG0, 0x00, 0x00 },

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{ WCD9335_CDC_TX2_TX_PATH_CFG1, 0x00, 0x00 },

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{ WCD9335_CDC_TX3_TX_PATH_CFG1, 0x00, 0x00 },

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{ WCD9335_CDC_TX4_TX_PATH_CFG1, 0x00, 0x00 },

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{ WCD9335_CDC_TX5_TX_PATH_CFG1, 0x00, 0x00 },

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{ WCD9335_CDC_TX6_TX_PATH_CFG1, 0x00, 0x00 },

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{ WCD9335_CDC_TX7_TX_PATH_CFG1, 0x00, 0x00 },

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{ WCD9335_CDC_TX8_TX_PATH_CFG1, 0x00, 0x00 },

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{ WCD9335_CDC_TX2_TX_PATH_SEC2, 0x00, 0x00 },

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{ WCD9335_CDC_TX3_TX_PATH_SEC2, 0x00, 0x00 },

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{ WCD9335_CDC_TX4_TX_PATH_SEC2, 0x00, 0x00 },

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{ WCD9335_CDC_TX5_TX_PATH_SEC2, 0x00, 0x00 },

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{ WCD9335_CDC_TX6_TX_PATH_SEC2, 0x00, 0x00 },

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{ WCD9335_CDC_TX7_TX_PATH_SEC2, 0x00, 0x00 },

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{ WCD9335_CDC_TX8_TX_PATH_SEC2, 0x00, 0x00 },

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{ WCD9335_CDC_TX2_TX_PATH_SEC3, 0x0c, 0x00 },

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{ WCD9335_CDC_TX3_TX_PATH_SEC3, 0x0c, 0x00 },

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{ WCD9335_CDC_TX4_TX_PATH_SEC3, 0x0c, 0x00 },

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{ WCD9335_CDC_TX5_TX_PATH_SEC3, 0x0c, 0x00 },

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{ WCD9335_CDC_TX6_TX_PATH_SEC3, 0x0c, 0x00 },

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{ WCD9335_CDC_TX7_TX_PATH_SEC3, 0x0c, 0x00 },

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{ WCD9335_CDC_TX8_TX_PATH_SEC3, 0x0c, 0x00 },

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{ WCD9335_CDC_COMPANDER1_CTL7, 0x0c, 0x00 },

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{ WCD9335_CDC_COMPANDER2_CTL7, 0x0c, 0x00 },

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{ WCD9335_CDC_COMPANDER3_CTL7, 0x0c, 0x00 },

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{ WCD9335_CDC_COMPANDER4_CTL7, 0x0c, 0x00 },

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{ WCD9335_CDC_COMPANDER5_CTL7, 0x0c, 0x00 },

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{ WCD9335_CDC_COMPANDER6_CTL7, 0x0c, 0x00 },

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{ WCD9335_CDC_COMPANDER7_CTL7, 0x0c, 0x00 },

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{ WCD9335_CDC_COMPANDER8_CTL7, 0x0c, 0x00 },

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{ WCD9335_CDC_RX0_RX_PATH_CFG1, 0x04, 0x00 },

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{ WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x0e, 0x00 },

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{ WCD9335_CDC_RX0_RX_PATH_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX0_RX_PATH_SEC1, 0x00, 0x00 },

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{ WCD9335_CDC_RX0_RX_PATH_MIX_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX1_RX_PATH_CFG1, 0x04, 0x00 },

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{ WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x0e, 0x00 },

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{ WCD9335_CDC_RX1_RX_PATH_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX1_RX_PATH_SEC1, 0x00, 0x00 },

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{ WCD9335_CDC_RX1_RX_PATH_MIX_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX2_RX_PATH_CFG1, 0x04, 0x00 },

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{ WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x0e, 0x00 },

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{ WCD9335_CDC_RX2_RX_PATH_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX2_RX_PATH_SEC1, 0x00, 0x00 },

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{ WCD9335_CDC_RX2_RX_PATH_MIX_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX3_RX_PATH_CFG1, 0x04, 0x00 },

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{ WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x0e, 0x00 },

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{ WCD9335_CDC_RX3_RX_PATH_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX3_RX_PATH_SEC1, 0x00, 0x00 },

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{ WCD9335_CDC_RX3_RX_PATH_MIX_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX4_RX_PATH_CFG1, 0x04, 0x00 },

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{ WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x0e, 0x00 },

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{ WCD9335_CDC_RX4_RX_PATH_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX4_RX_PATH_SEC1, 0x00, 0x00 },

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{ WCD9335_CDC_RX4_RX_PATH_MIX_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX5_RX_PATH_CFG1, 0x04, 0x00 },

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{ WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x0e, 0x00 },

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{ WCD9335_CDC_RX5_RX_PATH_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX5_RX_PATH_SEC1, 0x00, 0x00 },

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{ WCD9335_CDC_RX5_RX_PATH_MIX_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX6_RX_PATH_CFG1, 0x04, 0x00 },

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{ WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x0e, 0x00 },

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{ WCD9335_CDC_RX6_RX_PATH_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX6_RX_PATH_SEC1, 0x00, 0x00 },

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{ WCD9335_CDC_RX6_RX_PATH_MIX_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX7_RX_PATH_CFG1, 0x04, 0x00 },

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{ WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x0e, 0x00 },

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{ WCD9335_CDC_RX7_RX_PATH_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX7_RX_PATH_SEC1, 0x00, 0x00 },

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{ WCD9335_CDC_RX7_RX_PATH_MIX_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX8_RX_PATH_CFG1, 0x04, 0x00 },

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{ WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x0e, 0x00 },

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{ WCD9335_CDC_RX8_RX_PATH_SEC0, 0x00, 0x00 },

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{ WCD9335_CDC_RX8_RX_PATH_SEC1, 0x00, 0x00 },

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{ WCD9335_CDC_RX8_RX_PATH_MIX_SEC0, 0x00, 0x00 },

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{ WCD9335_SPLINE_SRC0_CLK_RST_CTL_0, 0x00, 0x00 },

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{ WCD9335_SPLINE_SRC1_CLK_RST_CTL_0, 0x00, 0x00 },

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{ WCD9335_SPLINE_SRC2_CLK_RST_CTL_0, 0x00, 0x00 },

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{ WCD9335_SPLINE_SRC3_CLK_RST_CTL_0, 0x00, 0x00 },

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{ WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00, 0x00 },

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{ WCD9335_TEST_DEBUG_NPL_DLY_TEST_1, 0x00, 0x00 },

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{ WCD9335_TEST_DEBUG_NPL_DLY_TEST_2, 0x00, 0x00 },

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};

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static const struct reg_sequence wcd9335_2_0_defaults[] = {

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{ WCD9335_CODEC_RPM_CLK_GATE, 0x07, 0x00 },

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{ WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN, 0x3f, 0x00 },

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{ WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 0x01, 0x00 },

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{ WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 0x10, 0x00 },

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{ WCD9335_DATA_HUB_DATA_HUB_RX0_INP_CFG, 0x08, 0x00 },

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{ WCD9335_DATA_HUB_DATA_HUB_RX1_INP_CFG, 0x08, 0x00 },

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{ WCD9335_DATA_HUB_DATA_HUB_RX2_INP_CFG, 0x08, 0x00 },

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{ WCD9335_DATA_HUB_DATA_HUB_RX3_INP_CFG, 0x08, 0x00 },

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{ WCD9335_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD, 0x13, 0x00 },

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{ WCD9335_CPE_SS_SS_ERROR_INT_MASK, 0xff, 0x00 },

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{ WCD9335_SOC_MAD_AUDIO_IIR_CTL_VAL, 0x40, 0x00 },

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{ WCD9335_BIAS_VBG_FINE_ADJ, 0xc5, 0x00 },

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{ WCD9335_SIDO_SIDO_CCL_2, 0x92, 0x00 },

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{ WCD9335_SIDO_SIDO_CCL_3, 0x35, 0x00 },

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{ WCD9335_SIDO_SIDO_CCL_8, 0x6e, 0x00 },

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{ WCD9335_SIDO_SIDO_CCL_10, 0x6e, 0x00 },

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{ WCD9335_SIDO_SIDO_DRIVER_2, 0x55, 0x00 },

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{ WCD9335_SIDO_SIDO_DRIVER_3, 0x55, 0x00 },

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{ WCD9335_SIDO_SIDO_TEST_2, 0x0f, 0x00 },

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{ WCD9335_MBHC_ZDET_ANA_CTL, 0x0f, 0x00 },

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{ WCD9335_TX_1_2_ATEST_REFCTL, 0x0a, 0x00 },

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{ WCD9335_TX_3_4_ATEST_REFCTL, 0x0a, 0x00 },

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{ WCD9335_TX_5_6_ATEST_REFCTL, 0x0a, 0x00 },

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{ WCD9335_FLYBACK_VNEG_CTRL_1, 0xeb, 0x00 },

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{ WCD9335_FLYBACK_VNEG_CTRL_4, 0x7f, 0x00 },

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{ WCD9335_FLYBACK_VNEG_CTRL_9, 0x64, 0x00 },

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{ WCD9335_FLYBACK_VNEG_DAC_CTRL_1, 0xed, 0x00 },

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{ WCD9335_RX_BIAS_HPH_PA, 0x9a, 0x00 },

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{ WCD9335_RX_BIAS_HPH_LOWPOWER, 0x82, 0x00 },

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{ WCD9335_HPH_PA_CTL2, 0x50, 0x00 },

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{ WCD9335_HPH_L_EN, 0x80, 0x00 },

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{ WCD9335_HPH_R_EN, 0x80, 0x00 },

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{ WCD9335_HPH_R_ATEST, 0x54, 0x00 },

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{ WCD9335_HPH_RDAC_LDO_CTL, 0x33, 0x00 },

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{ WCD9335_CDC_TX0_TX_PATH_CFG0, 0x10, 0x00 },

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{ WCD9335_CDC_TX0_TX_PATH_CFG1, 0x02, 0x00 },

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{ WCD9335_CDC_TX0_TX_PATH_SEC2, 0x01, 0x00 },

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{ WCD9335_CDC_TX0_TX_PATH_SEC3, 0x3c, 0x00 },

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{ WCD9335_CDC_TX1_TX_PATH_CFG0, 0x10, 0x00 },

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{ WCD9335_CDC_TX1_TX_PATH_CFG1, 0x02, 0x00 },

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{ WCD9335_CDC_TX1_TX_PATH_SEC2, 0x01, 0x00 },

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{ WCD9335_CDC_TX1_TX_PATH_SEC3, 0x3c, 0x00 },

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{ WCD9335_CDC_TX2_TX_PATH_CFG0, 0x10, 0x00 },

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{ WCD9335_CDC_TX3_TX_PATH_CFG0, 0x10, 0x00 },

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{ WCD9335_CDC_TX4_TX_PATH_CFG0, 0x10, 0x00 },

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{ WCD9335_CDC_TX5_TX_PATH_CFG0, 0x10, 0x00 },

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{ WCD9335_CDC_TX6_TX_PATH_CFG0, 0x10, 0x00 },

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{ WCD9335_CDC_TX7_TX_PATH_CFG0, 0x10, 0x00 },

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{ WCD9335_CDC_TX8_TX_PATH_CFG0, 0x10, 0x00 },

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{ WCD9335_CDC_TX2_TX_PATH_CFG1, 0x02, 0x00 },

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{ WCD9335_CDC_TX3_TX_PATH_CFG1, 0x02, 0x00 },

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{ WCD9335_CDC_TX4_TX_PATH_CFG1, 0x02, 0x00 },

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{ WCD9335_CDC_TX5_TX_PATH_CFG1, 0x02, 0x00 },

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{ WCD9335_CDC_TX6_TX_PATH_CFG1, 0x02, 0x00 },

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{ WCD9335_CDC_TX7_TX_PATH_CFG1, 0x02, 0x00 },

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{ WCD9335_CDC_TX8_TX_PATH_CFG1, 0x02, 0x00 },

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{ WCD9335_CDC_TX2_TX_PATH_SEC2, 0x01, 0x00 },

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{ WCD9335_CDC_TX3_TX_PATH_SEC2, 0x01, 0x00 },

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{ WCD9335_CDC_TX4_TX_PATH_SEC2, 0x01, 0x00 },

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{ WCD9335_CDC_TX5_TX_PATH_SEC2, 0x01, 0x00 },

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{ WCD9335_CDC_TX6_TX_PATH_SEC2, 0x01, 0x00 },

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{ WCD9335_CDC_TX7_TX_PATH_SEC2, 0x01, 0x00 },

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{ WCD9335_CDC_TX8_TX_PATH_SEC2, 0x01, 0x00 },

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{ WCD9335_CDC_TX2_TX_PATH_SEC3, 0x3c, 0x00 },

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{ WCD9335_CDC_TX3_TX_PATH_SEC3, 0x3c, 0x00 },

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{ WCD9335_CDC_TX4_TX_PATH_SEC3, 0x3c, 0x00 },

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{ WCD9335_CDC_TX5_TX_PATH_SEC3, 0x3c, 0x00 },

223

{ WCD9335_CDC_TX6_TX_PATH_SEC3, 0x3c, 0x00 },

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{ WCD9335_CDC_TX7_TX_PATH_SEC3, 0x3c, 0x00 },

225

{ WCD9335_CDC_TX8_TX_PATH_SEC3, 0x3c, 0x00 },

226

{ WCD9335_CDC_COMPANDER1_CTL7, 0x08, 0x00 },

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{ WCD9335_CDC_COMPANDER2_CTL7, 0x08, 0x00 },

228

{ WCD9335_CDC_COMPANDER3_CTL7, 0x08, 0x00 },

229

{ WCD9335_CDC_COMPANDER4_CTL7, 0x08, 0x00 },

230

{ WCD9335_CDC_COMPANDER5_CTL7, 0x08, 0x00 },

231

{ WCD9335_CDC_COMPANDER6_CTL7, 0x08, 0x00 },

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{ WCD9335_CDC_COMPANDER7_CTL7, 0x08, 0x00 },

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{ WCD9335_CDC_COMPANDER8_CTL7, 0x08, 0x00 },

234

{ WCD9335_CDC_RX0_RX_PATH_CFG1, 0x44, 0x00 },

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{ WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x1e, 0x00 },

236

{ WCD9335_CDC_RX0_RX_PATH_SEC0, 0xfc, 0x00 },

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{ WCD9335_CDC_RX0_RX_PATH_SEC1, 0x08, 0x00 },

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{ WCD9335_CDC_RX0_RX_PATH_MIX_SEC0, 0x08, 0x00 },

239

{ WCD9335_CDC_RX1_RX_PATH_CFG1, 0x44, 0x00 },

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{ WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x1e, 0x00 },

241

{ WCD9335_CDC_RX1_RX_PATH_SEC0, 0xfc, 0x00 },

242

{ WCD9335_CDC_RX1_RX_PATH_SEC1, 0x08, 0x00 },

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{ WCD9335_CDC_RX1_RX_PATH_MIX_SEC0, 0x08, 0x00 },

244

{ WCD9335_CDC_RX2_RX_PATH_CFG1, 0x44, 0x00 },

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{ WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x1e, 0x00 },

246

{ WCD9335_CDC_RX2_RX_PATH_SEC0, 0xfc, 0x00 },

247

{ WCD9335_CDC_RX2_RX_PATH_SEC1, 0x08, 0x00 },

248

{ WCD9335_CDC_RX2_RX_PATH_MIX_SEC0, 0x08, 0x00 },

249

{ WCD9335_CDC_RX3_RX_PATH_CFG1, 0x44, 0x00 },

250

{ WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x1e, 0x00 },

251

{ WCD9335_CDC_RX3_RX_PATH_SEC0, 0xfc, 0x00 },

252

{ WCD9335_CDC_RX3_RX_PATH_SEC1, 0x08, 0x00 },

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{ WCD9335_CDC_RX3_RX_PATH_MIX_SEC0, 0x08, 0x00 },

254

{ WCD9335_CDC_RX4_RX_PATH_CFG1, 0x44, 0x00 },

255

{ WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x1e, 0x00 },

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{ WCD9335_CDC_RX4_RX_PATH_SEC0, 0xfc, 0x00 },

257

{ WCD9335_CDC_RX4_RX_PATH_SEC1, 0x08, 0x00 },

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{ WCD9335_CDC_RX4_RX_PATH_MIX_SEC0, 0x08, 0x00 },

259

{ WCD9335_CDC_RX5_RX_PATH_CFG1, 0x44, 0x00 },

260

{ WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x1e, 0x00 },

261

{ WCD9335_CDC_RX5_RX_PATH_SEC0, 0xfc, 0x00 },

262

{ WCD9335_CDC_RX5_RX_PATH_SEC1, 0x08, 0x00 },

263

{ WCD9335_CDC_RX5_RX_PATH_MIX_SEC0, 0x08, 0x00 },

264

{ WCD9335_CDC_RX6_RX_PATH_CFG1, 0x44, 0x00 },

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{ WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x1e, 0x00 },

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{ WCD9335_CDC_RX6_RX_PATH_SEC0, 0xfc, 0x00 },

267

{ WCD9335_CDC_RX6_RX_PATH_SEC1, 0x08, 0x00 },

268

{ WCD9335_CDC_RX6_RX_PATH_MIX_SEC0, 0x08, 0x00 },

269

{ WCD9335_CDC_RX7_RX_PATH_CFG1, 0x44, 0x00 },

270

{ WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x1e, 0x00 },

271

{ WCD9335_CDC_RX7_RX_PATH_SEC0, 0xfc, 0x00 },

272

{ WCD9335_CDC_RX7_RX_PATH_SEC1, 0x08, 0x00 },

273

{ WCD9335_CDC_RX7_RX_PATH_MIX_SEC0, 0x08, 0x00 },

274

{ WCD9335_CDC_RX8_RX_PATH_CFG1, 0x44, 0x00 },

275

{ WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x1e, 0x00 },

276

{ WCD9335_CDC_RX8_RX_PATH_SEC0, 0xfc, 0x00 },

277

{ WCD9335_CDC_RX8_RX_PATH_SEC1, 0x08, 0x00 },

278

{ WCD9335_CDC_RX8_RX_PATH_MIX_SEC0, 0x08, 0x00 },

279

{ WCD9335_SPLINE_SRC0_CLK_RST_CTL_0, 0x20, 0x00 },

280

{ WCD9335_SPLINE_SRC1_CLK_RST_CTL_0, 0x20, 0x00 },

281

{ WCD9335_SPLINE_SRC2_CLK_RST_CTL_0, 0x20, 0x00 },

282

{ WCD9335_SPLINE_SRC3_CLK_RST_CTL_0, 0x20, 0x00 },

283

{ WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 0x0c, 0x00 },

284

{ WCD9335_TEST_DEBUG_NPL_DLY_TEST_1, 0x10, 0x00 },

285

{ WCD9335_TEST_DEBUG_NPL_DLY_TEST_2, 0x60, 0x00 },

286

{ WCD9335_DATA_HUB_NATIVE_FIFO_SYNC, 0x00, 0x00 },

287

{ WCD9335_DATA_HUB_NATIVE_FIFO_STATUS, 0x00, 0x00 },

288

{ WCD9335_CPE_SS_TX_PP_BUF_INT_PERIOD, 0x60, 0x00 },

289

{ WCD9335_CPE_SS_TX_PP_CFG, 0x3C, 0x00 },

290

{ WCD9335_CPE_SS_SVA_CFG, 0x00, 0x00 },

291

{ WCD9335_MBHC_FSM_STATUS, 0x00, 0x00 },

292

{ WCD9335_FLYBACK_CTRL_1, 0x45, 0x00 },

293

{ WCD9335_CDC_TX0_TX_PATH_SEC7, 0x25, 0x00 },

294

{ WCD9335_SPLINE_SRC0_STATUS, 0x00, 0x00 },

295

{ WCD9335_SPLINE_SRC1_STATUS, 0x00, 0x00 },

296

{ WCD9335_SPLINE_SRC2_STATUS, 0x00, 0x00 },

297

{ WCD9335_SPLINE_SRC3_STATUS, 0x00, 0x00 },

298

{ WCD9335_CDC_PROX_DETECT_PROX_CTL_REPEAT_PAT, 0x00, 0x00 },

299

};

300

301

static const struct reg_default wcd9335_defaults[] = {

302

/* Page #0 registers */

303

{ WCD9335_PAGE0_PAGE_REGISTER, 0x00 },

304

{ WCD9335_CODEC_RPM_CLK_BYPASS, 0x00 },

305

{ WCD9335_CODEC_RPM_CLK_MCLK_CFG, 0x00 },

306

{ WCD9335_CODEC_RPM_RST_CTL, 0x00 },

307

{ WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x07 },

308

{ WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_1, 0x00 },

309

{ WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_2, 0x00 },

310

{ WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_3, 0x00 },

311

{ WCD9335_CODEC_RPM_PWR_CPE_IRAM_SHUTDOWN, 0x01 },

312

{ WCD9335_CODEC_RPM_PWR_CPE_DRAM0_SHUTDOWN_1, 0xff },

313

{ WCD9335_CODEC_RPM_PWR_CPE_DRAM0_SHUTDOWN_2, 0xff },

314

{ WCD9335_CODEC_RPM_INT_MASK, 0x3f },

315

{ WCD9335_CODEC_RPM_INT_STATUS, 0x00 },

316

{ WCD9335_CODEC_RPM_INT_CLEAR, 0x00 },

317

{ WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE1, 0x00 },

318

{ WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE2, 0x07 },

319

{ WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE3, 0x01 },

320

{ WCD9335_CHIP_TIER_CTRL_EFUSE_TEST0, 0x00 },

321

{ WCD9335_CHIP_TIER_CTRL_EFUSE_TEST1, 0x00 },

322

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, 0x00 },

323

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT1, 0x00 },

324

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT2, 0x00 },

325

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT3, 0x00 },

326

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT4, 0x00 },

327

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT5, 0x00 },

328

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT6, 0x00 },

329

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT7, 0x00 },

330

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT8, 0x00 },

331

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT9, 0x00 },

332

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT10, 0x00 },

333

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT11, 0x00 },

334

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT12, 0x00 },

335

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT13, 0x00 },

336

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, 0x00 },

337

{ WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, 0x00 },

338

{ WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS, 0x00 },

339

{ WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_NONNEGO, 0x0d },

340

{ WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_1, 0x00 },

341

{ WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_2, 0x00 },

342

{ WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_3, 0x00 },

343

{ WCD9335_CHIP_TIER_CTRL_ANA_WAIT_STATE_CTL, 0xCC },

344

{ WCD9335_CHIP_TIER_CTRL_I2C_ACTIVE, 0x00 },

345

{ WCD9335_CHIP_TIER_CTRL_PROC1_MON_CTL, 0x06 },

346

{ WCD9335_CHIP_TIER_CTRL_PROC1_MON_STATUS, 0x00 },

347

{ WCD9335_CHIP_TIER_CTRL_PROC1_MON_CNT_MSB, 0x00 },

348

{ WCD9335_CHIP_TIER_CTRL_PROC1_MON_CNT_LSB, 0x00 },

349

{ WCD9335_CHIP_TIER_CTRL_PROC2_MON_CTL, 0x06 },

350

{ WCD9335_CHIP_TIER_CTRL_PROC2_MON_STATUS, 0x00 },

351

{ WCD9335_CHIP_TIER_CTRL_PROC2_MON_CNT_MSB, 0x00 },

352

{ WCD9335_CHIP_TIER_CTRL_PROC2_MON_CNT_LSB, 0x00 },

353

{ WCD9335_CHIP_TIER_CTRL_PROC3_MON_CTL, 0x06 },

354

{ WCD9335_CHIP_TIER_CTRL_PROC3_MON_STATUS, 0x00 },

355

{ WCD9335_CHIP_TIER_CTRL_PROC3_MON_CNT_MSB, 0x00 },

356

{ WCD9335_CHIP_TIER_CTRL_PROC3_MON_CNT_LSB, 0x00 },

357

{ WCD9335_DATA_HUB_DATA_HUB_RX_I2S_CTL, 0x0c },

358

{ WCD9335_DATA_HUB_DATA_HUB_TX_I2S_CTL, 0x0c },

359

{ WCD9335_DATA_HUB_DATA_HUB_I2S_CLK, 0x00 },

360

{ WCD9335_DATA_HUB_DATA_HUB_RX4_INP_CFG, 0x00 },

361

{ WCD9335_DATA_HUB_DATA_HUB_RX5_INP_CFG, 0x00 },

362

{ WCD9335_DATA_HUB_DATA_HUB_RX6_INP_CFG, 0x00 },

363

{ WCD9335_DATA_HUB_DATA_HUB_RX7_INP_CFG, 0x00 },

364

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX0_INP_CFG, 0x00 },

365

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX1_INP_CFG, 0x00 },

366

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX2_INP_CFG, 0x00 },

367

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX3_INP_CFG, 0x00 },

368

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX4_INP_CFG, 0x00 },

369

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX5_INP_CFG, 0x00 },

370

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX6_INP_CFG, 0x00 },

371

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX7_INP_CFG, 0x00 },

372

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX8_INP_CFG, 0x00 },

373

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX9_INP_CFG, 0x00 },

374

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX10_INP_CFG, 0x00 },

375

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX11_INP_CFG, 0x00 },

376

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX13_INP_CFG, 0x00 },

377

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX14_INP_CFG, 0x00 },

378

{ WCD9335_DATA_HUB_DATA_HUB_SB_TX15_INP_CFG, 0x00 },

379

{ WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_L_CFG, 0x00 },

380

{ WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_R_CFG, 0x00 },

381

{ WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_L_CFG, 0x00 },

382

{ WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_R_CFG, 0x00 },

383

{ WCD9335_INTR_CFG, 0x00 },

384

{ WCD9335_INTR_CLR_COMMIT, 0x00 },

385

{ WCD9335_INTR_PIN1_MASK0, 0xff },

386

{ WCD9335_INTR_PIN1_MASK1, 0xff },

387

{ WCD9335_INTR_PIN1_MASK2, 0xff },

388

{ WCD9335_INTR_PIN1_MASK3, 0xff },

389

{ WCD9335_INTR_PIN1_STATUS0, 0x00 },

390

{ WCD9335_INTR_PIN1_STATUS1, 0x00 },

391

{ WCD9335_INTR_PIN1_STATUS2, 0x00 },

392

{ WCD9335_INTR_PIN1_STATUS3, 0x00 },

393

{ WCD9335_INTR_PIN1_CLEAR0, 0x00 },

394

{ WCD9335_INTR_PIN1_CLEAR1, 0x00 },

395

{ WCD9335_INTR_PIN1_CLEAR2, 0x00 },

396

{ WCD9335_INTR_PIN1_CLEAR3, 0x00 },

397

{ WCD9335_INTR_PIN2_MASK0, 0xff },

398

{ WCD9335_INTR_PIN2_MASK1, 0xff },

399

{ WCD9335_INTR_PIN2_MASK2, 0xff },

400

{ WCD9335_INTR_PIN2_MASK3, 0xff },

401

{ WCD9335_INTR_PIN2_STATUS0, 0x00 },

402

{ WCD9335_INTR_PIN2_STATUS1, 0x00 },

403

{ WCD9335_INTR_PIN2_STATUS2, 0x00 },

404

{ WCD9335_INTR_PIN2_STATUS3, 0x00 },

405

{ WCD9335_INTR_PIN2_CLEAR0, 0x00 },

406

{ WCD9335_INTR_PIN2_CLEAR1, 0x00 },

407

{ WCD9335_INTR_PIN2_CLEAR2, 0x00 },

408

{ WCD9335_INTR_PIN2_CLEAR3, 0x00 },

409

{ WCD9335_INTR_LEVEL0, 0x03 },

410

{ WCD9335_INTR_LEVEL1, 0xe0 },

411

{ WCD9335_INTR_LEVEL2, 0x10 },

412

{ WCD9335_INTR_LEVEL3, 0x80 },

413

{ WCD9335_INTR_BYPASS0, 0x00 },

414

{ WCD9335_INTR_BYPASS1, 0x00 },

415

{ WCD9335_INTR_BYPASS2, 0x00 },

416

{ WCD9335_INTR_BYPASS3, 0x00 },

417

{ WCD9335_INTR_SET0, 0x00 },

418

{ WCD9335_INTR_SET1, 0x00 },

419

{ WCD9335_INTR_SET2, 0x00 },

420

{ WCD9335_INTR_SET3, 0x00 },

421

/* Page #1 registers */

422

{ WCD9335_PAGE1_PAGE_REGISTER, 0x00 },

423

{ WCD9335_CPE_FLL_USER_CTL_0, 0x71 },

424

{ WCD9335_CPE_FLL_USER_CTL_1, 0x34 },

425

{ WCD9335_CPE_FLL_USER_CTL_2, 0x0b },

426

{ WCD9335_CPE_FLL_USER_CTL_3, 0x02 },

427

{ WCD9335_CPE_FLL_USER_CTL_4, 0x04 },

428

{ WCD9335_CPE_FLL_USER_CTL_5, 0x02 },

429

{ WCD9335_CPE_FLL_USER_CTL_6, 0x64 },

430

{ WCD9335_CPE_FLL_USER_CTL_7, 0x00 },

431

{ WCD9335_CPE_FLL_USER_CTL_8, 0x94 },

432

{ WCD9335_CPE_FLL_USER_CTL_9, 0x70 },

433

{ WCD9335_CPE_FLL_L_VAL_CTL_0, 0x40 },

434

{ WCD9335_CPE_FLL_L_VAL_CTL_1, 0x00 },

435

{ WCD9335_CPE_FLL_DSM_FRAC_CTL_0, 0x00 },

436

{ WCD9335_CPE_FLL_DSM_FRAC_CTL_1, 0xff },

437

{ WCD9335_CPE_FLL_CONFIG_CTL_0, 0x6b },

438

{ WCD9335_CPE_FLL_CONFIG_CTL_1, 0x05 },

439

{ WCD9335_CPE_FLL_CONFIG_CTL_2, 0x08 },

440

{ WCD9335_CPE_FLL_CONFIG_CTL_3, 0x00 },

441

{ WCD9335_CPE_FLL_CONFIG_CTL_4, 0x10 },

442

{ WCD9335_CPE_FLL_TEST_CTL_0, 0x00 },

443

{ WCD9335_CPE_FLL_TEST_CTL_1, 0x00 },

444

{ WCD9335_CPE_FLL_TEST_CTL_2, 0x00 },

445

{ WCD9335_CPE_FLL_TEST_CTL_3, 0x00 },

446

{ WCD9335_CPE_FLL_TEST_CTL_4, 0x00 },

447

{ WCD9335_CPE_FLL_TEST_CTL_5, 0x00 },

448

{ WCD9335_CPE_FLL_TEST_CTL_6, 0x00 },

449

{ WCD9335_CPE_FLL_TEST_CTL_7, 0x33 },

450

{ WCD9335_CPE_FLL_FREQ_CTL_0, 0x00 },

451

{ WCD9335_CPE_FLL_FREQ_CTL_1, 0x00 },

452

{ WCD9335_CPE_FLL_FREQ_CTL_2, 0x00 },

453

{ WCD9335_CPE_FLL_FREQ_CTL_3, 0x00 },

454

{ WCD9335_CPE_FLL_SSC_CTL_0, 0x00 },

455

{ WCD9335_CPE_FLL_SSC_CTL_1, 0x00 },

456

{ WCD9335_CPE_FLL_SSC_CTL_2, 0x00 },

457

{ WCD9335_CPE_FLL_SSC_CTL_3, 0x00 },

458

{ WCD9335_CPE_FLL_FLL_MODE, 0x20 },

459

{ WCD9335_CPE_FLL_STATUS_0, 0x00 },

460

{ WCD9335_CPE_FLL_STATUS_1, 0x00 },

461

{ WCD9335_CPE_FLL_STATUS_2, 0x00 },

462

{ WCD9335_CPE_FLL_STATUS_3, 0x00 },

463

{ WCD9335_I2S_FLL_USER_CTL_0, 0x41 },

464

{ WCD9335_I2S_FLL_USER_CTL_1, 0x94 },

465

{ WCD9335_I2S_FLL_USER_CTL_2, 0x08 },

466

{ WCD9335_I2S_FLL_USER_CTL_3, 0x02 },

467

{ WCD9335_I2S_FLL_USER_CTL_4, 0x04 },

468

{ WCD9335_I2S_FLL_USER_CTL_5, 0x02 },

469

{ WCD9335_I2S_FLL_USER_CTL_6, 0x40 },

470

{ WCD9335_I2S_FLL_USER_CTL_7, 0x00 },

471

{ WCD9335_I2S_FLL_USER_CTL_8, 0x5f },

472

{ WCD9335_I2S_FLL_USER_CTL_9, 0x02 },

473

{ WCD9335_I2S_FLL_L_VAL_CTL_0, 0x40 },

474

{ WCD9335_I2S_FLL_L_VAL_CTL_1, 0x00 },

475

{ WCD9335_I2S_FLL_DSM_FRAC_CTL_0, 0x00 },

476

{ WCD9335_I2S_FLL_DSM_FRAC_CTL_1, 0xff },

477

{ WCD9335_I2S_FLL_CONFIG_CTL_0, 0x6b },

478

{ WCD9335_I2S_FLL_CONFIG_CTL_1, 0x05 },

479

{ WCD9335_I2S_FLL_CONFIG_CTL_2, 0x08 },

480

{ WCD9335_I2S_FLL_CONFIG_CTL_3, 0x00 },

481

{ WCD9335_I2S_FLL_CONFIG_CTL_4, 0x30 },

482

{ WCD9335_I2S_FLL_TEST_CTL_0, 0x80 },

483

{ WCD9335_I2S_FLL_TEST_CTL_1, 0x00 },

484

{ WCD9335_I2S_FLL_TEST_CTL_2, 0x00 },

485

{ WCD9335_I2S_FLL_TEST_CTL_3, 0x00 },

486

{ WCD9335_I2S_FLL_TEST_CTL_4, 0x00 },

487

{ WCD9335_I2S_FLL_TEST_CTL_5, 0x00 },

488

{ WCD9335_I2S_FLL_TEST_CTL_6, 0x00 },

489

{ WCD9335_I2S_FLL_TEST_CTL_7, 0xff },

490

{ WCD9335_I2S_FLL_FREQ_CTL_0, 0x00 },

491

{ WCD9335_I2S_FLL_FREQ_CTL_1, 0x00 },

492

{ WCD9335_I2S_FLL_FREQ_CTL_2, 0x00 },

493

{ WCD9335_I2S_FLL_FREQ_CTL_3, 0x00 },

494

{ WCD9335_I2S_FLL_SSC_CTL_0, 0x00 },

495

{ WCD9335_I2S_FLL_SSC_CTL_1, 0x00 },

496

{ WCD9335_I2S_FLL_SSC_CTL_2, 0x00 },

497

{ WCD9335_I2S_FLL_SSC_CTL_3, 0x00 },

498

{ WCD9335_I2S_FLL_FLL_MODE, 0x00 },

499

{ WCD9335_I2S_FLL_STATUS_0, 0x00 },

500

{ WCD9335_I2S_FLL_STATUS_1, 0x00 },

501

{ WCD9335_I2S_FLL_STATUS_2, 0x00 },

502

{ WCD9335_I2S_FLL_STATUS_3, 0x00 },

503

{ WCD9335_SB_FLL_USER_CTL_0, 0x41 },

504

{ WCD9335_SB_FLL_USER_CTL_1, 0x94 },

505

{ WCD9335_SB_FLL_USER_CTL_2, 0x08 },

506

{ WCD9335_SB_FLL_USER_CTL_3, 0x02 },

507

{ WCD9335_SB_FLL_USER_CTL_4, 0x04 },

508

{ WCD9335_SB_FLL_USER_CTL_5, 0x02 },

509

{ WCD9335_SB_FLL_USER_CTL_6, 0x40 },

510

{ WCD9335_SB_FLL_USER_CTL_7, 0x00 },

511

{ WCD9335_SB_FLL_USER_CTL_8, 0x5e },

512

{ WCD9335_SB_FLL_USER_CTL_9, 0x01 },

513

{ WCD9335_SB_FLL_L_VAL_CTL_0, 0x40 },

514

{ WCD9335_SB_FLL_L_VAL_CTL_1, 0x00 },

515

{ WCD9335_SB_FLL_DSM_FRAC_CTL_0, 0x00 },

516

{ WCD9335_SB_FLL_DSM_FRAC_CTL_1, 0xff },

517

{ WCD9335_SB_FLL_CONFIG_CTL_0, 0x6b },

518

{ WCD9335_SB_FLL_CONFIG_CTL_1, 0x05 },

519

{ WCD9335_SB_FLL_CONFIG_CTL_2, 0x08 },

520

{ WCD9335_SB_FLL_CONFIG_CTL_3, 0x00 },

521

{ WCD9335_SB_FLL_CONFIG_CTL_4, 0x10 },

522

{ WCD9335_SB_FLL_TEST_CTL_0, 0x00 },

523

{ WCD9335_SB_FLL_TEST_CTL_1, 0x00 },

524

{ WCD9335_SB_FLL_TEST_CTL_2, 0x00 },

525

{ WCD9335_SB_FLL_TEST_CTL_3, 0x00 },

526

{ WCD9335_SB_FLL_TEST_CTL_4, 0x00 },

527

{ WCD9335_SB_FLL_TEST_CTL_5, 0x00 },

528

{ WCD9335_SB_FLL_TEST_CTL_6, 0x00 },

529

{ WCD9335_SB_FLL_TEST_CTL_7, 0xff },

530

{ WCD9335_SB_FLL_FREQ_CTL_0, 0x00 },

531

{ WCD9335_SB_FLL_FREQ_CTL_1, 0x00 },

532

{ WCD9335_SB_FLL_FREQ_CTL_2, 0x00 },

533

{ WCD9335_SB_FLL_FREQ_CTL_3, 0x00 },

534

{ WCD9335_SB_FLL_SSC_CTL_0, 0x00 },

535

{ WCD9335_SB_FLL_SSC_CTL_1, 0x00 },

536

{ WCD9335_SB_FLL_SSC_CTL_2, 0x00 },

537

{ WCD9335_SB_FLL_SSC_CTL_3, 0x00 },

538

{ WCD9335_SB_FLL_FLL_MODE, 0x00 },

539

{ WCD9335_SB_FLL_STATUS_0, 0x00 },

540

{ WCD9335_SB_FLL_STATUS_1, 0x00 },

541

{ WCD9335_SB_FLL_STATUS_2, 0x00 },

542

{ WCD9335_SB_FLL_STATUS_3, 0x00 },

543

/* Page #2 registers */

544

{ WCD9335_PAGE2_PAGE_REGISTER, 0x00 },

545

{ WCD9335_CPE_SS_MEM_PTR_0, 0x00 },

546

{ WCD9335_CPE_SS_MEM_PTR_1, 0x00 },

547

{ WCD9335_CPE_SS_MEM_PTR_2, 0x00 },

548

{ WCD9335_CPE_SS_MEM_CTRL, 0x08 },

549

{ WCD9335_CPE_SS_MEM_BANK_0, 0x00 },

550

{ WCD9335_CPE_SS_MEM_BANK_1, 0x00 },

551

{ WCD9335_CPE_SS_MEM_BANK_2, 0x00 },

552

{ WCD9335_CPE_SS_MEM_BANK_3, 0x00 },

553

{ WCD9335_CPE_SS_MEM_BANK_4, 0x00 },

554

{ WCD9335_CPE_SS_MEM_BANK_5, 0x00 },

555

{ WCD9335_CPE_SS_MEM_BANK_6, 0x00 },

556

{ WCD9335_CPE_SS_MEM_BANK_7, 0x00 },

557

{ WCD9335_CPE_SS_MEM_BANK_8, 0x00 },

558

{ WCD9335_CPE_SS_MEM_BANK_9, 0x00 },

559

{ WCD9335_CPE_SS_MEM_BANK_10, 0x00 },

560

{ WCD9335_CPE_SS_MEM_BANK_11, 0x00 },

561

{ WCD9335_CPE_SS_MEM_BANK_12, 0x00 },

562

{ WCD9335_CPE_SS_MEM_BANK_13, 0x00 },

563

{ WCD9335_CPE_SS_MEM_BANK_14, 0x00 },

564

{ WCD9335_CPE_SS_MEM_BANK_15, 0x00 },

565

{ WCD9335_CPE_SS_INBOX1_TRG, 0x00 },

566

{ WCD9335_CPE_SS_INBOX2_TRG, 0x00 },

567

{ WCD9335_CPE_SS_INBOX1_0, 0x00 },

568

{ WCD9335_CPE_SS_INBOX1_1, 0x00 },

569

{ WCD9335_CPE_SS_INBOX1_2, 0x00 },

570

{ WCD9335_CPE_SS_INBOX1_3, 0x00 },

571

{ WCD9335_CPE_SS_INBOX1_4, 0x00 },

572

{ WCD9335_CPE_SS_INBOX1_5, 0x00 },

573

{ WCD9335_CPE_SS_INBOX1_6, 0x00 },

574

{ WCD9335_CPE_SS_INBOX1_7, 0x00 },

575

{ WCD9335_CPE_SS_INBOX1_8, 0x00 },

576

{ WCD9335_CPE_SS_INBOX1_9, 0x00 },

577

{ WCD9335_CPE_SS_INBOX1_10, 0x00 },

578

{ WCD9335_CPE_SS_INBOX1_11, 0x00 },

579

{ WCD9335_CPE_SS_INBOX1_12, 0x00 },

580

{ WCD9335_CPE_SS_INBOX1_13, 0x00 },

581

{ WCD9335_CPE_SS_INBOX1_14, 0x00 },

582

{ WCD9335_CPE_SS_INBOX1_15, 0x00 },

583

{ WCD9335_CPE_SS_OUTBOX1_0, 0x00 },

584

{ WCD9335_CPE_SS_OUTBOX1_1, 0x00 },

585

{ WCD9335_CPE_SS_OUTBOX1_2, 0x00 },

586

{ WCD9335_CPE_SS_OUTBOX1_3, 0x00 },

587

{ WCD9335_CPE_SS_OUTBOX1_4, 0x00 },

588

{ WCD9335_CPE_SS_OUTBOX1_5, 0x00 },

589

{ WCD9335_CPE_SS_OUTBOX1_6, 0x00 },

590

{ WCD9335_CPE_SS_OUTBOX1_7, 0x00 },

591

{ WCD9335_CPE_SS_OUTBOX1_8, 0x00 },

592

{ WCD9335_CPE_SS_OUTBOX1_9, 0x00 },

593

{ WCD9335_CPE_SS_OUTBOX1_10, 0x00 },

594

{ WCD9335_CPE_SS_OUTBOX1_11, 0x00 },

595

{ WCD9335_CPE_SS_OUTBOX1_12, 0x00 },

596

{ WCD9335_CPE_SS_OUTBOX1_13, 0x00 },

597

{ WCD9335_CPE_SS_OUTBOX1_14, 0x00 },

598

{ WCD9335_CPE_SS_OUTBOX1_15, 0x00 },

599

{ WCD9335_CPE_SS_INBOX2_0, 0x00 },

600

{ WCD9335_CPE_SS_INBOX2_1, 0x00 },

601

{ WCD9335_CPE_SS_INBOX2_2, 0x00 },

602

{ WCD9335_CPE_SS_INBOX2_3, 0x00 },

603

{ WCD9335_CPE_SS_INBOX2_4, 0x00 },

604

{ WCD9335_CPE_SS_INBOX2_5, 0x00 },

605

{ WCD9335_CPE_SS_INBOX2_6, 0x00 },

606

{ WCD9335_CPE_SS_INBOX2_7, 0x00 },

607

{ WCD9335_CPE_SS_INBOX2_8, 0x00 },

608

{ WCD9335_CPE_SS_INBOX2_9, 0x00 },

609

{ WCD9335_CPE_SS_INBOX2_10, 0x00 },

610

{ WCD9335_CPE_SS_INBOX2_11, 0x00 },

611

{ WCD9335_CPE_SS_INBOX2_12, 0x00 },

612

{ WCD9335_CPE_SS_INBOX2_13, 0x00 },

613

{ WCD9335_CPE_SS_INBOX2_14, 0x00 },

614

{ WCD9335_CPE_SS_INBOX2_15, 0x00 },

615

{ WCD9335_CPE_SS_OUTBOX2_0, 0x00 },

616

{ WCD9335_CPE_SS_OUTBOX2_1, 0x00 },

617

{ WCD9335_CPE_SS_OUTBOX2_2, 0x00 },

618

{ WCD9335_CPE_SS_OUTBOX2_3, 0x00 },

619

{ WCD9335_CPE_SS_OUTBOX2_4, 0x00 },

620

{ WCD9335_CPE_SS_OUTBOX2_5, 0x00 },

621

{ WCD9335_CPE_SS_OUTBOX2_6, 0x00 },

622

{ WCD9335_CPE_SS_OUTBOX2_7, 0x00 },

623

{ WCD9335_CPE_SS_OUTBOX2_8, 0x00 },

624

{ WCD9335_CPE_SS_OUTBOX2_9, 0x00 },

625

{ WCD9335_CPE_SS_OUTBOX2_10, 0x00 },

626

{ WCD9335_CPE_SS_OUTBOX2_11, 0x00 },

627

{ WCD9335_CPE_SS_OUTBOX2_12, 0x00 },

628

{ WCD9335_CPE_SS_OUTBOX2_13, 0x00 },

629

{ WCD9335_CPE_SS_OUTBOX2_14, 0x00 },

630

{ WCD9335_CPE_SS_OUTBOX2_15, 0x00 },

631

{ WCD9335_CPE_SS_OUTBOX1_ACK, 0x00 },

632

{ WCD9335_CPE_SS_OUTBOX2_ACK, 0x00 },

633

{ WCD9335_CPE_SS_EC_BUF_INT_PERIOD, 0x3c },

634

{ WCD9335_CPE_SS_US_BUF_INT_PERIOD, 0x60 },

635

{ WCD9335_CPE_SS_CFG, 0x41 },

636

{ WCD9335_CPE_SS_US_EC_MUX_CFG, 0x00 },

637

{ WCD9335_CPE_SS_MAD_CTL, 0x00 },

638

{ WCD9335_CPE_SS_CPAR_CTL, 0x00 },

639

{ WCD9335_CPE_SS_DMIC0_CTL, 0x00 },

640

{ WCD9335_CPE_SS_DMIC1_CTL, 0x00 },

641

{ WCD9335_CPE_SS_DMIC2_CTL, 0x00 },

642

{ WCD9335_CPE_SS_DMIC_CFG, 0x80 },

643

{ WCD9335_CPE_SS_CPAR_CFG, 0x00 },

644

{ WCD9335_CPE_SS_WDOG_CFG, 0x01 },

645

{ WCD9335_CPE_SS_BACKUP_INT, 0x00 },

646

{ WCD9335_CPE_SS_STATUS, 0x00 },

647

{ WCD9335_CPE_SS_CPE_OCD_CFG, 0x00 },

648

{ WCD9335_CPE_SS_SS_ERROR_INT_STATUS, 0x00 },

649

{ WCD9335_CPE_SS_SS_ERROR_INT_CLEAR, 0x00 },

650

{ WCD9335_SOC_MAD_MAIN_CTL_1, 0x00 },

651

{ WCD9335_SOC_MAD_MAIN_CTL_2, 0x00 },

652

{ WCD9335_SOC_MAD_AUDIO_CTL_1, 0x00 },

653

{ WCD9335_SOC_MAD_AUDIO_CTL_2, 0x00 },

654

{ WCD9335_SOC_MAD_AUDIO_CTL_3, 0x00 },

655

{ WCD9335_SOC_MAD_AUDIO_CTL_4, 0x00 },

656

{ WCD9335_SOC_MAD_AUDIO_CTL_5, 0x00 },

657

{ WCD9335_SOC_MAD_AUDIO_CTL_6, 0x00 },

658

{ WCD9335_SOC_MAD_AUDIO_CTL_7, 0x00 },

659

{ WCD9335_SOC_MAD_AUDIO_CTL_8, 0x00 },

660

{ WCD9335_SOC_MAD_AUDIO_IIR_CTL_PTR, 0x00 },

661

{ WCD9335_SOC_MAD_ULTR_CTL_1, 0x00 },

662

{ WCD9335_SOC_MAD_ULTR_CTL_2, 0x00 },

663

{ WCD9335_SOC_MAD_ULTR_CTL_3, 0x00 },

664

{ WCD9335_SOC_MAD_ULTR_CTL_4, 0x00 },

665

{ WCD9335_SOC_MAD_ULTR_CTL_5, 0x00 },

666

{ WCD9335_SOC_MAD_ULTR_CTL_6, 0x00 },

667

{ WCD9335_SOC_MAD_ULTR_CTL_7, 0x00 },

668

{ WCD9335_SOC_MAD_BEACON_CTL_1, 0x00 },

669

{ WCD9335_SOC_MAD_BEACON_CTL_2, 0x00 },

670

{ WCD9335_SOC_MAD_BEACON_CTL_3, 0x00 },

671

{ WCD9335_SOC_MAD_BEACON_CTL_4, 0x00 },

672

{ WCD9335_SOC_MAD_BEACON_CTL_5, 0x00 },

673

{ WCD9335_SOC_MAD_BEACON_CTL_6, 0x00 },

674

{ WCD9335_SOC_MAD_BEACON_CTL_7, 0x00 },

675

{ WCD9335_SOC_MAD_BEACON_CTL_8, 0x00 },

676

{ WCD9335_SOC_MAD_BEACON_IIR_CTL_PTR, 0x00 },

677

{ WCD9335_SOC_MAD_BEACON_IIR_CTL_VAL, 0x00 },

678

{ WCD9335_SOC_MAD_INP_SEL, 0x00 },

679

/* Page #6 registers */

680

{ WCD9335_PAGE6_PAGE_REGISTER, 0x00 },

681

{ WCD9335_ANA_BIAS, 0x00 },

682

{ WCD9335_ANA_CLK_TOP, 0x00 },

683

{ WCD9335_ANA_RCO, 0x30 },

684

{ WCD9335_ANA_BUCK_VOUT_A, 0xb4 },

685

{ WCD9335_ANA_BUCK_VOUT_D, 0xb4 },

686

{ WCD9335_ANA_BUCK_CTL, 0x00 },

687

{ WCD9335_ANA_BUCK_STATUS, 0xe0 },

688

{ WCD9335_ANA_RX_SUPPLIES, 0x00 },

689

{ WCD9335_ANA_HPH, 0x00 },

690

{ WCD9335_ANA_EAR, 0x00 },

691

{ WCD9335_ANA_LO_1_2, 0x00 },

692

{ WCD9335_ANA_LO_3_4, 0x00 },

693

{ WCD9335_ANA_MAD_SETUP, 0x81 },

694

{ WCD9335_ANA_AMIC1, 0x20 },

695

{ WCD9335_ANA_AMIC2, 0x00 },

696

{ WCD9335_ANA_AMIC3, 0x20 },

697

{ WCD9335_ANA_AMIC4, 0x00 },

698

{ WCD9335_ANA_AMIC5, 0x20 },

699

{ WCD9335_ANA_AMIC6, 0x00 },

700

{ WCD9335_ANA_MBHC_MECH, 0x39 },

701

{ WCD9335_ANA_MBHC_ELECT, 0x08 },

702

{ WCD9335_ANA_MBHC_ZDET, 0x00 },

703

{ WCD9335_ANA_MBHC_RESULT_1, 0x00 },

704

{ WCD9335_ANA_MBHC_RESULT_2, 0x00 },

705

{ WCD9335_ANA_MBHC_RESULT_3, 0x00 },

706

{ WCD9335_ANA_MBHC_BTN0, 0x00 },

707

{ WCD9335_ANA_MBHC_BTN1, 0x10 },

708

{ WCD9335_ANA_MBHC_BTN2, 0x20 },

709

{ WCD9335_ANA_MBHC_BTN3, 0x30 },

710

{ WCD9335_ANA_MBHC_BTN4, 0x40 },

711

{ WCD9335_ANA_MBHC_BTN5, 0x50 },

712

{ WCD9335_ANA_MBHC_BTN6, 0x60 },

713

{ WCD9335_ANA_MBHC_BTN7, 0x70 },

714

{ WCD9335_ANA_MICB1, 0x10 },

715

{ WCD9335_ANA_MICB2, 0x10 },

716

{ WCD9335_ANA_MICB2_RAMP, 0x00 },

717

{ WCD9335_ANA_MICB3, 0x10 },

718

{ WCD9335_ANA_MICB4, 0x10 },

719

{ WCD9335_ANA_VBADC, 0x00 },

720

{ WCD9335_BIAS_CTL, 0x28 },

721

{ WCD9335_CLOCK_TEST_CTL, 0x00 },

722

{ WCD9335_RCO_CTRL_1, 0x44 },

723

{ WCD9335_RCO_CTRL_2, 0x44 },

724

{ WCD9335_RCO_CAL, 0x00 },

725

{ WCD9335_RCO_CAL_1, 0x00 },

726

{ WCD9335_RCO_CAL_2, 0x00 },

727

{ WCD9335_RCO_TEST_CTRL, 0x00 },

728

{ WCD9335_RCO_CAL_OUT_1, 0x00 },

729

{ WCD9335_RCO_CAL_OUT_2, 0x00 },

730

{ WCD9335_RCO_CAL_OUT_3, 0x00 },

731

{ WCD9335_RCO_CAL_OUT_4, 0x00 },

732

{ WCD9335_RCO_CAL_OUT_5, 0x00 },

733

{ WCD9335_SIDO_SIDO_MODE_1, 0x84 },

734

{ WCD9335_SIDO_SIDO_MODE_2, 0xfe },

735

{ WCD9335_SIDO_SIDO_MODE_3, 0xf6 },

736

{ WCD9335_SIDO_SIDO_MODE_4, 0x56 },

737

{ WCD9335_SIDO_SIDO_VCL_1, 0x00 },

738

{ WCD9335_SIDO_SIDO_VCL_2, 0x6c },

739

{ WCD9335_SIDO_SIDO_VCL_3, 0x44 },

740

{ WCD9335_SIDO_SIDO_CCL_1, 0x57 },

741

{ WCD9335_SIDO_SIDO_CCL_4, 0x61 },

742

{ WCD9335_SIDO_SIDO_CCL_5, 0x6d },

743

{ WCD9335_SIDO_SIDO_CCL_6, 0x60 },

744

{ WCD9335_SIDO_SIDO_CCL_7, 0x6f },

745

{ WCD9335_SIDO_SIDO_CCL_9, 0x6e },

746

{ WCD9335_SIDO_SIDO_FILTER_1, 0x92 },

747

{ WCD9335_SIDO_SIDO_FILTER_2, 0x54 },

748

{ WCD9335_SIDO_SIDO_DRIVER_1, 0x77 },

749

{ WCD9335_SIDO_SIDO_CAL_CODE_EXT_1, 0x9c },

750

{ WCD9335_SIDO_SIDO_CAL_CODE_EXT_2, 0x82 },

751

{ WCD9335_SIDO_SIDO_CAL_CODE_OUT_1, 0x00 },

752

{ WCD9335_SIDO_SIDO_CAL_CODE_OUT_2, 0x00 },

753

{ WCD9335_SIDO_SIDO_TEST_1, 0x00 },

754

{ WCD9335_MBHC_CTL_1, 0x32 },

755

{ WCD9335_MBHC_CTL_2, 0x01 },

756

{ WCD9335_MBHC_PLUG_DETECT_CTL, 0x69 },

757

{ WCD9335_MBHC_ZDET_RAMP_CTL, 0x00 },

758

{ WCD9335_MBHC_TEST_CTL, 0x00 },

759

{ WCD9335_VBADC_SUBBLOCK_EN, 0xfe },

760

{ WCD9335_VBADC_IBIAS_FE, 0x54 },

761

{ WCD9335_VBADC_BIAS_ADC, 0x51 },

762

{ WCD9335_VBADC_FE_CTRL, 0x1c },

763

{ WCD9335_VBADC_ADC_REF, 0x20 },

764

{ WCD9335_VBADC_ADC_IO, 0x80 },

765

{ WCD9335_VBADC_ADC_SAR, 0xff },

766

{ WCD9335_VBADC_DEBUG, 0x00 },

767

{ WCD9335_VBADC_ADC_DOUTMSB, 0x00 },

768

{ WCD9335_VBADC_ADC_DOUTLSB, 0x00 },

769

{ WCD9335_LDOH_MODE, 0x2b },

770

{ WCD9335_LDOH_BIAS, 0x68 },

771

{ WCD9335_LDOH_STB_LOADS, 0x00 },

772

{ WCD9335_LDOH_SLOWRAMP, 0x50 },

773

{ WCD9335_MICB1_TEST_CTL_1, 0x1a },

774

{ WCD9335_MICB1_TEST_CTL_2, 0x18 },

775

{ WCD9335_MICB1_TEST_CTL_3, 0xa4 },

776

{ WCD9335_MICB2_TEST_CTL_1, 0x1a },

777

{ WCD9335_MICB2_TEST_CTL_2, 0x18 },

778

{ WCD9335_MICB2_TEST_CTL_3, 0x24 },

779

{ WCD9335_MICB3_TEST_CTL_1, 0x1a },

780

{ WCD9335_MICB3_TEST_CTL_2, 0x18 },

781

{ WCD9335_MICB3_TEST_CTL_3, 0xa4 },

782

{ WCD9335_MICB4_TEST_CTL_1, 0x1a },

783

{ WCD9335_MICB4_TEST_CTL_2, 0x18 },

784

{ WCD9335_MICB4_TEST_CTL_3, 0xa4 },

785

{ WCD9335_TX_COM_ADC_VCM, 0x39 },

786

{ WCD9335_TX_COM_BIAS_ATEST, 0xc0 },

787

{ WCD9335_TX_COM_ADC_INT1_IB, 0x6f },

788

{ WCD9335_TX_COM_ADC_INT2_IB, 0x4f },

789

{ WCD9335_TX_COM_TXFE_DIV_CTL, 0x2e },

790

{ WCD9335_TX_COM_TXFE_DIV_START, 0x00 },

791

{ WCD9335_TX_COM_TXFE_DIV_STOP_9P6M, 0xc7 },

792

{ WCD9335_TX_COM_TXFE_DIV_STOP_12P288M, 0xff },

793

{ WCD9335_TX_1_2_TEST_EN, 0xcc },

794

{ WCD9335_TX_1_2_ADC_IB, 0x09 },

795

{ WCD9335_TX_1_2_TEST_CTL, 0x38 },

796

{ WCD9335_TX_1_2_TEST_BLK_EN, 0xff },

797

{ WCD9335_TX_1_2_TXFE_CLKDIV, 0x00 },

798

{ WCD9335_TX_1_2_SAR1_ERR, 0x00 },

799

{ WCD9335_TX_1_2_SAR2_ERR, 0x00 },

800

{ WCD9335_TX_3_4_TEST_EN, 0xcc },

801

{ WCD9335_TX_3_4_ADC_IB, 0x09 },

802

{ WCD9335_TX_3_4_TEST_CTL, 0x38 },

803

{ WCD9335_TX_3_4_TEST_BLK_EN, 0xff },

804

{ WCD9335_TX_3_4_TXFE_CLKDIV, 0x00 },

805

{ WCD9335_TX_3_4_SAR1_ERR, 0x00 },

806

{ WCD9335_TX_3_4_SAR2_ERR, 0x00 },

807

{ WCD9335_TX_5_6_TEST_EN, 0xcc },

808

{ WCD9335_TX_5_6_ADC_IB, 0x09 },

809

{ WCD9335_TX_5_6_TEST_CTL, 0x38 },

810

{ WCD9335_TX_5_6_TEST_BLK_EN, 0xff },

811

{ WCD9335_TX_5_6_TXFE_CLKDIV, 0x00 },

812

{ WCD9335_TX_5_6_SAR1_ERR, 0x00 },

813

{ WCD9335_TX_5_6_SAR2_ERR, 0x00 },

814

{ WCD9335_CLASSH_MODE_1, 0x40 },

815

{ WCD9335_CLASSH_MODE_2, 0x3a },

816

{ WCD9335_CLASSH_MODE_3, 0x00 },

817

{ WCD9335_CLASSH_CTRL_VCL_1, 0x70 },

818

{ WCD9335_CLASSH_CTRL_VCL_2, 0xa2 },

819

{ WCD9335_CLASSH_CTRL_CCL_1, 0x51 },

820

{ WCD9335_CLASSH_CTRL_CCL_2, 0x80 },

821

{ WCD9335_CLASSH_CTRL_CCL_3, 0x80 },

822

{ WCD9335_CLASSH_CTRL_CCL_4, 0x51 },

823

{ WCD9335_CLASSH_CTRL_CCL_5, 0x00 },

824

{ WCD9335_CLASSH_BUCK_TMUX_A_D, 0x00 },

825

{ WCD9335_CLASSH_BUCK_SW_DRV_CNTL, 0x77 },

826

{ WCD9335_CLASSH_SPARE, 0x00 },

827

{ WCD9335_FLYBACK_EN, 0x4e },

828

{ WCD9335_FLYBACK_VNEG_CTRL_2, 0x45 },

829

{ WCD9335_FLYBACK_VNEG_CTRL_3, 0x74 },

830

{ WCD9335_FLYBACK_VNEG_CTRL_5, 0x83 },

831

{ WCD9335_FLYBACK_VNEG_CTRL_6, 0x98 },

832

{ WCD9335_FLYBACK_VNEG_CTRL_7, 0xa9 },

833

{ WCD9335_FLYBACK_VNEG_CTRL_8, 0x68 },

834

{ WCD9335_FLYBACK_VNEG_DAC_CTRL_2, 0x50 },

835

{ WCD9335_FLYBACK_VNEG_DAC_CTRL_3, 0xa6 },

836

{ WCD9335_FLYBACK_TEST_CTL, 0x00 },

837

{ WCD9335_RX_AUX_SW_CTL, 0x00 },

838

{ WCD9335_RX_PA_AUX_IN_CONN, 0x00 },

839

{ WCD9335_RX_TIMER_DIV, 0x74 },

840

{ WCD9335_RX_OCP_CTL, 0x1f },

841

{ WCD9335_RX_OCP_COUNT, 0x77 },

842

{ WCD9335_RX_BIAS_EAR_DAC, 0xa0 },

843

{ WCD9335_RX_BIAS_EAR_AMP, 0xaa },

844

{ WCD9335_RX_BIAS_HPH_LDO, 0xa9 },

845

{ WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8a },

846

{ WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x88 },

847

{ WCD9335_RX_BIAS_HPH_CNP1, 0x86 },

848

{ WCD9335_RX_BIAS_DIFFLO_PA, 0x80 },

849

{ WCD9335_RX_BIAS_DIFFLO_REF, 0x88 },

850

{ WCD9335_RX_BIAS_DIFFLO_LDO, 0x88 },

851

{ WCD9335_RX_BIAS_SELO_DAC_PA, 0xa8 },

852

{ WCD9335_RX_BIAS_BUCK_RST, 0x08 },

853

{ WCD9335_RX_BIAS_BUCK_VREF_ERRAMP, 0x44 },

854

{ WCD9335_RX_BIAS_FLYB_ERRAMP, 0x40 },

855

{ WCD9335_RX_BIAS_FLYB_BUFF, 0xaa },

856

{ WCD9335_RX_BIAS_FLYB_MID_RST, 0x44 },

857

{ WCD9335_HPH_L_STATUS, 0x04 },

858

{ WCD9335_HPH_R_STATUS, 0x04 },

859

{ WCD9335_HPH_CNP_EN, 0x80 },

860

{ WCD9335_HPH_CNP_WG_CTL, 0xda },

861

{ WCD9335_HPH_CNP_WG_TIME, 0x15 },

862

{ WCD9335_HPH_OCP_CTL, 0x28 },

863

{ WCD9335_HPH_AUTO_CHOP, 0x12 },

864

{ WCD9335_HPH_CHOP_CTL, 0x83 },

865

{ WCD9335_HPH_PA_CTL1, 0x46 },

866

{ WCD9335_HPH_L_TEST, 0x00 },

867

{ WCD9335_HPH_L_ATEST, 0x50 },

868

{ WCD9335_HPH_R_TEST, 0x00 },

869

{ WCD9335_HPH_RDAC_CLK_CTL1, 0x99 },

870

{ WCD9335_HPH_RDAC_CLK_CTL2, 0x9b },

871

{ WCD9335_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00 },

872

{ WCD9335_HPH_REFBUFF_UHQA_CTL, 0xa8 },

873

{ WCD9335_HPH_REFBUFF_LP_CTL, 0x00 },

874

{ WCD9335_HPH_L_DAC_CTL, 0x00 },

875

{ WCD9335_HPH_R_DAC_CTL, 0x00 },

876

{ WCD9335_EAR_EN_REG, 0x60 },

877

{ WCD9335_EAR_CMBUFF, 0x0d },

878

{ WCD9335_EAR_ICTL, 0x40 },

879

{ WCD9335_EAR_EN_DBG_CTL, 0x00 },

880

{ WCD9335_EAR_CNP, 0xe0 },

881

{ WCD9335_EAR_DAC_CTL_ATEST, 0x00 },

882

{ WCD9335_EAR_STATUS_REG, 0x04 },

883

{ WCD9335_EAR_OUT_SHORT, 0x00 },

884

{ WCD9335_DIFF_LO_MISC, 0x03 },

885

{ WCD9335_DIFF_LO_LO2_COMPANDER, 0x00 },

886

{ WCD9335_DIFF_LO_LO1_COMPANDER, 0x00 },

887

{ WCD9335_DIFF_LO_COMMON, 0x40 },

888

{ WCD9335_DIFF_LO_BYPASS_EN, 0x00 },

889

{ WCD9335_DIFF_LO_CNP, 0x20 },

890

{ WCD9335_DIFF_LO_CORE_OUT_PROG, 0x00 },

891

{ WCD9335_DIFF_LO_LDO_OUT_PROG, 0x00 },

892

{ WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x9b },

893

{ WCD9335_DIFF_LO_COM_PA_FREQ, 0xb0 },

894

{ WCD9335_DIFF_LO_RESERVED_REG, 0x60 },

895

{ WCD9335_DIFF_LO_LO1_STATUS_1, 0x00 },

896

{ WCD9335_DIFF_LO_LO1_STATUS_2, 0x00 },

897

{ WCD9335_SE_LO_COM1, 0x80 },

898

{ WCD9335_SE_LO_COM2, 0x04 },

899

{ WCD9335_SE_LO_LO3_GAIN, 0x20 },

900

{ WCD9335_SE_LO_LO3_CTRL, 0x04 },

901

{ WCD9335_SE_LO_LO4_GAIN, 0x20 },

902

{ WCD9335_SE_LO_LO4_CTRL, 0x04 },

903

{ WCD9335_SE_LO_LO3_STATUS, 0x00 },

904

{ WCD9335_SE_LO_LO4_STATUS, 0x00 },

905

/* Page #10 registers */

906

{ WCD9335_PAGE10_PAGE_REGISTER, 0x00 },

907

{ WCD9335_CDC_ANC0_CLK_RESET_CTL, 0x00 },

908

{ WCD9335_CDC_ANC0_MODE_1_CTL, 0x00 },

909

{ WCD9335_CDC_ANC0_MODE_2_CTL, 0x00 },

910

{ WCD9335_CDC_ANC0_FF_SHIFT, 0x00 },

911

{ WCD9335_CDC_ANC0_FB_SHIFT, 0x00 },

912

{ WCD9335_CDC_ANC0_LPF_FF_A_CTL, 0x00 },

913

{ WCD9335_CDC_ANC0_LPF_FF_B_CTL, 0x00 },

914

{ WCD9335_CDC_ANC0_LPF_FB_CTL, 0x00 },

915

{ WCD9335_CDC_ANC0_SMLPF_CTL, 0x00 },

916

{ WCD9335_CDC_ANC0_DCFLT_SHIFT_CTL, 0x00 },

917

{ WCD9335_CDC_ANC0_IIR_ADAPT_CTL, 0x00 },

918

{ WCD9335_CDC_ANC0_IIR_COEFF_1_CTL, 0x00 },

919

{ WCD9335_CDC_ANC0_IIR_COEFF_2_CTL, 0x00 },

920

{ WCD9335_CDC_ANC0_FF_A_GAIN_CTL, 0x00 },

921

{ WCD9335_CDC_ANC0_FF_B_GAIN_CTL, 0x00 },

922

{ WCD9335_CDC_ANC0_FB_GAIN_CTL, 0x00 },

923

{ WCD9335_CDC_ANC1_CLK_RESET_CTL, 0x00 },

924

{ WCD9335_CDC_ANC1_MODE_1_CTL, 0x00 },

925

{ WCD9335_CDC_ANC1_MODE_2_CTL, 0x00 },

926

{ WCD9335_CDC_ANC1_FF_SHIFT, 0x00 },

927

{ WCD9335_CDC_ANC1_FB_SHIFT, 0x00 },

928

{ WCD9335_CDC_ANC1_LPF_FF_A_CTL, 0x00 },

929

{ WCD9335_CDC_ANC1_LPF_FF_B_CTL, 0x00 },

930

{ WCD9335_CDC_ANC1_LPF_FB_CTL, 0x00 },

931

{ WCD9335_CDC_ANC1_SMLPF_CTL, 0x00 },

932

{ WCD9335_CDC_ANC1_DCFLT_SHIFT_CTL, 0x00 },

933

{ WCD9335_CDC_ANC1_IIR_ADAPT_CTL, 0x00 },

934

{ WCD9335_CDC_ANC1_IIR_COEFF_1_CTL, 0x00 },

935

{ WCD9335_CDC_ANC1_IIR_COEFF_2_CTL, 0x00 },

936

{ WCD9335_CDC_ANC1_FF_A_GAIN_CTL, 0x00 },

937

{ WCD9335_CDC_ANC1_FF_B_GAIN_CTL, 0x00 },

938

{ WCD9335_CDC_ANC1_FB_GAIN_CTL, 0x00 },

939

{ WCD9335_CDC_TX0_TX_PATH_CTL, 0x04 },

940

{ WCD9335_CDC_TX0_TX_VOL_CTL, 0x00 },

941

{ WCD9335_CDC_TX0_TX_PATH_192_CTL, 0x00 },

942

{ WCD9335_CDC_TX0_TX_PATH_192_CFG, 0x00 },

943

{ WCD9335_CDC_TX0_TX_PATH_SEC0, 0x00 },

944

{ WCD9335_CDC_TX0_TX_PATH_SEC1, 0x00 },

945

{ WCD9335_CDC_TX0_TX_PATH_SEC4, 0x20 },

946

{ WCD9335_CDC_TX0_TX_PATH_SEC5, 0x00 },

947

{ WCD9335_CDC_TX0_TX_PATH_SEC6, 0x00 },

948

{ WCD9335_CDC_TX1_TX_PATH_CTL, 0x04 },

949

{ WCD9335_CDC_TX1_TX_VOL_CTL, 0x00 },

950

{ WCD9335_CDC_TX1_TX_PATH_192_CTL, 0x00 },

951

{ WCD9335_CDC_TX1_TX_PATH_192_CFG, 0x00 },

952

{ WCD9335_CDC_TX1_TX_PATH_SEC0, 0x00 },

953

{ WCD9335_CDC_TX1_TX_PATH_SEC1, 0x00 },

954

{ WCD9335_CDC_TX1_TX_PATH_SEC4, 0x20 },

955

{ WCD9335_CDC_TX1_TX_PATH_SEC5, 0x00 },

956

{ WCD9335_CDC_TX1_TX_PATH_SEC6, 0x00 },

957

{ WCD9335_CDC_TX2_TX_PATH_CTL, 0x04 },

958

{ WCD9335_CDC_TX2_TX_VOL_CTL, 0x00 },

959

{ WCD9335_CDC_TX2_TX_PATH_192_CTL, 0x00 },

960

{ WCD9335_CDC_TX2_TX_PATH_192_CFG, 0x00 },

961

{ WCD9335_CDC_TX2_TX_PATH_SEC0, 0x00 },

962

{ WCD9335_CDC_TX2_TX_PATH_SEC1, 0x00 },

963

{ WCD9335_CDC_TX2_TX_PATH_SEC4, 0x20 },

964

{ WCD9335_CDC_TX2_TX_PATH_SEC5, 0x00 },

965

{ WCD9335_CDC_TX2_TX_PATH_SEC6, 0x00 },

966

{ WCD9335_CDC_TX3_TX_PATH_CTL, 0x04 },

967

{ WCD9335_CDC_TX3_TX_VOL_CTL, 0x00 },

968

{ WCD9335_CDC_TX3_TX_PATH_192_CTL, 0x00 },

969

{ WCD9335_CDC_TX3_TX_PATH_192_CFG, 0x00 },

970

{ WCD9335_CDC_TX3_TX_PATH_SEC0, 0x00 },

971

{ WCD9335_CDC_TX3_TX_PATH_SEC1, 0x00 },

972

{ WCD9335_CDC_TX3_TX_PATH_SEC4, 0x20 },

973

{ WCD9335_CDC_TX3_TX_PATH_SEC5, 0x00 },

974

{ WCD9335_CDC_TX3_TX_PATH_SEC6, 0x00 },

975

{ WCD9335_CDC_TX4_TX_PATH_CTL, 0x04 },

976

{ WCD9335_CDC_TX4_TX_VOL_CTL, 0x00 },

977

{ WCD9335_CDC_TX4_TX_PATH_192_CTL, 0x00 },

978

{ WCD9335_CDC_TX4_TX_PATH_192_CFG, 0x00 },

979

{ WCD9335_CDC_TX4_TX_PATH_SEC0, 0x00 },

980

{ WCD9335_CDC_TX4_TX_PATH_SEC1, 0x00 },

981

{ WCD9335_CDC_TX4_TX_PATH_SEC4, 0x20 },

982

{ WCD9335_CDC_TX4_TX_PATH_SEC5, 0x00 },

983

{ WCD9335_CDC_TX4_TX_PATH_SEC6, 0x00 },

984

{ WCD9335_CDC_TX5_TX_PATH_CTL, 0x04 },

985

{ WCD9335_CDC_TX5_TX_VOL_CTL, 0x00 },

986

{ WCD9335_CDC_TX5_TX_PATH_192_CTL, 0x00 },

987

{ WCD9335_CDC_TX5_TX_PATH_192_CFG, 0x00 },

988

{ WCD9335_CDC_TX5_TX_PATH_SEC0, 0x00 },

989

{ WCD9335_CDC_TX5_TX_PATH_SEC1, 0x00 },

990

{ WCD9335_CDC_TX5_TX_PATH_SEC4, 0x20 },

991

{ WCD9335_CDC_TX5_TX_PATH_SEC5, 0x00 },

992

{ WCD9335_CDC_TX5_TX_PATH_SEC6, 0x00 },

993

{ WCD9335_CDC_TX6_TX_PATH_CTL, 0x04 },

994

{ WCD9335_CDC_TX6_TX_VOL_CTL, 0x00 },

995

{ WCD9335_CDC_TX6_TX_PATH_192_CTL, 0x00 },

996

{ WCD9335_CDC_TX6_TX_PATH_192_CFG, 0x00 },

997

{ WCD9335_CDC_TX6_TX_PATH_SEC0, 0x00 },

998

{ WCD9335_CDC_TX6_TX_PATH_SEC1, 0x00 },

999

{ WCD9335_CDC_TX6_TX_PATH_SEC4, 0x20 },

1000

{ WCD9335_CDC_TX6_TX_PATH_SEC5, 0x00 },

1001

{ WCD9335_CDC_TX6_TX_PATH_SEC6, 0x00 },

1002

{ WCD9335_CDC_TX7_TX_PATH_CTL, 0x04 },

1003

{ WCD9335_CDC_TX7_TX_VOL_CTL, 0x00 },

1004

{ WCD9335_CDC_TX7_TX_PATH_192_CTL, 0x00 },

1005

{ WCD9335_CDC_TX7_TX_PATH_192_CFG, 0x00 },

1006

{ WCD9335_CDC_TX7_TX_PATH_SEC0, 0x00 },

1007

{ WCD9335_CDC_TX7_TX_PATH_SEC1, 0x00 },

1008

{ WCD9335_CDC_TX7_TX_PATH_SEC4, 0x20 },

1009

{ WCD9335_CDC_TX7_TX_PATH_SEC5, 0x00 },

1010

{ WCD9335_CDC_TX7_TX_PATH_SEC6, 0x00 },

1011

{ WCD9335_CDC_TX8_TX_PATH_CTL, 0x04 },

1012

{ WCD9335_CDC_TX8_TX_VOL_CTL, 0x00 },

1013

{ WCD9335_CDC_TX8_TX_PATH_192_CTL, 0x00 },

1014

{ WCD9335_CDC_TX8_TX_PATH_192_CFG, 0x00 },

1015

{ WCD9335_CDC_TX8_TX_PATH_SEC0, 0x00 },

1016

{ WCD9335_CDC_TX8_TX_PATH_SEC1, 0x00 },

1017

{ WCD9335_CDC_TX8_TX_PATH_SEC4, 0x20 },

1018

{ WCD9335_CDC_TX8_TX_PATH_SEC5, 0x00 },

1019

{ WCD9335_CDC_TX8_TX_PATH_SEC6, 0x00 },

1020

{ WCD9335_CDC_TX9_SPKR_PROT_PATH_CTL, 0x02 },

1021

{ WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x00 },

1022

{ WCD9335_CDC_TX10_SPKR_PROT_PATH_CTL, 0x02 },

1023

{ WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x00 },

1024

{ WCD9335_CDC_TX11_SPKR_PROT_PATH_CTL, 0x02 },

1025

{ WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x00 },

1026

{ WCD9335_CDC_TX12_SPKR_PROT_PATH_CTL, 0x02 },

1027

{ WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x00 },

1028

/* Page #11 registers */

1029

{ WCD9335_PAGE11_PAGE_REGISTER, 0x00 },

1030

{ WCD9335_CDC_COMPANDER1_CTL0, 0x60 },

1031

{ WCD9335_CDC_COMPANDER1_CTL1, 0xdb },

1032

{ WCD9335_CDC_COMPANDER1_CTL2, 0xff },

1033

{ WCD9335_CDC_COMPANDER1_CTL3, 0x35 },

1034

{ WCD9335_CDC_COMPANDER1_CTL4, 0xff },

1035

{ WCD9335_CDC_COMPANDER1_CTL5, 0x00 },

1036

{ WCD9335_CDC_COMPANDER1_CTL6, 0x01 },

1037

{ WCD9335_CDC_COMPANDER2_CTL0, 0x60 },

1038

{ WCD9335_CDC_COMPANDER2_CTL1, 0xdb },

1039

{ WCD9335_CDC_COMPANDER2_CTL2, 0xff },

1040

{ WCD9335_CDC_COMPANDER2_CTL3, 0x35 },

1041

{ WCD9335_CDC_COMPANDER2_CTL4, 0xff },

1042

{ WCD9335_CDC_COMPANDER2_CTL5, 0x00 },

1043

{ WCD9335_CDC_COMPANDER2_CTL6, 0x01 },

1044

{ WCD9335_CDC_COMPANDER3_CTL0, 0x60 },

1045

{ WCD9335_CDC_COMPANDER3_CTL1, 0xdb },

1046

{ WCD9335_CDC_COMPANDER3_CTL2, 0xff },

1047

{ WCD9335_CDC_COMPANDER3_CTL3, 0x35 },

1048

{ WCD9335_CDC_COMPANDER3_CTL4, 0xff },

1049

{ WCD9335_CDC_COMPANDER3_CTL5, 0x00 },

1050

{ WCD9335_CDC_COMPANDER3_CTL6, 0x01 },

1051

{ WCD9335_CDC_COMPANDER4_CTL0, 0x60 },

1052

{ WCD9335_CDC_COMPANDER4_CTL1, 0xdb },

1053

{ WCD9335_CDC_COMPANDER4_CTL2, 0xff },

1054

{ WCD9335_CDC_COMPANDER4_CTL3, 0x35 },

1055

{ WCD9335_CDC_COMPANDER4_CTL4, 0xff },

1056

{ WCD9335_CDC_COMPANDER4_CTL5, 0x00 },

1057

{ WCD9335_CDC_COMPANDER4_CTL6, 0x01 },

1058

{ WCD9335_CDC_COMPANDER5_CTL0, 0x60 },

1059

{ WCD9335_CDC_COMPANDER5_CTL1, 0xdb },

1060

{ WCD9335_CDC_COMPANDER5_CTL2, 0xff },

1061

{ WCD9335_CDC_COMPANDER5_CTL3, 0x35 },

1062

{ WCD9335_CDC_COMPANDER5_CTL4, 0xff },

1063

{ WCD9335_CDC_COMPANDER5_CTL5, 0x00 },

1064

{ WCD9335_CDC_COMPANDER5_CTL6, 0x01 },

1065

{ WCD9335_CDC_COMPANDER6_CTL0, 0x60 },

1066

{ WCD9335_CDC_COMPANDER6_CTL1, 0xdb },

1067

{ WCD9335_CDC_COMPANDER6_CTL2, 0xff },

1068

{ WCD9335_CDC_COMPANDER6_CTL3, 0x35 },

1069

{ WCD9335_CDC_COMPANDER6_CTL4, 0xff },

1070

{ WCD9335_CDC_COMPANDER6_CTL5, 0x00 },

1071

{ WCD9335_CDC_COMPANDER6_CTL6, 0x01 },

1072

{ WCD9335_CDC_COMPANDER7_CTL0, 0x60 },

1073

{ WCD9335_CDC_COMPANDER7_CTL1, 0xdb },

1074

{ WCD9335_CDC_COMPANDER7_CTL2, 0xff },

1075

{ WCD9335_CDC_COMPANDER7_CTL3, 0x35 },

1076

{ WCD9335_CDC_COMPANDER7_CTL4, 0xff },

1077

{ WCD9335_CDC_COMPANDER7_CTL5, 0x00 },

1078

{ WCD9335_CDC_COMPANDER7_CTL6, 0x01 },

1079

{ WCD9335_CDC_COMPANDER8_CTL0, 0x60 },

1080

{ WCD9335_CDC_COMPANDER8_CTL1, 0xdb },

1081

{ WCD9335_CDC_COMPANDER8_CTL2, 0xff },

1082

{ WCD9335_CDC_COMPANDER8_CTL3, 0x35 },

1083

{ WCD9335_CDC_COMPANDER8_CTL4, 0xff },

1084

{ WCD9335_CDC_COMPANDER8_CTL5, 0x00 },

1085

{ WCD9335_CDC_COMPANDER8_CTL6, 0x01 },

1086

{ WCD9335_CDC_RX0_RX_PATH_CTL, 0x04 },

1087

{ WCD9335_CDC_RX0_RX_PATH_CFG0, 0x00 },

1088

{ WCD9335_CDC_RX0_RX_PATH_CFG2, 0x8f },

1089

{ WCD9335_CDC_RX0_RX_VOL_CTL, 0x00 },

1090

{ WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 0x04 },

1091

{ WCD9335_CDC_RX0_RX_VOL_MIX_CTL, 0x00 },

1092

{ WCD9335_CDC_RX0_RX_PATH_SEC2, 0x00 },

1093

{ WCD9335_CDC_RX0_RX_PATH_SEC3, 0x00 },

1094

{ WCD9335_CDC_RX0_RX_PATH_SEC5, 0x00 },

1095

{ WCD9335_CDC_RX0_RX_PATH_SEC6, 0x00 },

1096

{ WCD9335_CDC_RX0_RX_PATH_SEC7, 0x00 },

1097

{ WCD9335_CDC_RX0_RX_PATH_MIX_SEC1, 0x00 },

1098

{ WCD9335_CDC_RX1_RX_PATH_CTL, 0x04 },

1099

{ WCD9335_CDC_RX1_RX_PATH_CFG0, 0x00 },

1100

{ WCD9335_CDC_RX1_RX_PATH_CFG2, 0x8f },

1101

{ WCD9335_CDC_RX1_RX_VOL_CTL, 0x00 },

1102

{ WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 0x04 },

1103

{ WCD9335_CDC_RX1_RX_VOL_MIX_CTL, 0x00 },

1104

{ WCD9335_CDC_RX1_RX_PATH_SEC2, 0x00 },

1105

{ WCD9335_CDC_RX1_RX_PATH_SEC3, 0x00 },

1106

{ WCD9335_CDC_RX1_RX_PATH_SEC4, 0x00 },

1107

{ WCD9335_CDC_RX1_RX_PATH_SEC5, 0x00 },

1108

{ WCD9335_CDC_RX1_RX_PATH_SEC6, 0x00 },

1109

{ WCD9335_CDC_RX1_RX_PATH_SEC7, 0x00 },

1110

{ WCD9335_CDC_RX1_RX_PATH_MIX_SEC1, 0x00 },

1111

{ WCD9335_CDC_RX2_RX_PATH_CTL, 0x04 },

1112

{ WCD9335_CDC_RX2_RX_PATH_CFG0, 0x00 },

1113

{ WCD9335_CDC_RX2_RX_PATH_CFG2, 0x8f },

1114

{ WCD9335_CDC_RX2_RX_VOL_CTL, 0x00 },

1115

{ WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 0x04 },

1116

{ WCD9335_CDC_RX2_RX_VOL_MIX_CTL, 0x00 },

1117

{ WCD9335_CDC_RX2_RX_PATH_SEC2, 0x00 },

1118

{ WCD9335_CDC_RX2_RX_PATH_SEC3, 0x00 },

1119

{ WCD9335_CDC_RX2_RX_PATH_SEC4, 0x00 },

1120

{ WCD9335_CDC_RX2_RX_PATH_SEC5, 0x00 },

1121

{ WCD9335_CDC_RX2_RX_PATH_SEC6, 0x00 },

1122

{ WCD9335_CDC_RX2_RX_PATH_SEC7, 0x00 },

1123

{ WCD9335_CDC_RX2_RX_PATH_MIX_SEC1, 0x00 },

1124

{ WCD9335_CDC_RX3_RX_PATH_CTL, 0x04 },

1125

{ WCD9335_CDC_RX3_RX_PATH_CFG0, 0x00 },

1126

{ WCD9335_CDC_RX3_RX_PATH_CFG2, 0x8f },

1127

{ WCD9335_CDC_RX3_RX_VOL_CTL, 0x00 },

1128

{ WCD9335_CDC_RX3_RX_PATH_MIX_CTL, 0x04 },

1129

{ WCD9335_CDC_RX3_RX_VOL_MIX_CTL, 0x00 },

1130

{ WCD9335_CDC_RX3_RX_PATH_SEC2, 0x00 },

1131

{ WCD9335_CDC_RX3_RX_PATH_SEC3, 0x00 },

1132

{ WCD9335_CDC_RX3_RX_PATH_SEC5, 0x00 },

1133

{ WCD9335_CDC_RX3_RX_PATH_SEC6, 0x00 },

1134

{ WCD9335_CDC_RX3_RX_PATH_SEC7, 0x00 },

1135

{ WCD9335_CDC_RX3_RX_PATH_MIX_SEC1, 0x00 },

1136

{ WCD9335_CDC_RX4_RX_PATH_CTL, 0x04 },

1137

{ WCD9335_CDC_RX4_RX_PATH_CFG0, 0x00 },

1138

{ WCD9335_CDC_RX4_RX_PATH_CFG2, 0x8f },

1139

{ WCD9335_CDC_RX4_RX_VOL_CTL, 0x00 },

1140

{ WCD9335_CDC_RX4_RX_PATH_MIX_CTL, 0x04 },

1141

{ WCD9335_CDC_RX4_RX_VOL_MIX_CTL, 0x00 },

1142

{ WCD9335_CDC_RX4_RX_PATH_SEC2, 0x00 },

1143

{ WCD9335_CDC_RX4_RX_PATH_SEC3, 0x00 },

1144

{ WCD9335_CDC_RX4_RX_PATH_SEC5, 0x00 },

1145

{ WCD9335_CDC_RX4_RX_PATH_SEC6, 0x00 },

1146

{ WCD9335_CDC_RX4_RX_PATH_SEC7, 0x00 },

1147

{ WCD9335_CDC_RX4_RX_PATH_MIX_SEC1, 0x00 },

1148

{ WCD9335_CDC_RX5_RX_PATH_CTL, 0x04 },

1149

{ WCD9335_CDC_RX5_RX_PATH_CFG0, 0x00 },

1150

{ WCD9335_CDC_RX5_RX_PATH_CFG2, 0x8f },

1151

{ WCD9335_CDC_RX5_RX_VOL_CTL, 0x00 },

1152

{ WCD9335_CDC_RX5_RX_PATH_MIX_CTL, 0x04 },

1153

{ WCD9335_CDC_RX5_RX_VOL_MIX_CTL, 0x00 },

1154

{ WCD9335_CDC_RX5_RX_PATH_SEC2, 0x00 },

1155

{ WCD9335_CDC_RX5_RX_PATH_SEC3, 0x00 },

1156

{ WCD9335_CDC_RX5_RX_PATH_SEC5, 0x00 },

1157

{ WCD9335_CDC_RX5_RX_PATH_SEC6, 0x00 },

1158

{ WCD9335_CDC_RX5_RX_PATH_SEC7, 0x00 },

1159

{ WCD9335_CDC_RX5_RX_PATH_MIX_SEC1, 0x00 },

1160

{ WCD9335_CDC_RX6_RX_PATH_CTL, 0x04 },

1161

{ WCD9335_CDC_RX6_RX_PATH_CFG0, 0x00 },

1162

{ WCD9335_CDC_RX6_RX_PATH_CFG2, 0x8f },

1163

{ WCD9335_CDC_RX6_RX_VOL_CTL, 0x00 },

1164

{ WCD9335_CDC_RX6_RX_PATH_MIX_CTL, 0x04 },

1165

{ WCD9335_CDC_RX6_RX_VOL_MIX_CTL, 0x00 },

1166

{ WCD9335_CDC_RX6_RX_PATH_SEC2, 0x00 },

1167

{ WCD9335_CDC_RX6_RX_PATH_SEC3, 0x00 },

1168

{ WCD9335_CDC_RX6_RX_PATH_SEC5, 0x00 },

1169

{ WCD9335_CDC_RX6_RX_PATH_SEC6, 0x00 },

1170

{ WCD9335_CDC_RX6_RX_PATH_SEC7, 0x00 },

1171

{ WCD9335_CDC_RX6_RX_PATH_MIX_SEC1, 0x00 },

1172

{ WCD9335_CDC_RX7_RX_PATH_CTL, 0x04 },

1173

{ WCD9335_CDC_RX7_RX_PATH_CFG0, 0x00 },

1174

{ WCD9335_CDC_RX7_RX_PATH_CFG2, 0x8f },

1175

{ WCD9335_CDC_RX7_RX_VOL_CTL, 0x00 },

1176

{ WCD9335_CDC_RX7_RX_PATH_MIX_CTL, 0x04 },

1177

{ WCD9335_CDC_RX7_RX_VOL_MIX_CTL, 0x00 },

1178

{ WCD9335_CDC_RX7_RX_PATH_SEC2, 0x00 },

1179

{ WCD9335_CDC_RX7_RX_PATH_SEC3, 0x00 },

1180

{ WCD9335_CDC_RX7_RX_PATH_SEC5, 0x00 },

1181

{ WCD9335_CDC_RX7_RX_PATH_SEC6, 0x00 },

1182

{ WCD9335_CDC_RX7_RX_PATH_SEC7, 0x00 },

1183

{ WCD9335_CDC_RX7_RX_PATH_MIX_SEC1, 0x00 },

1184

{ WCD9335_CDC_RX8_RX_PATH_CTL, 0x04 },

1185

{ WCD9335_CDC_RX8_RX_PATH_CFG0, 0x00 },

1186

{ WCD9335_CDC_RX8_RX_PATH_CFG2, 0x8f },

1187

{ WCD9335_CDC_RX8_RX_VOL_CTL, 0x00 },

1188

{ WCD9335_CDC_RX8_RX_PATH_MIX_CTL, 0x04 },

1189

{ WCD9335_CDC_RX8_RX_VOL_MIX_CTL, 0x00 },

1190

{ WCD9335_CDC_RX8_RX_PATH_SEC2, 0x00 },

1191

{ WCD9335_CDC_RX8_RX_PATH_SEC3, 0x00 },

1192

{ WCD9335_CDC_RX8_RX_PATH_SEC5, 0x00 },

1193

{ WCD9335_CDC_RX8_RX_PATH_SEC6, 0x00 },

1194

{ WCD9335_CDC_RX8_RX_PATH_SEC7, 0x00 },

1195

{ WCD9335_CDC_RX8_RX_PATH_MIX_SEC1, 0x00 },

1196

/* Page #12 registers */

1197

{ WCD9335_PAGE12_PAGE_REGISTER, 0x00 },

1198

{ WCD9335_CDC_CLSH_CRC, 0x00 },

1199

{ WCD9335_CDC_CLSH_DLY_CTRL, 0x03 },

1200

{ WCD9335_CDC_CLSH_DECAY_CTRL, 0x02 },

1201

{ WCD9335_CDC_CLSH_HPH_V_PA, 0x1c },

1202

{ WCD9335_CDC_CLSH_EAR_V_PA, 0x39 },

1203

{ WCD9335_CDC_CLSH_HPH_V_HD, 0x0c },

1204

{ WCD9335_CDC_CLSH_EAR_V_HD, 0x0c },

1205

{ WCD9335_CDC_CLSH_K1_MSB, 0x01 },

1206

{ WCD9335_CDC_CLSH_K1_LSB, 0x00 },

1207

{ WCD9335_CDC_CLSH_K2_MSB, 0x00 },

1208

{ WCD9335_CDC_CLSH_K2_LSB, 0x80 },

1209

{ WCD9335_CDC_CLSH_IDLE_CTRL, 0x00 },

1210

{ WCD9335_CDC_CLSH_IDLE_HPH, 0x00 },

1211

{ WCD9335_CDC_CLSH_IDLE_EAR, 0x00 },

1212

{ WCD9335_CDC_CLSH_TEST0, 0x07 },

1213

{ WCD9335_CDC_CLSH_TEST1, 0x00 },

1214

{ WCD9335_CDC_CLSH_OVR_VREF, 0x00 },

1215

{ WCD9335_CDC_BOOST0_BOOST_PATH_CTL, 0x00 },

1216

{ WCD9335_CDC_BOOST0_BOOST_CTL, 0xb2 },

1217

{ WCD9335_CDC_BOOST0_BOOST_CFG1, 0x00 },

1218

{ WCD9335_CDC_BOOST0_BOOST_CFG2, 0x00 },

1219

{ WCD9335_CDC_BOOST1_BOOST_PATH_CTL, 0x00 },

1220

{ WCD9335_CDC_BOOST1_BOOST_CTL, 0xb2 },

1221

{ WCD9335_CDC_BOOST1_BOOST_CFG1, 0x00 },

1222

{ WCD9335_CDC_BOOST1_BOOST_CFG2, 0x00 },

1223

{ WCD9335_SWR_AHB_BRIDGE_WR_DATA_0, 0x00 },

1224

{ WCD9335_SWR_AHB_BRIDGE_WR_DATA_1, 0x00 },

1225

{ WCD9335_SWR_AHB_BRIDGE_WR_DATA_2, 0x00 },

1226

{ WCD9335_SWR_AHB_BRIDGE_WR_DATA_3, 0x00 },

1227

{ WCD9335_SWR_AHB_BRIDGE_WR_ADDR_0, 0x00 },

1228

{ WCD9335_SWR_AHB_BRIDGE_WR_ADDR_1, 0x00 },

1229

{ WCD9335_SWR_AHB_BRIDGE_WR_ADDR_2, 0x00 },

1230

{ WCD9335_SWR_AHB_BRIDGE_WR_ADDR_3, 0x00 },

1231

{ WCD9335_SWR_AHB_BRIDGE_RD_ADDR_0, 0x00 },

1232

{ WCD9335_SWR_AHB_BRIDGE_RD_ADDR_1, 0x00 },

1233

{ WCD9335_SWR_AHB_BRIDGE_RD_ADDR_2, 0x00 },

1234

{ WCD9335_SWR_AHB_BRIDGE_RD_ADDR_3, 0x00 },

1235

{ WCD9335_SWR_AHB_BRIDGE_RD_DATA_0, 0x00 },

1236

{ WCD9335_SWR_AHB_BRIDGE_RD_DATA_1, 0x00 },

1237

{ WCD9335_SWR_AHB_BRIDGE_RD_DATA_2, 0x00 },

1238

{ WCD9335_SWR_AHB_BRIDGE_RD_DATA_3, 0x00 },

1239

{ WCD9335_SWR_AHB_BRIDGE_ACCESS_CFG, 0x0f },

1240

{ WCD9335_SWR_AHB_BRIDGE_ACCESS_STATUS, 0x03 },

1241

{ WCD9335_CDC_VBAT_VBAT_PATH_CTL, 0x00 },

1242

{ WCD9335_CDC_VBAT_VBAT_CFG, 0x0a },

1243

{ WCD9335_CDC_VBAT_VBAT_ADC_CAL1, 0x00 },

1244

{ WCD9335_CDC_VBAT_VBAT_ADC_CAL2, 0x00 },

1245

{ WCD9335_CDC_VBAT_VBAT_ADC_CAL3, 0x04 },

1246

{ WCD9335_CDC_VBAT_VBAT_PK_EST1, 0xe0 },

1247

{ WCD9335_CDC_VBAT_VBAT_PK_EST2, 0x01 },

1248

{ WCD9335_CDC_VBAT_VBAT_PK_EST3, 0x40 },

1249

{ WCD9335_CDC_VBAT_VBAT_RF_PROC1, 0x2a },

1250

{ WCD9335_CDC_VBAT_VBAT_RF_PROC2, 0x86 },

1251

{ WCD9335_CDC_VBAT_VBAT_TAC1, 0x70 },

1252

{ WCD9335_CDC_VBAT_VBAT_TAC2, 0x18 },

1253

{ WCD9335_CDC_VBAT_VBAT_TAC3, 0x18 },

1254

{ WCD9335_CDC_VBAT_VBAT_TAC4, 0x03 },

1255

{ WCD9335_CDC_VBAT_VBAT_GAIN_UPD1, 0x01 },

1256

{ WCD9335_CDC_VBAT_VBAT_GAIN_UPD2, 0x00 },

1257

{ WCD9335_CDC_VBAT_VBAT_GAIN_UPD3, 0x64 },

1258

{ WCD9335_CDC_VBAT_VBAT_GAIN_UPD4, 0x01 },

1259

{ WCD9335_CDC_VBAT_VBAT_DEBUG1, 0x00 },

1260

{ WCD9335_CDC_VBAT_VBAT_GAIN_UPD_MON, 0x00 },

1261

{ WCD9335_CDC_VBAT_VBAT_GAIN_MON_VAL, 0x00 },

1262

{ WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 },

1263

{ WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 },

1264

{ WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 },

1265

{ WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 },

1266

/* Page #13 registers */

1267

{ WCD9335_PAGE13_PAGE_REGISTER, 0x00 },

1268

{ WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 },

1269

{ WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 },

1270

{ WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 },

1271

{ WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 },

1272

{ WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 },

1273

{ WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 },

1274

{ WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0x00 },

1275

{ WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0x00 },

1276

{ WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0x00 },

1277

{ WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0x00 },

1278

{ WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0x00 },

1279

{ WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0x00 },

1280

{ WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0x00 },

1281

{ WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0x00 },

1282

{ WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0x00 },

1283

{ WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0x00 },

1284

{ WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0x00 },

1285

{ WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0x00 },

1286

{ WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG0, 0x00 },

1287

{ WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG1, 0x00 },

1288

{ WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG2, 0x00 },

1289

{ WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG3, 0x00 },

1290

{ WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 },

1291

{ WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 },

1292

{ WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0x00 },

1293

{ WCD9335_CDC_RX_INP_MUX_ANC_CFG0, 0x00 },

1294

{ WCD9335_CDC_RX_INP_MUX_SPLINE_SRC_CFG0, 0x00 },

1295

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00 },

1296

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00 },

1297

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00 },

1298

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00 },

1299

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00 },

1300

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00 },

1301

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00 },

1302

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00 },

1303

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00 },

1304

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00 },

1305

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00 },

1306

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00 },

1307

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0x00 },

1308

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX10_CFG0, 0x00 },

1309

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX11_CFG0, 0x00 },

1310

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX12_CFG0, 0x00 },

1311

{ WCD9335_CDC_TX_INP_MUX_ADC_MUX13_CFG0, 0x00 },

1312

{ WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 },

1313

{ WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 },

1314

{ WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 },

1315

{ WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 },

1316

{ WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 },

1317

{ WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 },

1318

{ WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 },

1319

{ WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 },

1320

{ WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0x00 },

1321

{ WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0x00 },

1322

{ WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0x00 },

1323

{ WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3, 0x00 },

1324

{ WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },

1325

{ WCD9335_CDC_CLK_RST_CTRL_SWR_CONTROL, 0x00 },

1326

{ WCD9335_CDC_PROX_DETECT_PROX_CTL, 0x08 },

1327

{ WCD9335_CDC_PROX_DETECT_PROX_POLL_PERIOD0, 0x00 },

1328

{ WCD9335_CDC_PROX_DETECT_PROX_POLL_PERIOD1, 0x4b },

1329

{ WCD9335_CDC_PROX_DETECT_PROX_SIG_PATTERN_LSB, 0x00 },

1330

{ WCD9335_CDC_PROX_DETECT_PROX_SIG_PATTERN_MSB, 0x00 },

1331

{ WCD9335_CDC_PROX_DETECT_PROX_STATUS, 0x00 },

1332

{ WCD9335_CDC_PROX_DETECT_PROX_TEST_CTRL, 0x00 },

1333

{ WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB, 0x00 },

1334

{ WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB, 0x00 },

1335

{ WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB_RD, 0x00 },

1336

{ WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB_RD, 0x00 },

1337

{ WCD9335_CDC_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 },

1338

{ WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 },

1339

{ WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 },

1340

{ WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 },

1341

{ WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 },

1342

{ WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 },

1343

{ WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 },

1344

{ WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 },

1345

{ WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 },

1346

{ WCD9335_CDC_SIDETONE_IIR0_IIR_CTL, 0x40 },

1347

{ WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 },

1348

{ WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 },

1349

{ WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 },

1350

{ WCD9335_CDC_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 },

1351

{ WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 },

1352

{ WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 },

1353

{ WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 },

1354

{ WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 },

1355

{ WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 },

1356

{ WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 },

1357

{ WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 },

1358

{ WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 },

1359

{ WCD9335_CDC_SIDETONE_IIR1_IIR_CTL, 0x40 },

1360

{ WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 },

1361

{ WCD9335_CDC_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 },

1362

{ WCD9335_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 },

1363

{ WCD9335_CDC_TOP_TOP_CFG0, 0x00 },

1364

{ WCD9335_CDC_TOP_TOP_CFG1, 0x00 },

1365

{ WCD9335_CDC_TOP_TOP_CFG2, 0x00 },

1366

{ WCD9335_CDC_TOP_TOP_CFG3, 0x18 },

1367

{ WCD9335_CDC_TOP_TOP_CFG4, 0x00 },

1368

{ WCD9335_CDC_TOP_TOP_CFG5, 0x00 },

1369

{ WCD9335_CDC_TOP_TOP_CFG6, 0x00 },

1370

{ WCD9335_CDC_TOP_TOP_CFG7, 0x00 },

1371

{ WCD9335_CDC_TOP_HPHL_COMP_WR_LSB, 0x00 },

1372

{ WCD9335_CDC_TOP_HPHL_COMP_WR_MSB, 0x00 },

1373

{ WCD9335_CDC_TOP_HPHL_COMP_LUT, 0x00 },

1374

{ WCD9335_CDC_TOP_HPHL_COMP_RD_LSB, 0x00 },

1375

{ WCD9335_CDC_TOP_HPHL_COMP_RD_MSB, 0x00 },

1376

{ WCD9335_CDC_TOP_HPHR_COMP_WR_LSB, 0x00 },

1377

{ WCD9335_CDC_TOP_HPHR_COMP_WR_MSB, 0x00 },

1378

{ WCD9335_CDC_TOP_HPHR_COMP_LUT, 0x00 },

1379

{ WCD9335_CDC_TOP_HPHR_COMP_RD_LSB, 0x00 },

1380

{ WCD9335_CDC_TOP_HPHR_COMP_RD_MSB, 0x00 },

1381

{ WCD9335_CDC_TOP_DIFFL_COMP_WR_LSB, 0x00 },

1382

{ WCD9335_CDC_TOP_DIFFL_COMP_WR_MSB, 0x00 },

1383

{ WCD9335_CDC_TOP_DIFFL_COMP_LUT, 0x00 },

1384

{ WCD9335_CDC_TOP_DIFFL_COMP_RD_LSB, 0x00 },

1385

{ WCD9335_CDC_TOP_DIFFL_COMP_RD_MSB, 0x00 },

1386

{ WCD9335_CDC_TOP_DIFFR_COMP_WR_LSB, 0x00 },

1387

{ WCD9335_CDC_TOP_DIFFR_COMP_WR_MSB, 0x00 },

1388

{ WCD9335_CDC_TOP_DIFFR_COMP_LUT, 0x00 },

1389

{ WCD9335_CDC_TOP_DIFFR_COMP_RD_LSB, 0x00 },

1390

{ WCD9335_CDC_TOP_DIFFR_COMP_RD_MSB, 0x00 },

1391

/* Page #0x80 registers */

1392

{ WCD9335_PAGE80_PAGE_REGISTER, 0x00 },

1393

{ WCD9335_TLMM_BIST_MODE_PINCFG, 0x00 },

1394

{ WCD9335_TLMM_RF_PA_ON_PINCFG, 0x00 },

1395

{ WCD9335_TLMM_INTR1_PINCFG, 0x00 },

1396

{ WCD9335_TLMM_INTR2_PINCFG, 0x00 },

1397

{ WCD9335_TLMM_SWR_DATA_PINCFG, 0x00 },

1398

{ WCD9335_TLMM_SWR_CLK_PINCFG, 0x00 },

1399

{ WCD9335_TLMM_SLIMBUS_DATA2_PINCFG, 0x00 },

1400

{ WCD9335_TLMM_I2C_CLK_PINCFG, 0x00 },

1401

{ WCD9335_TLMM_I2C_DATA_PINCFG, 0x00 },

1402

{ WCD9335_TLMM_I2S_RX_SD0_PINCFG, 0x00 },

1403

{ WCD9335_TLMM_I2S_RX_SD1_PINCFG, 0x00 },

1404

{ WCD9335_TLMM_I2S_RX_SCK_PINCFG, 0x00 },

1405

{ WCD9335_TLMM_I2S_RX_WS_PINCFG, 0x00 },

1406

{ WCD9335_TLMM_I2S_TX_SD0_PINCFG, 0x00 },

1407

{ WCD9335_TLMM_I2S_TX_SD1_PINCFG, 0x00 },

1408

{ WCD9335_TLMM_I2S_TX_SCK_PINCFG, 0x00 },

1409

{ WCD9335_TLMM_I2S_TX_WS_PINCFG, 0x00 },

1410

{ WCD9335_TLMM_DMIC1_CLK_PINCFG, 0x00 },

1411

{ WCD9335_TLMM_DMIC1_DATA_PINCFG, 0x00 },

1412

{ WCD9335_TLMM_DMIC2_CLK_PINCFG, 0x00 },

1413

{ WCD9335_TLMM_DMIC2_DATA_PINCFG, 0x00 },

1414

{ WCD9335_TLMM_DMIC3_CLK_PINCFG, 0x00 },

1415

{ WCD9335_TLMM_DMIC3_DATA_PINCFG, 0x00 },

1416

{ WCD9335_TLMM_JTDI_PINCFG, 0x00 },

1417

{ WCD9335_TLMM_JTDO_PINCFG, 0x00 },

1418

{ WCD9335_TLMM_JTMS_PINCFG, 0x00 },

1419

{ WCD9335_TLMM_JTCK_PINCFG, 0x00 },

1420

{ WCD9335_TLMM_JTRST_PINCFG, 0x00 },

1421

{ WCD9335_TEST_DEBUG_PIN_CTL_OE_0, 0x00 },

1422

{ WCD9335_TEST_DEBUG_PIN_CTL_OE_1, 0x00 },

1423

{ WCD9335_TEST_DEBUG_PIN_CTL_OE_2, 0x00 },

1424

{ WCD9335_TEST_DEBUG_PIN_CTL_OE_3, 0x00 },

1425

{ WCD9335_TEST_DEBUG_PIN_CTL_DATA_0, 0x00 },

1426

{ WCD9335_TEST_DEBUG_PIN_CTL_DATA_1, 0x00 },

1427

{ WCD9335_TEST_DEBUG_PIN_CTL_DATA_2, 0x00 },

1428

{ WCD9335_TEST_DEBUG_PIN_CTL_DATA_3, 0x00 },

1429

{ WCD9335_TEST_DEBUG_PAD_DRVCTL, 0x00 },

1430

{ WCD9335_TEST_DEBUG_PIN_STATUS, 0x00 },

1431

{ WCD9335_TEST_DEBUG_MEM_CTRL, 0x00 },

1432

{ WCD9335_TEST_DEBUG_DEBUG_BUS_SEL, 0x00 },

1433

{ WCD9335_TEST_DEBUG_DEBUG_JTAG, 0x00 },

1434

{ WCD9335_TEST_DEBUG_DEBUG_EN_1, 0x00 },

1435

{ WCD9335_TEST_DEBUG_DEBUG_EN_2, 0x00 },

1436

{ WCD9335_TEST_DEBUG_DEBUG_EN_3, 0x00 },

};

/*

* wcd9335_regmap_register_patch: Update register defaults based on version

1441

* @regmap: handle to wcd9xxx regmap

1442

* @version: wcd9335 version

1443

*

1444

* Returns error code in case of failure or 0 for success

1445

*/

1446

int wcd9335_regmap_register_patch(struct regmap *regmap, int version)

{

int rc;

if (!regmap) {

pr_err("%s: regmap struct is NULL\n", __func__);

return -EINVAL;

}

switch (version) {

case TASHA_VERSION_1_0:

1457

case TASHA_VERSION_1_1:

1458

regcache_cache_only(regmap, true);

1459

rc = regmap_multi_reg_write(regmap, wcd9335_1_x_defaults,

1460

ARRAY_SIZE(wcd9335_1_x_defaults));

1461

regcache_cache_only(regmap, false);

1462

break;

1463

case TASHA_VERSION_2_0:

1464

regcache_cache_only(regmap, true);

1465

rc = regmap_multi_reg_write(regmap, wcd9335_2_0_defaults,

1466

ARRAY_SIZE(wcd9335_2_0_defaults));

1467

regcache_cache_only(regmap, false);

1468

break;

1469

default:

1470

pr_err("%s: unknown version: %d\n", __func__, version);

rc = -EINVAL;

break;

}

return rc;

}

EXPORT_SYMBOL(wcd9335_regmap_register_patch);

1478

1479

static bool wcd9335_is_readable_register(struct device *dev, unsigned int reg)

1480

{

1481

u8 pg_num, reg_offset;

1482

const u8 *reg_tbl = NULL;

1483

1484

/*

1485

* Get the page number from MSB of codec register. If its 0x80, assign

1486

* the corresponding page index PAGE_0x80.

*/

pg_num = reg >> 0x8;

if (pg_num == 0x80)

pg_num = PAGE_0X80;

else if (pg_num >= 0xE)

1492

return false;

1493

1494

reg_tbl = wcd9335_reg[pg_num];

1495

reg_offset = reg & 0xFF;

1496

1497

if (reg_tbl)

1498

return reg_tbl[reg_offset];

else

return false;

}

static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)

1504

{

1505

/*

1506

* registers from 0x000 to 0x0FF are volatile because

1507

* this space contains registers related to interrupt

* status, mask etc

*/

if (reg < 0x100)

return true;

/* IIR Coeff registers are not cacheable */

1514

if ((reg >= WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL) &&

1515

(reg <= WCD9335_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL))

1516

return true;

1517

1518

if ((reg >= WCD9335_CDC_ANC0_IIR_COEFF_1_CTL) &&

1519

(reg <= WCD9335_CDC_ANC0_FB_GAIN_CTL))

1520

return true;

1521

1522

if ((reg >= WCD9335_CDC_ANC1_IIR_COEFF_1_CTL) &&

1523

(reg <= WCD9335_CDC_ANC1_FB_GAIN_CTL))

1524

return true;

1525

/*

1526

* CPE inbox and outbox registers are volatile

1527

* since they can be updated in the codec hardware

1528

* to indicate CPE status

1529

*/

1530

if (reg >= WCD9335_CPE_SS_MEM_PTR_0 &&

1531

reg <= WCD9335_CPE_SS_OUTBOX2_ACK)

1532

return true;

1533

1534

if (reg >= WCD9335_RCO_CAL_OUT_1 &&

1535

reg <= WCD9335_RCO_CAL_OUT_5)

return true;

switch (reg) {

case WCD9335_CPE_SS_INBOX1_TRG:

1540

case WCD9335_CPE_SS_INBOX2_TRG:

1541

case WCD9335_SWR_AHB_BRIDGE_WR_DATA_0:

1542

case WCD9335_SWR_AHB_BRIDGE_WR_DATA_1:

1543

case WCD9335_SWR_AHB_BRIDGE_WR_DATA_2:

1544

case WCD9335_SWR_AHB_BRIDGE_WR_DATA_3:

1545

case WCD9335_SWR_AHB_BRIDGE_WR_ADDR_0:

1546

case WCD9335_SWR_AHB_BRIDGE_WR_ADDR_1:

1547

case WCD9335_SWR_AHB_BRIDGE_WR_ADDR_2:

1548

case WCD9335_SWR_AHB_BRIDGE_WR_ADDR_3:

1549

case WCD9335_SWR_AHB_BRIDGE_RD_DATA_0:

1550

case WCD9335_SWR_AHB_BRIDGE_RD_DATA_1:

1551

case WCD9335_SWR_AHB_BRIDGE_RD_DATA_2:

1552

case WCD9335_SWR_AHB_BRIDGE_RD_DATA_3:

1553

case WCD9335_SWR_AHB_BRIDGE_RD_ADDR_0:

1554

case WCD9335_SWR_AHB_BRIDGE_RD_ADDR_1:

1555

case WCD9335_SWR_AHB_BRIDGE_RD_ADDR_2:

1556

case WCD9335_SWR_AHB_BRIDGE_RD_ADDR_3:

1557

case WCD9335_ANA_BIAS:

1558

case WCD9335_ANA_CLK_TOP:

1559

case WCD9335_ANA_RCO:

1560

case WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL:

1561

case WCD9335_ANA_MBHC_RESULT_3:

1562

case WCD9335_ANA_MBHC_RESULT_2:

1563

case WCD9335_ANA_MBHC_RESULT_1:

1564

case WCD9335_ANA_MBHC_MECH:

1565

case WCD9335_ANA_MBHC_ELECT:

1566

case WCD9335_ANA_MBHC_ZDET:

1567

case WCD9335_ANA_MICB2:

1568

case WCD9335_CPE_SS_SS_ERROR_INT_STATUS:

1569

case WCD9335_CPE_SS_SS_ERROR_INT_MASK:

1570

case WCD9335_CPE_SS_SS_ERROR_INT_CLEAR:

1571

case WCD9335_CPE_SS_STATUS:

1572

case WCD9335_CPE_SS_BACKUP_INT:

1573

case WCD9335_CPE_SS_CFG:

1574

case WCD9335_SOC_MAD_MAIN_CTL_1:

1575

case WCD9335_SOC_MAD_AUDIO_CTL_3:

1576

case WCD9335_SOC_MAD_AUDIO_CTL_4:

1577

case WCD9335_FLYBACK_EN:

1578

case WCD9335_ANA_RX_SUPPLIES:

1579

case WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL:

1580

case WCD9335_SIDO_SIDO_CCL_2:

1581

case WCD9335_SIDO_SIDO_CCL_4:

1582

case WCD9335_DATA_HUB_NATIVE_FIFO_STATUS:

1583

case WCD9335_MBHC_FSM_STATUS:

1584

case WCD9335_SPLINE_SRC0_STATUS:

1585

case WCD9335_SPLINE_SRC1_STATUS:

1586

case WCD9335_SPLINE_SRC2_STATUS:

1587

case WCD9335_SPLINE_SRC3_STATUS:

1588

case WCD9335_SIDO_SIDO_TEST_2:

1589

case WCD9335_SIDO_SIDO_CCL_8:

1590

case WCD9335_BIAS_VBG_FINE_ADJ:

1591

case WCD9335_VBADC_ADC_DOUTMSB:

1592

case WCD9335_VBADC_ADC_DOUTLSB:

1593

case WCD9335_CDC_VBAT_VBAT_GAIN_MON_VAL:

1594

case WCD9335_ANA_BUCK_CTL:

return true;

default:

return false;

}

}

struct regmap_config wcd9335_regmap_config = {

1602

.reg_bits = 16,

1603

.val_bits = 8,

1604

.cache_type = REGCACHE_RBTREE,

1605

.reg_defaults = wcd9335_defaults,

1606

.num_reg_defaults = ARRAY_SIZE(wcd9335_defaults),

1607

.max_register = WCD9335_MAX_REGISTER,

1608

.volatile_reg = wcd9335_is_volatile_register,

1609

.readable_reg = wcd9335_is_readable_register,

1610

.can_multi_write = true,

1611

};