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Catalin Marinasb3901d52012-03-05 11:49:28 +00001/*
2 * Based on arch/arm/kernel/process.c
3 *
4 * Original Copyright (C) 1995 Linus Torvalds
5 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <stdarg.h>
22
AKASHI Takahirofd92d4a2014-04-30 10:51:32 +010023#include <linux/compat.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000024#include <linux/export.h>
25#include <linux/sched.h>
26#include <linux/kernel.h>
27#include <linux/mm.h>
28#include <linux/stddef.h>
29#include <linux/unistd.h>
30#include <linux/user.h>
31#include <linux/delay.h>
32#include <linux/reboot.h>
33#include <linux/interrupt.h>
34#include <linux/kallsyms.h>
35#include <linux/init.h>
36#include <linux/cpu.h>
37#include <linux/elfcore.h>
38#include <linux/pm.h>
39#include <linux/tick.h>
40#include <linux/utsname.h>
41#include <linux/uaccess.h>
42#include <linux/random.h>
43#include <linux/hw_breakpoint.h>
44#include <linux/personality.h>
45#include <linux/notifier.h>
46
47#include <asm/compat.h>
48#include <asm/cacheflush.h>
Will Deaconec45d1c2013-01-17 12:31:45 +000049#include <asm/fpsimd.h>
50#include <asm/mmu_context.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000051#include <asm/processor.h>
52#include <asm/stacktrace.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000053
54static void setup_restart(void)
55{
56 /*
57 * Tell the mm system that we are going to reboot -
58 * we may need it to insert some 1:1 mappings so that
59 * soft boot works.
60 */
61 setup_mm_for_reboot();
62
63 /* Clean and invalidate caches */
64 flush_cache_all();
65
66 /* Turn D-cache off */
67 cpu_cache_off();
68
69 /* Push out any further dirty data, and ensure cache is empty */
70 flush_cache_all();
71}
72
73void soft_restart(unsigned long addr)
74{
Geoff Levand09024aa2013-12-17 00:19:29 +000075 typedef void (*phys_reset_t)(unsigned long);
76 phys_reset_t phys_reset;
77
Catalin Marinasb3901d52012-03-05 11:49:28 +000078 setup_restart();
Geoff Levand09024aa2013-12-17 00:19:29 +000079
80 /* Switch to the identity mapping */
81 phys_reset = (phys_reset_t)virt_to_phys(cpu_reset);
82 phys_reset(addr);
83
84 /* Should never get here */
85 BUG();
Catalin Marinasb3901d52012-03-05 11:49:28 +000086}
87
88/*
89 * Function pointers to optional machine specific functions
90 */
91void (*pm_power_off)(void);
92EXPORT_SYMBOL_GPL(pm_power_off);
93
Catalin Marinasb0946fc2013-07-23 11:05:10 +010094void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000095EXPORT_SYMBOL_GPL(arm_pm_restart);
Catalin Marinasb3901d52012-03-05 11:49:28 +000096
Catalin Marinasb3901d52012-03-05 11:49:28 +000097/*
98 * This is our default idle handler.
99 */
Thomas Gleixner00872982013-03-21 22:49:39 +0100100void arch_cpu_idle(void)
Catalin Marinasb3901d52012-03-05 11:49:28 +0000101{
102 /*
103 * This should do all the clock switching and wait for interrupt
104 * tricks
105 */
Nicolas Pitre69905662014-02-17 10:59:30 -0500106 cpu_do_idle();
107 local_irq_enable();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000108}
109
Mark Rutland9327e2c2013-10-24 20:30:18 +0100110#ifdef CONFIG_HOTPLUG_CPU
111void arch_cpu_idle_dead(void)
112{
113 cpu_die();
114}
115#endif
116
Arun KS90f51a02014-05-07 02:41:22 +0100117/*
118 * Called by kexec, immediately prior to machine_kexec().
119 *
120 * This must completely disable all secondary CPUs; simply causing those CPUs
121 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
122 * kexec'd kernel to use any and all RAM as it sees fit, without having to
123 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
124 * functionality embodied in disable_nonboot_cpus() to achieve this.
125 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000126void machine_shutdown(void)
127{
Arun KS90f51a02014-05-07 02:41:22 +0100128 disable_nonboot_cpus();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000129}
130
Arun KS90f51a02014-05-07 02:41:22 +0100131/*
132 * Halting simply requires that the secondary CPUs stop performing any
133 * activity (executing tasks, handling interrupts). smp_send_stop()
134 * achieves this.
135 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000136void machine_halt(void)
137{
Arun KS90f51a02014-05-07 02:41:22 +0100138 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000139 while (1);
140}
141
Arun KS90f51a02014-05-07 02:41:22 +0100142/*
143 * Power-off simply requires that the secondary CPUs stop performing any
144 * activity (executing tasks, handling interrupts). smp_send_stop()
145 * achieves this. When the system power is turned off, it will take all CPUs
146 * with it.
147 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000148void machine_power_off(void)
149{
Arun KS90f51a02014-05-07 02:41:22 +0100150 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000151 if (pm_power_off)
152 pm_power_off();
153}
154
Arun KS90f51a02014-05-07 02:41:22 +0100155/*
156 * Restart requires that the secondary CPUs stop performing any activity
157 * while the primary CPU resets the system. Systems with a single CPU can
158 * use soft_restart() as their machine descriptor's .restart hook, since that
159 * will cause the only available CPU to reset. Systems with multiple CPUs must
160 * provide a HW restart implementation, to ensure that all CPUs reset at once.
161 * This is required so that any code running after reset on the primary CPU
162 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
163 * executing pre-reset code, and using RAM that the primary CPU's code wishes
164 * to use. Implementing such co-ordination would be essentially impossible.
165 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000166void machine_restart(char *cmd)
167{
Arun KS90f51a02014-05-07 02:41:22 +0100168 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000169
170 /* Disable interrupts first */
171 local_irq_disable();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000172
173 /* Now call the architecture specific reboot code. */
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000174 if (arm_pm_restart)
Marc Zyngierff701302013-07-11 12:13:00 +0100175 arm_pm_restart(reboot_mode, cmd);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000176
177 /*
178 * Whoops - the architecture was unable to reboot.
179 */
180 printk("Reboot failed -- System halted\n");
181 while (1);
182}
183
184void __show_regs(struct pt_regs *regs)
185{
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100186 int i, top_reg;
187 u64 lr, sp;
188
189 if (compat_user_mode(regs)) {
190 lr = regs->compat_lr;
191 sp = regs->compat_sp;
192 top_reg = 12;
193 } else {
194 lr = regs->regs[30];
195 sp = regs->sp;
196 top_reg = 29;
197 }
Catalin Marinasb3901d52012-03-05 11:49:28 +0000198
Tejun Heoa43cb952013-04-30 15:27:17 -0700199 show_regs_print_info(KERN_DEFAULT);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000200 print_symbol("PC is at %s\n", instruction_pointer(regs));
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100201 print_symbol("LR is at %s\n", lr);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000202 printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100203 regs->pc, lr, regs->pstate);
204 printk("sp : %016llx\n", sp);
205 for (i = top_reg; i >= 0; i--) {
Catalin Marinasb3901d52012-03-05 11:49:28 +0000206 printk("x%-2d: %016llx ", i, regs->regs[i]);
207 if (i % 2 == 0)
208 printk("\n");
209 }
210 printk("\n");
211}
212
213void show_regs(struct pt_regs * regs)
214{
215 printk("\n");
Catalin Marinasb3901d52012-03-05 11:49:28 +0000216 __show_regs(regs);
217}
218
219/*
220 * Free current thread data structures etc..
221 */
222void exit_thread(void)
223{
224}
225
226void flush_thread(void)
227{
228 fpsimd_flush_thread();
229 flush_ptrace_hw_breakpoint(current);
230}
231
232void release_thread(struct task_struct *dead_task)
233{
234}
235
236int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
237{
Ard Biesheuvelc51f9262014-02-24 15:26:27 +0100238 fpsimd_preserve_current_state();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000239 *dst = *src;
240 return 0;
241}
242
243asmlinkage void ret_from_fork(void) asm("ret_from_fork");
244
245int copy_thread(unsigned long clone_flags, unsigned long stack_start,
Al Viroafa86fc2012-10-22 22:51:14 -0400246 unsigned long stk_sz, struct task_struct *p)
Catalin Marinasb3901d52012-03-05 11:49:28 +0000247{
248 struct pt_regs *childregs = task_pt_regs(p);
249 unsigned long tls = p->thread.tp_value;
250
Catalin Marinasb3901d52012-03-05 11:49:28 +0000251 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
Catalin Marinasb3901d52012-03-05 11:49:28 +0000252
Al Viro9ac08002012-10-21 15:56:52 -0400253 if (likely(!(p->flags & PF_KTHREAD))) {
254 *childregs = *current_pt_regs();
Catalin Marinasc34501d2012-10-05 12:31:20 +0100255 childregs->regs[0] = 0;
256 if (is_compat_thread(task_thread_info(p))) {
Al Viroe0fd18c2012-10-18 00:55:54 -0400257 if (stack_start)
258 childregs->compat_sp = stack_start;
Catalin Marinasc34501d2012-10-05 12:31:20 +0100259 } else {
260 /*
261 * Read the current TLS pointer from tpidr_el0 as it may be
262 * out-of-sync with the saved value.
263 */
264 asm("mrs %0, tpidr_el0" : "=r" (tls));
Al Viroe0fd18c2012-10-18 00:55:54 -0400265 if (stack_start) {
266 /* 16-byte aligned stack mandatory on AArch64 */
267 if (stack_start & 15)
268 return -EINVAL;
269 childregs->sp = stack_start;
270 }
Catalin Marinasc34501d2012-10-05 12:31:20 +0100271 }
272 /*
273 * If a TLS pointer was passed to clone (4th argument), use it
274 * for the new thread.
275 */
276 if (clone_flags & CLONE_SETTLS)
Al Viro9ac08002012-10-21 15:56:52 -0400277 tls = childregs->regs[3];
Catalin Marinasc34501d2012-10-05 12:31:20 +0100278 } else {
279 memset(childregs, 0, sizeof(struct pt_regs));
280 childregs->pstate = PSR_MODE_EL1h;
281 p->thread.cpu_context.x19 = stack_start;
282 p->thread.cpu_context.x20 = stk_sz;
283 }
284 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
285 p->thread.cpu_context.sp = (unsigned long)childregs;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000286 p->thread.tp_value = tls;
287
288 ptrace_hw_copy_thread(p);
289
290 return 0;
291}
292
293static void tls_thread_switch(struct task_struct *next)
294{
295 unsigned long tpidr, tpidrro;
296
297 if (!is_compat_task()) {
298 asm("mrs %0, tpidr_el0" : "=r" (tpidr));
299 current->thread.tp_value = tpidr;
300 }
301
302 if (is_compat_thread(task_thread_info(next))) {
303 tpidr = 0;
304 tpidrro = next->thread.tp_value;
305 } else {
306 tpidr = next->thread.tp_value;
307 tpidrro = 0;
308 }
309
310 asm(
311 " msr tpidr_el0, %0\n"
312 " msr tpidrro_el0, %1"
313 : : "r" (tpidr), "r" (tpidrro));
314}
315
316/*
317 * Thread switching.
318 */
319struct task_struct *__switch_to(struct task_struct *prev,
320 struct task_struct *next)
321{
322 struct task_struct *last;
323
324 fpsimd_thread_switch(next);
325 tls_thread_switch(next);
326 hw_breakpoint_thread_switch(next);
Christopher Covington33257322013-04-03 19:01:01 +0100327 contextidr_thread_switch(next);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000328
Catalin Marinas5108c672013-04-24 14:47:02 +0100329 /*
330 * Complete any pending TLB or cache maintenance on this CPU in case
331 * the thread migrates to a different CPU.
332 */
Will Deacon98f76852014-05-02 16:24:10 +0100333 dsb(ish);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000334
335 /* the actual thread switch */
336 last = cpu_switch_to(prev, next);
337
338 return last;
339}
340
Catalin Marinasb3901d52012-03-05 11:49:28 +0000341unsigned long get_wchan(struct task_struct *p)
342{
343 struct stackframe frame;
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000344 unsigned long stack_page;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000345 int count = 0;
346 if (!p || p == current || p->state == TASK_RUNNING)
347 return 0;
348
349 frame.fp = thread_saved_fp(p);
350 frame.sp = thread_saved_sp(p);
351 frame.pc = thread_saved_pc(p);
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000352 stack_page = (unsigned long)task_stack_page(p);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000353 do {
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000354 if (frame.sp < stack_page ||
355 frame.sp >= stack_page + THREAD_SIZE ||
356 unwind_frame(&frame))
Catalin Marinasb3901d52012-03-05 11:49:28 +0000357 return 0;
358 if (!in_sched_functions(frame.pc))
359 return frame.pc;
360 } while (count ++ < 16);
361 return 0;
362}
363
364unsigned long arch_align_stack(unsigned long sp)
365{
366 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
367 sp -= get_random_int() & ~PAGE_MASK;
368 return sp & ~0xf;
369}
370
371static unsigned long randomize_base(unsigned long base)
372{
373 unsigned long range_end = base + (STACK_RND_MASK << PAGE_SHIFT) + 1;
374 return randomize_range(base, range_end, 0) ? : base;
375}
376
377unsigned long arch_randomize_brk(struct mm_struct *mm)
378{
379 return randomize_base(mm->brk);
380}
381
382unsigned long randomize_et_dyn(unsigned long base)
383{
384 return randomize_base(base);
385}