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review.shift-gmbh.com / SHIFTPHONES / android_kernel_shift_sdm845 / b54942f8203689014f80ec89c55ccb1f48ab1166 / . / include / asm-arm / hardware / iop3xx.h
blob: 63feceb7ede558afe103496036f46cfb7195924b [file] [log] [blame]
Lennert Buytenhek7ae1f7e2006-09-18 23:12:53 +0100[diff] [blame]1/*
2 * include/asm-arm/hardware/iop3xx.h
3 *
4 * Intel IOP32X and IOP33X register definitions
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __IOP3XX_H
16#define __IOP3XX_H
17
18/*
Lennert Buytenhek72edd842006-09-18 23:23:07 +0100[diff] [blame]19 * IOP3XX GPIO handling
20 */
21#define GPIO_IN 0
22#define GPIO_OUT 1
23#define GPIO_LOW 0
24#define GPIO_HIGH 1
25#define IOP3XX_GPIO_LINE(x) (x)
26
27#ifndef __ASSEMBLY__
28extern void gpio_line_config(int line, int direction);
29extern int gpio_line_get(int line);
30extern void gpio_line_set(int line, int value);
Dan Williamse90ddd82007-05-02 17:59:44 +0100[diff] [blame]31extern int init_atu;
Lennert Buytenhek72edd842006-09-18 23:23:07 +0100[diff] [blame]32#endif
33
34
35/*
Lennert Buytenhek7ae1f7e2006-09-18 23:12:53 +0100[diff] [blame]36 * IOP3XX processor registers
37 */
38#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
39#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
40#define IOP3XX_PERIPHERAL_SIZE 0x00002000
Dan Williams6df26702007-02-13 17:11:04 +0100[diff] [blame]41#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
42 IOP3XX_PERIPHERAL_SIZE - 1)
43#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
44 IOP3XX_PERIPHERAL_SIZE - 1)
Russell Kingad902cb2007-05-05 11:59:13 +0100[diff] [blame]45#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
Dan Williams6df26702007-02-13 17:11:04 +0100[diff] [blame]46 (IOP3XX_PERIPHERAL_PHYS_BASE\
47 - IOP3XX_PERIPHERAL_VIRT_BASE))
Lennert Buytenhek7ae1f7e2006-09-18 23:12:53 +0100[diff] [blame]48#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
49
Lennert Buytenhek0cb015f2006-09-18 23:16:23 +0100[diff] [blame]50/* Address Translation Unit */
51#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
52#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
53#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
54#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
55#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
56#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
57#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
58#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
59#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
60#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
61#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
62#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
63#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
64#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
65#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
66#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
67#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
68#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
69#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
70#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
71#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
72#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
73#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
74#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
75#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
76#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
77#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
78#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
79#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
80#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
81#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
82#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
83#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
84#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
85#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
86#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
87#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
88#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
89#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
90#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
91#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
92#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
93#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
94#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
95#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
96#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
97#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
98#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
99#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
100#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
101#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
102#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
103#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
104#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
105#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
106#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
Dan Williamse90ddd82007-05-02 17:59:44 +0100[diff] [blame]107#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
108#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14)
109#define IOP3XX_ATUCR_OUT_EN (1 << 1)
110
111#define IOP3XX_INIT_ATU_DEFAULT 0
112#define IOP3XX_INIT_ATU_DISABLE -1
113#define IOP3XX_INIT_ATU_ENABLE 1
114
115#ifdef CONFIG_IOP3XX_ATU
116#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
117 IOP3XX_INIT_ATU_ENABLE : init_atu)
118#else
119#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
120 IOP3XX_INIT_ATU_DISABLE : init_atu)
121#endif
Lennert Buytenhek0cb015f2006-09-18 23:16:23 +0100[diff] [blame]122
Lennert Buytenhek475549f2006-09-18 23:25:33 +0100[diff] [blame]123/* Messaging Unit */
124#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
125#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
126#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
127#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
128#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
129#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
130#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
131#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
132#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
133#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
134#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
135#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
136#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
137#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
138#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
139#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
140#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
141#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
142#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
143#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
144#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
145
146/* DMA Controller */
147#define IOP3XX_DMA0_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0400)
148#define IOP3XX_DMA0_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0404)
149#define IOP3XX_DMA0_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x040c)
150#define IOP3XX_DMA0_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0410)
151#define IOP3XX_DMA0_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0414)
152#define IOP3XX_DMA0_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0418)
153#define IOP3XX_DMA0_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x041c)
154#define IOP3XX_DMA0_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0420)
155#define IOP3XX_DMA0_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0424)
156#define IOP3XX_DMA1_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0440)
157#define IOP3XX_DMA1_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0444)
158#define IOP3XX_DMA1_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x044c)
159#define IOP3XX_DMA1_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0450)
160#define IOP3XX_DMA1_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0454)
161#define IOP3XX_DMA1_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0458)
162#define IOP3XX_DMA1_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x045c)
163#define IOP3XX_DMA1_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0460)
164#define IOP3XX_DMA1_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0464)
165
166/* Peripheral bus interface */
167#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
168#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
169#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
170#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
171#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
172#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
173#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
174#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
175#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
176#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
177#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
178#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
179#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
180#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
181#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
182#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
183#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
184
185/* Peripheral performance monitoring unit */
186#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
187#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
188#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
189#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
190/* PERCR0 DOESN'T EXIST - index from 1! */
191#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
192
Lennert Buytenhek72edd842006-09-18 23:23:07 +0100[diff] [blame]193/* General Purpose I/O */
Dan Williams4ac941d2007-01-04 02:14:49 +0100[diff] [blame]194#define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0000)
195#define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0004)
196#define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x0008)
Lennert Buytenhek72edd842006-09-18 23:23:07 +0100[diff] [blame]197
Lennert Buytenhek48388b22006-09-18 23:18:16 +0100[diff] [blame]198/* Timers */
199#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
200#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
201#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
202#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
203#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
204#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
205#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
206#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
Dan Williams3668b452007-02-13 17:13:34 +0100[diff] [blame]207#define IOP_TMR_EN 0x02
208#define IOP_TMR_RELOAD 0x04
209#define IOP_TMR_PRIVILEGED 0x08
210#define IOP_TMR_RATIO_1_1 0x00
Lennert Buytenhek48388b22006-09-18 23:18:16 +0100[diff] [blame]211
Lennert Buytenhek475549f2006-09-18 23:25:33 +0100[diff] [blame]212/* Application accelerator unit */
213#define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800)
214#define IOP3XX_AAU_ASR (volatile u32 *)IOP3XX_REG_ADDR(0x0804)
215#define IOP3XX_AAU_ADAR (volatile u32 *)IOP3XX_REG_ADDR(0x0808)
216#define IOP3XX_AAU_ANDAR (volatile u32 *)IOP3XX_REG_ADDR(0x080c)
217#define IOP3XX_AAU_SAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0810)
218#define IOP3XX_AAU_SAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0814)
219#define IOP3XX_AAU_SAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0818)
220#define IOP3XX_AAU_SAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x081c)
221#define IOP3XX_AAU_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x0820)
222#define IOP3XX_AAU_ABCR (volatile u32 *)IOP3XX_REG_ADDR(0x0824)
223#define IOP3XX_AAU_ADCR (volatile u32 *)IOP3XX_REG_ADDR(0x0828)
224#define IOP3XX_AAU_SAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x082c)
225#define IOP3XX_AAU_SAR6 (volatile u32 *)IOP3XX_REG_ADDR(0x0830)
226#define IOP3XX_AAU_SAR7 (volatile u32 *)IOP3XX_REG_ADDR(0x0834)
227#define IOP3XX_AAU_SAR8 (volatile u32 *)IOP3XX_REG_ADDR(0x0838)
228#define IOP3XX_AAU_EDCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x083c)
229#define IOP3XX_AAU_SAR9 (volatile u32 *)IOP3XX_REG_ADDR(0x0840)
230#define IOP3XX_AAU_SAR10 (volatile u32 *)IOP3XX_REG_ADDR(0x0844)
231#define IOP3XX_AAU_SAR11 (volatile u32 *)IOP3XX_REG_ADDR(0x0848)
232#define IOP3XX_AAU_SAR12 (volatile u32 *)IOP3XX_REG_ADDR(0x084c)
233#define IOP3XX_AAU_SAR13 (volatile u32 *)IOP3XX_REG_ADDR(0x0850)
234#define IOP3XX_AAU_SAR14 (volatile u32 *)IOP3XX_REG_ADDR(0x0854)
235#define IOP3XX_AAU_SAR15 (volatile u32 *)IOP3XX_REG_ADDR(0x0858)
236#define IOP3XX_AAU_SAR16 (volatile u32 *)IOP3XX_REG_ADDR(0x085c)
237#define IOP3XX_AAU_EDCR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0860)
238#define IOP3XX_AAU_SAR17 (volatile u32 *)IOP3XX_REG_ADDR(0x0864)
239#define IOP3XX_AAU_SAR18 (volatile u32 *)IOP3XX_REG_ADDR(0x0868)
240#define IOP3XX_AAU_SAR19 (volatile u32 *)IOP3XX_REG_ADDR(0x086c)
241#define IOP3XX_AAU_SAR20 (volatile u32 *)IOP3XX_REG_ADDR(0x0870)
242#define IOP3XX_AAU_SAR21 (volatile u32 *)IOP3XX_REG_ADDR(0x0874)
243#define IOP3XX_AAU_SAR22 (volatile u32 *)IOP3XX_REG_ADDR(0x0878)
244#define IOP3XX_AAU_SAR23 (volatile u32 *)IOP3XX_REG_ADDR(0x087c)
245#define IOP3XX_AAU_SAR24 (volatile u32 *)IOP3XX_REG_ADDR(0x0880)
246#define IOP3XX_AAU_EDCR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0884)
247#define IOP3XX_AAU_SAR25 (volatile u32 *)IOP3XX_REG_ADDR(0x0888)
248#define IOP3XX_AAU_SAR26 (volatile u32 *)IOP3XX_REG_ADDR(0x088c)
249#define IOP3XX_AAU_SAR27 (volatile u32 *)IOP3XX_REG_ADDR(0x0890)
250#define IOP3XX_AAU_SAR28 (volatile u32 *)IOP3XX_REG_ADDR(0x0894)
251#define IOP3XX_AAU_SAR29 (volatile u32 *)IOP3XX_REG_ADDR(0x0898)
252#define IOP3XX_AAU_SAR30 (volatile u32 *)IOP3XX_REG_ADDR(0x089c)
253#define IOP3XX_AAU_SAR31 (volatile u32 *)IOP3XX_REG_ADDR(0x08a0)
254#define IOP3XX_AAU_SAR32 (volatile u32 *)IOP3XX_REG_ADDR(0x08a4)
255
Lennert Buytenheke25d64f2006-09-18 23:15:21 +0100[diff] [blame]256/* I2C bus interface unit */
257#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
258#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
259#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
260#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
261#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
262#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
263#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
264#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
265#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
266#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
267
Lennert Buytenhek7ae1f7e2006-09-18 23:12:53 +0100[diff] [blame]268
269/*
270 * IOP3XX I/O and Mem space regions for PCI autoconfiguration
271 */
Dan Williamse90ddd82007-05-02 17:59:44 +0100[diff] [blame]272#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
Lennert Buytenhek7ae1f7e2006-09-18 23:12:53 +0100[diff] [blame]273
274#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
275#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
276#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
Dan Williamse90ddd82007-05-02 17:59:44 +0100[diff] [blame]277#define IOP3XX_PCI_LOWER_IO_BA 0x90000000
Dan Williams6df26702007-02-13 17:11:04 +0100[diff] [blame]278#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\
279 IOP3XX_PCI_IO_WINDOW_SIZE - 1)
280#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\
281 IOP3XX_PCI_IO_WINDOW_SIZE - 1)
282#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) addr -\
283 IOP3XX_PCI_LOWER_IO_PA) +\
284 IOP3XX_PCI_LOWER_IO_VA)
Lennert Buytenhek7ae1f7e2006-09-18 23:12:53 +0100[diff] [blame]285
286
287#ifndef __ASSEMBLY__
288void iop3xx_map_io(void);
Dan Williams588ef762007-02-13 17:12:04 +0100[diff] [blame]289void iop_init_cp6_handler(void);
Dan Williams3668b452007-02-13 17:13:34 +0100[diff] [blame]290void iop_init_time(unsigned long tickrate);
291unsigned long iop_gettimeoffset(void);
292
293static inline void write_tmr0(u32 val)
294{
295 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
296}
297
298static inline void write_tmr1(u32 val)
299{
300 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
301}
302
303static inline u32 read_tcr0(void)
304{
305 u32 val;
306 asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
307 return val;
308}
309
310static inline u32 read_tcr1(void)
311{
312 u32 val;
313 asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
314 return val;
315}
316
317static inline void write_trr0(u32 val)
318{
319 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
320}
321
322static inline void write_trr1(u32 val)
323{
324 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
325}
326
327static inline void write_tisr(u32 val)
328{
329 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
330}
Lennert Buytenheke25d64f2006-09-18 23:15:21 +0100[diff] [blame]331
332extern struct platform_device iop3xx_i2c0_device;
333extern struct platform_device iop3xx_i2c1_device;
Lennert Buytenhek0b29de42006-09-18 23:20:55 +0100[diff] [blame]334
Lennert Buytenhek7ae1f7e2006-09-18 23:12:53 +0100[diff] [blame]335#endif
336
337
338#endif