Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1 | /* |
| 2 | * drivers/spi/spi-fsl-dspi.c |
| 3 | * |
| 4 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 5 | * |
| 6 | * Freescale DSPI driver |
| 7 | * This file contains a driver for the Freescale DSPI |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | */ |
| 15 | |
Xiubo Li | a310836 | 2014-09-29 10:57:06 +0800 | [diff] [blame] | 16 | #include <linux/clk.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/errno.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/io.h> |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 22 | #include <linux/kernel.h> |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 23 | #include <linux/math64.h> |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 24 | #include <linux/module.h> |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 25 | #include <linux/of.h> |
| 26 | #include <linux/of_device.h> |
Mirza Krak | 432a17d | 2015-06-12 18:55:22 +0200 | [diff] [blame] | 27 | #include <linux/pinctrl/consumer.h> |
Xiubo Li | a310836 | 2014-09-29 10:57:06 +0800 | [diff] [blame] | 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/pm_runtime.h> |
| 30 | #include <linux/regmap.h> |
| 31 | #include <linux/sched.h> |
| 32 | #include <linux/spi/spi.h> |
| 33 | #include <linux/spi/spi_bitbang.h> |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 34 | #include <linux/time.h> |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 35 | |
| 36 | #define DRIVER_NAME "fsl-dspi" |
| 37 | |
| 38 | #define TRAN_STATE_RX_VOID 0x01 |
| 39 | #define TRAN_STATE_TX_VOID 0x02 |
| 40 | #define TRAN_STATE_WORD_ODD_NUM 0x04 |
| 41 | |
| 42 | #define DSPI_FIFO_SIZE 4 |
| 43 | |
| 44 | #define SPI_MCR 0x00 |
| 45 | #define SPI_MCR_MASTER (1 << 31) |
| 46 | #define SPI_MCR_PCSIS (0x3F << 16) |
| 47 | #define SPI_MCR_CLR_TXF (1 << 11) |
| 48 | #define SPI_MCR_CLR_RXF (1 << 10) |
| 49 | |
| 50 | #define SPI_TCR 0x08 |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 51 | #define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 52 | |
Alexander Stein | 5cc7b04 | 2014-11-04 09:20:18 +0100 | [diff] [blame] | 53 | #define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4)) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 54 | #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) |
| 55 | #define SPI_CTAR_CPOL(x) ((x) << 26) |
| 56 | #define SPI_CTAR_CPHA(x) ((x) << 25) |
| 57 | #define SPI_CTAR_LSBFE(x) ((x) << 24) |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 58 | #define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 59 | #define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20) |
| 60 | #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18) |
| 61 | #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16) |
| 62 | #define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12) |
| 63 | #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8) |
| 64 | #define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4) |
| 65 | #define SPI_CTAR_BR(x) ((x) & 0x0000000f) |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 66 | #define SPI_CTAR_SCALE_BITS 0xf |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 67 | |
| 68 | #define SPI_CTAR0_SLAVE 0x0c |
| 69 | |
| 70 | #define SPI_SR 0x2c |
| 71 | #define SPI_SR_EOQF 0x10000000 |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 72 | #define SPI_SR_TCFQF 0x80000000 |
Angelo Dureghello | 750c4f0 | 2018-12-26 22:45:06 +0100 | [diff] [blame] | 73 | #define SPI_SR_CLEAR 0x9aaf0000 |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 74 | |
| 75 | #define SPI_RSER 0x30 |
| 76 | #define SPI_RSER_EOQFE 0x10000000 |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 77 | #define SPI_RSER_TCFQE 0x80000000 |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 78 | |
| 79 | #define SPI_PUSHR 0x34 |
| 80 | #define SPI_PUSHR_CONT (1 << 31) |
Alexander Stein | 5cc7b04 | 2014-11-04 09:20:18 +0100 | [diff] [blame] | 81 | #define SPI_PUSHR_CTAS(x) (((x) & 0x00000003) << 28) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 82 | #define SPI_PUSHR_EOQ (1 << 27) |
| 83 | #define SPI_PUSHR_CTCNT (1 << 26) |
| 84 | #define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16) |
| 85 | #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff) |
| 86 | |
| 87 | #define SPI_PUSHR_SLAVE 0x34 |
| 88 | |
| 89 | #define SPI_POPR 0x38 |
| 90 | #define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff) |
| 91 | |
| 92 | #define SPI_TXFR0 0x3c |
| 93 | #define SPI_TXFR1 0x40 |
| 94 | #define SPI_TXFR2 0x44 |
| 95 | #define SPI_TXFR3 0x48 |
| 96 | #define SPI_RXFR0 0x7c |
| 97 | #define SPI_RXFR1 0x80 |
| 98 | #define SPI_RXFR2 0x84 |
| 99 | #define SPI_RXFR3 0x88 |
| 100 | |
| 101 | #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) |
| 102 | #define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf) |
| 103 | #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf) |
| 104 | #define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7) |
| 105 | |
| 106 | #define SPI_CS_INIT 0x01 |
| 107 | #define SPI_CS_ASSERT 0x02 |
| 108 | #define SPI_CS_DROP 0x04 |
| 109 | |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 110 | #define SPI_TCR_TCNT_MAX 0x10000 |
| 111 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 112 | struct chip_data { |
| 113 | u32 mcr_val; |
| 114 | u32 ctar_val; |
| 115 | u16 void_write_data; |
| 116 | }; |
| 117 | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 118 | enum dspi_trans_mode { |
| 119 | DSPI_EOQ_MODE = 0, |
| 120 | DSPI_TCFQ_MODE, |
| 121 | }; |
| 122 | |
| 123 | struct fsl_dspi_devtype_data { |
| 124 | enum dspi_trans_mode trans_mode; |
Bhuvanchandra DV | 9419b20 | 2016-03-22 01:41:52 +0530 | [diff] [blame] | 125 | u8 max_clock_factor; |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 126 | }; |
| 127 | |
| 128 | static const struct fsl_dspi_devtype_data vf610_data = { |
| 129 | .trans_mode = DSPI_EOQ_MODE, |
Bhuvanchandra DV | 9419b20 | 2016-03-22 01:41:52 +0530 | [diff] [blame] | 130 | .max_clock_factor = 2, |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 131 | }; |
| 132 | |
| 133 | static const struct fsl_dspi_devtype_data ls1021a_v1_data = { |
| 134 | .trans_mode = DSPI_TCFQ_MODE, |
Bhuvanchandra DV | 9419b20 | 2016-03-22 01:41:52 +0530 | [diff] [blame] | 135 | .max_clock_factor = 8, |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 136 | }; |
| 137 | |
| 138 | static const struct fsl_dspi_devtype_data ls2085a_data = { |
| 139 | .trans_mode = DSPI_TCFQ_MODE, |
Bhuvanchandra DV | 9419b20 | 2016-03-22 01:41:52 +0530 | [diff] [blame] | 140 | .max_clock_factor = 8, |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 141 | }; |
| 142 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 143 | struct fsl_dspi { |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 144 | struct spi_master *master; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 145 | struct platform_device *pdev; |
| 146 | |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 147 | struct regmap *regmap; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 148 | int irq; |
Chao Fu | 88386e8 | 2014-02-12 15:29:06 +0800 | [diff] [blame] | 149 | struct clk *clk; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 150 | |
Chao Fu | 88386e8 | 2014-02-12 15:29:06 +0800 | [diff] [blame] | 151 | struct spi_transfer *cur_transfer; |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 152 | struct spi_message *cur_msg; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 153 | struct chip_data *cur_chip; |
| 154 | size_t len; |
| 155 | void *tx; |
| 156 | void *tx_end; |
| 157 | void *rx; |
| 158 | void *rx_end; |
| 159 | char dataflags; |
| 160 | u8 cs; |
| 161 | u16 void_write_data; |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 162 | u32 cs_change; |
LABBE Corentin | 94b968b | 2016-08-16 11:50:20 +0200 | [diff] [blame] | 163 | const struct fsl_dspi_devtype_data *devtype_data; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 164 | |
Chao Fu | 88386e8 | 2014-02-12 15:29:06 +0800 | [diff] [blame] | 165 | wait_queue_head_t waitq; |
| 166 | u32 waitflags; |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 167 | |
| 168 | u32 spi_tcnt; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 169 | }; |
| 170 | |
| 171 | static inline int is_double_byte_mode(struct fsl_dspi *dspi) |
| 172 | { |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 173 | unsigned int val; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 174 | |
Bhuvanchandra DV | ef22d16 | 2015-12-10 11:25:30 +0530 | [diff] [blame] | 175 | regmap_read(dspi->regmap, SPI_CTAR(0), &val); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 176 | |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 177 | return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, |
| 181 | unsigned long clkrate) |
| 182 | { |
| 183 | /* Valid baud rate pre-scaler values */ |
| 184 | int pbr_tbl[4] = {2, 3, 5, 7}; |
| 185 | int brs[16] = { 2, 4, 6, 8, |
| 186 | 16, 32, 64, 128, |
| 187 | 256, 512, 1024, 2048, |
| 188 | 4096, 8192, 16384, 32768 }; |
Aaron Brice | 6fd6308 | 2015-03-30 10:49:15 -0700 | [diff] [blame] | 189 | int scale_needed, scale, minscale = INT_MAX; |
| 190 | int i, j; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 191 | |
Aaron Brice | 6fd6308 | 2015-03-30 10:49:15 -0700 | [diff] [blame] | 192 | scale_needed = clkrate / speed_hz; |
Aaron Brice | e689d6d | 2015-04-03 13:39:29 -0700 | [diff] [blame] | 193 | if (clkrate % speed_hz) |
| 194 | scale_needed++; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 195 | |
Aaron Brice | 6fd6308 | 2015-03-30 10:49:15 -0700 | [diff] [blame] | 196 | for (i = 0; i < ARRAY_SIZE(brs); i++) |
| 197 | for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) { |
| 198 | scale = brs[i] * pbr_tbl[j]; |
| 199 | if (scale >= scale_needed) { |
| 200 | if (scale < minscale) { |
| 201 | minscale = scale; |
| 202 | *br = i; |
| 203 | *pbr = j; |
| 204 | } |
| 205 | break; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 206 | } |
| 207 | } |
| 208 | |
Aaron Brice | 6fd6308 | 2015-03-30 10:49:15 -0700 | [diff] [blame] | 209 | if (minscale == INT_MAX) { |
| 210 | pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n", |
| 211 | speed_hz, clkrate); |
| 212 | *pbr = ARRAY_SIZE(pbr_tbl) - 1; |
| 213 | *br = ARRAY_SIZE(brs) - 1; |
| 214 | } |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 215 | } |
| 216 | |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 217 | static void ns_delay_scale(char *psc, char *sc, int delay_ns, |
| 218 | unsigned long clkrate) |
| 219 | { |
| 220 | int pscale_tbl[4] = {1, 3, 5, 7}; |
| 221 | int scale_needed, scale, minscale = INT_MAX; |
| 222 | int i, j; |
| 223 | u32 remainder; |
| 224 | |
| 225 | scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, |
| 226 | &remainder); |
| 227 | if (remainder) |
| 228 | scale_needed++; |
| 229 | |
| 230 | for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++) |
| 231 | for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) { |
| 232 | scale = pscale_tbl[i] * (2 << j); |
| 233 | if (scale >= scale_needed) { |
| 234 | if (scale < minscale) { |
| 235 | minscale = scale; |
| 236 | *psc = i; |
| 237 | *sc = j; |
| 238 | } |
| 239 | break; |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | if (minscale == INT_MAX) { |
| 244 | pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value", |
| 245 | delay_ns, clkrate); |
| 246 | *psc = ARRAY_SIZE(pscale_tbl) - 1; |
| 247 | *sc = SPI_CTAR_SCALE_BITS; |
| 248 | } |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 249 | } |
| 250 | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 251 | static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word) |
| 252 | { |
| 253 | u16 d16; |
| 254 | |
| 255 | if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) |
| 256 | d16 = tx_word ? *(u16 *)dspi->tx : *(u8 *)dspi->tx; |
| 257 | else |
| 258 | d16 = dspi->void_write_data; |
| 259 | |
| 260 | dspi->tx += tx_word + 1; |
| 261 | dspi->len -= tx_word + 1; |
| 262 | |
| 263 | return SPI_PUSHR_TXDATA(d16) | |
| 264 | SPI_PUSHR_PCS(dspi->cs) | |
Bhuvanchandra DV | ef22d16 | 2015-12-10 11:25:30 +0530 | [diff] [blame] | 265 | SPI_PUSHR_CTAS(0) | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 266 | SPI_PUSHR_CONT; |
| 267 | } |
| 268 | |
| 269 | static void dspi_data_from_popr(struct fsl_dspi *dspi, int rx_word) |
| 270 | { |
| 271 | u16 d; |
| 272 | unsigned int val; |
| 273 | |
| 274 | regmap_read(dspi->regmap, SPI_POPR, &val); |
| 275 | d = SPI_POPR_RXDATA(val); |
| 276 | |
| 277 | if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) |
| 278 | rx_word ? (*(u16 *)dspi->rx = d) : (*(u8 *)dspi->rx = d); |
| 279 | |
| 280 | dspi->rx += rx_word + 1; |
| 281 | } |
| 282 | |
| 283 | static int dspi_eoq_write(struct fsl_dspi *dspi) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 284 | { |
| 285 | int tx_count = 0; |
| 286 | int tx_word; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 287 | u32 dspi_pushr = 0; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 288 | |
| 289 | tx_word = is_double_byte_mode(dspi); |
| 290 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 291 | while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) { |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 292 | /* If we are in word mode, only have a single byte to transfer |
| 293 | * switch to byte mode temporarily. Will switch back at the |
| 294 | * end of the transfer. |
| 295 | */ |
| 296 | if (tx_word && (dspi->len == 1)) { |
| 297 | dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; |
Bhuvanchandra DV | ef22d16 | 2015-12-10 11:25:30 +0530 | [diff] [blame] | 298 | regmap_update_bits(dspi->regmap, SPI_CTAR(0), |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 299 | SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8)); |
| 300 | tx_word = 0; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 301 | } |
| 302 | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 303 | dspi_pushr = dspi_data_to_pushr(dspi, tx_word); |
| 304 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 305 | if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) { |
| 306 | /* last transfer in the transfer */ |
| 307 | dspi_pushr |= SPI_PUSHR_EOQ; |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 308 | if ((dspi->cs_change) && (!dspi->len)) |
| 309 | dspi_pushr &= ~SPI_PUSHR_CONT; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 310 | } else if (tx_word && (dspi->len == 1)) |
| 311 | dspi_pushr |= SPI_PUSHR_EOQ; |
| 312 | |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 313 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr); |
| 314 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 315 | tx_count++; |
| 316 | } |
| 317 | |
| 318 | return tx_count * (tx_word + 1); |
| 319 | } |
| 320 | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 321 | static int dspi_eoq_read(struct fsl_dspi *dspi) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 322 | { |
| 323 | int rx_count = 0; |
| 324 | int rx_word = is_double_byte_mode(dspi); |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 325 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 326 | while ((dspi->rx < dspi->rx_end) |
| 327 | && (rx_count < DSPI_FIFO_SIZE)) { |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 328 | if (rx_word && (dspi->rx_end - dspi->rx) == 1) |
| 329 | rx_word = 0; |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 330 | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 331 | dspi_data_from_popr(dspi, rx_word); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 332 | rx_count++; |
| 333 | } |
| 334 | |
| 335 | return rx_count; |
| 336 | } |
| 337 | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 338 | static int dspi_tcfq_write(struct fsl_dspi *dspi) |
| 339 | { |
| 340 | int tx_word; |
| 341 | u32 dspi_pushr = 0; |
| 342 | |
| 343 | tx_word = is_double_byte_mode(dspi); |
| 344 | |
| 345 | if (tx_word && (dspi->len == 1)) { |
| 346 | dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; |
Bhuvanchandra DV | ef22d16 | 2015-12-10 11:25:30 +0530 | [diff] [blame] | 347 | regmap_update_bits(dspi->regmap, SPI_CTAR(0), |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 348 | SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8)); |
| 349 | tx_word = 0; |
| 350 | } |
| 351 | |
| 352 | dspi_pushr = dspi_data_to_pushr(dspi, tx_word); |
| 353 | |
| 354 | if ((dspi->cs_change) && (!dspi->len)) |
| 355 | dspi_pushr &= ~SPI_PUSHR_CONT; |
| 356 | |
| 357 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr); |
| 358 | |
| 359 | return tx_word + 1; |
| 360 | } |
| 361 | |
| 362 | static void dspi_tcfq_read(struct fsl_dspi *dspi) |
| 363 | { |
| 364 | int rx_word = is_double_byte_mode(dspi); |
| 365 | |
| 366 | if (rx_word && (dspi->rx_end - dspi->rx) == 1) |
| 367 | rx_word = 0; |
| 368 | |
| 369 | dspi_data_from_popr(dspi, rx_word); |
| 370 | } |
| 371 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 372 | static int dspi_transfer_one_message(struct spi_master *master, |
| 373 | struct spi_message *message) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 374 | { |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 375 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
| 376 | struct spi_device *spi = message->spi; |
| 377 | struct spi_transfer *transfer; |
| 378 | int status = 0; |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 379 | enum dspi_trans_mode trans_mode; |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 380 | u32 spi_tcr; |
| 381 | |
| 382 | regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); |
| 383 | dspi->spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 384 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 385 | message->actual_length = 0; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 386 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 387 | list_for_each_entry(transfer, &message->transfers, transfer_list) { |
| 388 | dspi->cur_transfer = transfer; |
| 389 | dspi->cur_msg = message; |
| 390 | dspi->cur_chip = spi_get_ctldata(spi); |
| 391 | dspi->cs = spi->chip_select; |
Haikun Wang | 9deef02 | 2015-05-13 18:12:15 +0800 | [diff] [blame] | 392 | dspi->cs_change = 0; |
Andrey Vostrikov | 92dc20d | 2016-04-05 15:33:14 +0300 | [diff] [blame] | 393 | if (list_is_last(&dspi->cur_transfer->transfer_list, |
| 394 | &dspi->cur_msg->transfers) || transfer->cs_change) |
Haikun Wang | 9deef02 | 2015-05-13 18:12:15 +0800 | [diff] [blame] | 395 | dspi->cs_change = 1; |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 396 | dspi->void_write_data = dspi->cur_chip->void_write_data; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 397 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 398 | dspi->dataflags = 0; |
| 399 | dspi->tx = (void *)transfer->tx_buf; |
| 400 | dspi->tx_end = dspi->tx + transfer->len; |
| 401 | dspi->rx = transfer->rx_buf; |
| 402 | dspi->rx_end = dspi->rx + transfer->len; |
| 403 | dspi->len = transfer->len; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 404 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 405 | if (!dspi->rx) |
| 406 | dspi->dataflags |= TRAN_STATE_RX_VOID; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 407 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 408 | if (!dspi->tx) |
| 409 | dspi->dataflags |= TRAN_STATE_TX_VOID; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 410 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 411 | regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val); |
| 412 | regmap_update_bits(dspi->regmap, SPI_MCR, |
| 413 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, |
| 414 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); |
Bhuvanchandra DV | ef22d16 | 2015-12-10 11:25:30 +0530 | [diff] [blame] | 415 | regmap_write(dspi->regmap, SPI_CTAR(0), |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 416 | dspi->cur_chip->ctar_val); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 417 | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 418 | trans_mode = dspi->devtype_data->trans_mode; |
| 419 | switch (trans_mode) { |
| 420 | case DSPI_EOQ_MODE: |
| 421 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 422 | dspi_eoq_write(dspi); |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 423 | break; |
| 424 | case DSPI_TCFQ_MODE: |
| 425 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE); |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 426 | dspi_tcfq_write(dspi); |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 427 | break; |
| 428 | default: |
| 429 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", |
| 430 | trans_mode); |
| 431 | status = -EINVAL; |
| 432 | goto out; |
| 433 | } |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 434 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 435 | if (wait_event_interruptible(dspi->waitq, dspi->waitflags)) |
| 436 | dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n"); |
| 437 | dspi->waitflags = 0; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 438 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 439 | if (transfer->delay_usecs) |
| 440 | udelay(transfer->delay_usecs); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 441 | } |
| 442 | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 443 | out: |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 444 | message->status = status; |
| 445 | spi_finalize_current_message(master); |
| 446 | |
| 447 | return status; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 448 | } |
| 449 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 450 | static int dspi_setup(struct spi_device *spi) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 451 | { |
| 452 | struct chip_data *chip; |
| 453 | struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 454 | u32 cs_sck_delay = 0, sck_cs_delay = 0; |
| 455 | unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0; |
| 456 | unsigned char pasc = 0, asc = 0, fmsz = 0; |
| 457 | unsigned long clkrate; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 458 | |
Bhuvanchandra DV | ceadfd8 | 2015-01-31 22:03:25 +0530 | [diff] [blame] | 459 | if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) { |
| 460 | fmsz = spi->bits_per_word - 1; |
| 461 | } else { |
| 462 | pr_err("Invalid wordsize\n"); |
| 463 | return -ENODEV; |
| 464 | } |
| 465 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 466 | /* Only alloc on first setup */ |
| 467 | chip = spi_get_ctldata(spi); |
| 468 | if (chip == NULL) { |
Bhuvanchandra DV | 973fbce | 2015-01-27 16:27:20 +0530 | [diff] [blame] | 469 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 470 | if (!chip) |
| 471 | return -ENOMEM; |
| 472 | } |
| 473 | |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 474 | of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay", |
| 475 | &cs_sck_delay); |
| 476 | |
| 477 | of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay", |
| 478 | &sck_cs_delay); |
| 479 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 480 | chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS | |
| 481 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 482 | |
| 483 | chip->void_write_data = 0; |
| 484 | |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 485 | clkrate = clk_get_rate(dspi->clk); |
| 486 | hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); |
| 487 | |
| 488 | /* Set PCS to SCK delay scale values */ |
| 489 | ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate); |
| 490 | |
| 491 | /* Set After SCK delay scale values */ |
| 492 | ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 493 | |
| 494 | chip->ctar_val = SPI_CTAR_FMSZ(fmsz) |
| 495 | | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0) |
| 496 | | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0) |
| 497 | | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0) |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 498 | | SPI_CTAR_PCSSCK(pcssck) |
| 499 | | SPI_CTAR_CSSCK(cssck) |
| 500 | | SPI_CTAR_PASC(pasc) |
| 501 | | SPI_CTAR_ASC(asc) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 502 | | SPI_CTAR_PBR(pbr) |
| 503 | | SPI_CTAR_BR(br); |
| 504 | |
| 505 | spi_set_ctldata(spi, chip); |
| 506 | |
| 507 | return 0; |
| 508 | } |
| 509 | |
Bhuvanchandra DV | 973fbce | 2015-01-27 16:27:20 +0530 | [diff] [blame] | 510 | static void dspi_cleanup(struct spi_device *spi) |
| 511 | { |
| 512 | struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); |
| 513 | |
| 514 | dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", |
| 515 | spi->master->bus_num, spi->chip_select); |
| 516 | |
| 517 | kfree(chip); |
| 518 | } |
| 519 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 520 | static irqreturn_t dspi_interrupt(int irq, void *dev_id) |
| 521 | { |
| 522 | struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 523 | struct spi_message *msg = dspi->cur_msg; |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 524 | enum dspi_trans_mode trans_mode; |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 525 | u32 spi_sr, spi_tcr; |
| 526 | u32 spi_tcnt, tcnt_diff; |
| 527 | int tx_word; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 528 | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 529 | regmap_read(dspi->regmap, SPI_SR, &spi_sr); |
| 530 | regmap_write(dspi->regmap, SPI_SR, spi_sr); |
| 531 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 532 | |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 533 | if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) { |
| 534 | tx_word = is_double_byte_mode(dspi); |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 535 | |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 536 | regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); |
| 537 | spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); |
| 538 | /* |
| 539 | * The width of SPI Transfer Counter in SPI_TCR is 16bits, |
| 540 | * so the max couner is 65535. When the counter reach 65535, |
| 541 | * it will wrap around, counter reset to zero. |
| 542 | * spi_tcnt my be less than dspi->spi_tcnt, it means the |
| 543 | * counter already wrapped around. |
| 544 | * SPI Transfer Counter is a counter of transmitted frames. |
| 545 | * The size of frame maybe two bytes. |
| 546 | */ |
| 547 | tcnt_diff = ((spi_tcnt + SPI_TCR_TCNT_MAX) - dspi->spi_tcnt) |
| 548 | % SPI_TCR_TCNT_MAX; |
| 549 | tcnt_diff *= (tx_word + 1); |
| 550 | if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) |
| 551 | tcnt_diff--; |
| 552 | |
| 553 | msg->actual_length += tcnt_diff; |
| 554 | |
| 555 | dspi->spi_tcnt = spi_tcnt; |
| 556 | |
| 557 | trans_mode = dspi->devtype_data->trans_mode; |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 558 | switch (trans_mode) { |
| 559 | case DSPI_EOQ_MODE: |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 560 | dspi_eoq_read(dspi); |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 561 | break; |
| 562 | case DSPI_TCFQ_MODE: |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 563 | dspi_tcfq_read(dspi); |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 564 | break; |
| 565 | default: |
| 566 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", |
| 567 | trans_mode); |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 568 | return IRQ_HANDLED; |
| 569 | } |
| 570 | |
| 571 | if (!dspi->len) { |
| 572 | if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) { |
| 573 | regmap_update_bits(dspi->regmap, |
Bhuvanchandra DV | ef22d16 | 2015-12-10 11:25:30 +0530 | [diff] [blame] | 574 | SPI_CTAR(0), |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 575 | SPI_FRAME_BITS_MASK, |
| 576 | SPI_FRAME_BITS(16)); |
| 577 | dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM; |
| 578 | } |
| 579 | |
| 580 | dspi->waitflags = 1; |
| 581 | wake_up_interruptible(&dspi->waitq); |
| 582 | } else { |
| 583 | switch (trans_mode) { |
| 584 | case DSPI_EOQ_MODE: |
| 585 | dspi_eoq_write(dspi); |
| 586 | break; |
| 587 | case DSPI_TCFQ_MODE: |
| 588 | dspi_tcfq_write(dspi); |
| 589 | break; |
| 590 | default: |
| 591 | dev_err(&dspi->pdev->dev, |
| 592 | "unsupported trans_mode %u\n", |
| 593 | trans_mode); |
| 594 | } |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 595 | } |
| 596 | } |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 597 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 598 | return IRQ_HANDLED; |
| 599 | } |
| 600 | |
Jingoo Han | 790d190 | 2014-05-07 16:45:41 +0900 | [diff] [blame] | 601 | static const struct of_device_id fsl_dspi_dt_ids[] = { |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 602 | { .compatible = "fsl,vf610-dspi", .data = (void *)&vf610_data, }, |
| 603 | { .compatible = "fsl,ls1021a-v1.0-dspi", |
| 604 | .data = (void *)&ls1021a_v1_data, }, |
| 605 | { .compatible = "fsl,ls2085a-dspi", .data = (void *)&ls2085a_data, }, |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 606 | { /* sentinel */ } |
| 607 | }; |
| 608 | MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); |
| 609 | |
| 610 | #ifdef CONFIG_PM_SLEEP |
| 611 | static int dspi_suspend(struct device *dev) |
| 612 | { |
| 613 | struct spi_master *master = dev_get_drvdata(dev); |
| 614 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
| 615 | |
| 616 | spi_master_suspend(master); |
| 617 | clk_disable_unprepare(dspi->clk); |
| 618 | |
Mirza Krak | 432a17d | 2015-06-12 18:55:22 +0200 | [diff] [blame] | 619 | pinctrl_pm_select_sleep_state(dev); |
| 620 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 621 | return 0; |
| 622 | } |
| 623 | |
| 624 | static int dspi_resume(struct device *dev) |
| 625 | { |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 626 | struct spi_master *master = dev_get_drvdata(dev); |
| 627 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
Fabio Estevam | 1c5ea2b | 2016-08-21 23:05:30 -0300 | [diff] [blame] | 628 | int ret; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 629 | |
Mirza Krak | 432a17d | 2015-06-12 18:55:22 +0200 | [diff] [blame] | 630 | pinctrl_pm_select_default_state(dev); |
| 631 | |
Fabio Estevam | 1c5ea2b | 2016-08-21 23:05:30 -0300 | [diff] [blame] | 632 | ret = clk_prepare_enable(dspi->clk); |
| 633 | if (ret) |
| 634 | return ret; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 635 | spi_master_resume(master); |
| 636 | |
| 637 | return 0; |
| 638 | } |
| 639 | #endif /* CONFIG_PM_SLEEP */ |
| 640 | |
Jingoo Han | ba811ad | 2014-02-26 10:30:14 +0900 | [diff] [blame] | 641 | static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 642 | |
Xiubo Li | 409851c | 2014-10-09 11:27:45 +0800 | [diff] [blame] | 643 | static const struct regmap_config dspi_regmap_config = { |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 644 | .reg_bits = 32, |
| 645 | .val_bits = 32, |
| 646 | .reg_stride = 4, |
| 647 | .max_register = 0x88, |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 648 | }; |
| 649 | |
Yuan Yao | 5ee67b5 | 2016-10-17 18:02:34 +0800 | [diff] [blame] | 650 | static void dspi_init(struct fsl_dspi *dspi) |
| 651 | { |
| 652 | regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); |
| 653 | } |
| 654 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 655 | static int dspi_probe(struct platform_device *pdev) |
| 656 | { |
| 657 | struct device_node *np = pdev->dev.of_node; |
| 658 | struct spi_master *master; |
| 659 | struct fsl_dspi *dspi; |
| 660 | struct resource *res; |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 661 | void __iomem *base; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 662 | int ret = 0, cs_num, bus_num; |
| 663 | |
| 664 | master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); |
| 665 | if (!master) |
| 666 | return -ENOMEM; |
| 667 | |
| 668 | dspi = spi_master_get_devdata(master); |
| 669 | dspi->pdev = pdev; |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 670 | dspi->master = master; |
| 671 | |
| 672 | master->transfer = NULL; |
| 673 | master->setup = dspi_setup; |
| 674 | master->transfer_one_message = dspi_transfer_one_message; |
| 675 | master->dev.of_node = pdev->dev.of_node; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 676 | |
Bhuvanchandra DV | 973fbce | 2015-01-27 16:27:20 +0530 | [diff] [blame] | 677 | master->cleanup = dspi_cleanup; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 678 | master->mode_bits = SPI_CPOL | SPI_CPHA; |
| 679 | master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) | |
| 680 | SPI_BPW_MASK(16); |
| 681 | |
| 682 | ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); |
| 683 | if (ret < 0) { |
| 684 | dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); |
| 685 | goto out_master_put; |
| 686 | } |
| 687 | master->num_chipselect = cs_num; |
| 688 | |
| 689 | ret = of_property_read_u32(np, "bus-num", &bus_num); |
| 690 | if (ret < 0) { |
| 691 | dev_err(&pdev->dev, "can't get bus-num\n"); |
| 692 | goto out_master_put; |
| 693 | } |
| 694 | master->bus_num = bus_num; |
| 695 | |
LABBE Corentin | 53d8916 | 2016-08-16 11:50:21 +0200 | [diff] [blame] | 696 | dspi->devtype_data = of_device_get_match_data(&pdev->dev); |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 697 | if (!dspi->devtype_data) { |
| 698 | dev_err(&pdev->dev, "can't get devtype_data\n"); |
| 699 | ret = -EFAULT; |
| 700 | goto out_master_put; |
| 701 | } |
| 702 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 703 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 704 | base = devm_ioremap_resource(&pdev->dev, res); |
| 705 | if (IS_ERR(base)) { |
| 706 | ret = PTR_ERR(base); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 707 | goto out_master_put; |
| 708 | } |
| 709 | |
Haikun Wang | d223332 | 2015-04-24 18:54:47 +0800 | [diff] [blame] | 710 | dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 711 | &dspi_regmap_config); |
| 712 | if (IS_ERR(dspi->regmap)) { |
| 713 | dev_err(&pdev->dev, "failed to init regmap: %ld\n", |
| 714 | PTR_ERR(dspi->regmap)); |
| 715 | return PTR_ERR(dspi->regmap); |
| 716 | } |
| 717 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 718 | dspi->clk = devm_clk_get(&pdev->dev, "dspi"); |
| 719 | if (IS_ERR(dspi->clk)) { |
| 720 | ret = PTR_ERR(dspi->clk); |
| 721 | dev_err(&pdev->dev, "unable to get clock\n"); |
| 722 | goto out_master_put; |
| 723 | } |
Fabio Estevam | 1c5ea2b | 2016-08-21 23:05:30 -0300 | [diff] [blame] | 724 | ret = clk_prepare_enable(dspi->clk); |
| 725 | if (ret) |
| 726 | goto out_master_put; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 727 | |
Krzysztof Kozlowski | 9f16a87 | 2018-06-29 13:33:09 +0200 | [diff] [blame] | 728 | dspi_init(dspi); |
| 729 | dspi->irq = platform_get_irq(pdev, 0); |
| 730 | if (dspi->irq < 0) { |
| 731 | dev_err(&pdev->dev, "can't get platform irq\n"); |
| 732 | ret = dspi->irq; |
| 733 | goto out_clk_put; |
| 734 | } |
| 735 | |
| 736 | ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0, |
| 737 | pdev->name, dspi); |
| 738 | if (ret < 0) { |
| 739 | dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n"); |
| 740 | goto out_clk_put; |
| 741 | } |
| 742 | |
Bhuvanchandra DV | 9419b20 | 2016-03-22 01:41:52 +0530 | [diff] [blame] | 743 | master->max_speed_hz = |
| 744 | clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; |
| 745 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 746 | init_waitqueue_head(&dspi->waitq); |
Axel Lin | 017145f | 2014-02-14 12:49:12 +0800 | [diff] [blame] | 747 | platform_set_drvdata(pdev, master); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 748 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 749 | ret = spi_register_master(master); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 750 | if (ret != 0) { |
| 751 | dev_err(&pdev->dev, "Problem registering DSPI master\n"); |
| 752 | goto out_clk_put; |
| 753 | } |
| 754 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 755 | return ret; |
| 756 | |
| 757 | out_clk_put: |
| 758 | clk_disable_unprepare(dspi->clk); |
| 759 | out_master_put: |
| 760 | spi_master_put(master); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 761 | |
| 762 | return ret; |
| 763 | } |
| 764 | |
| 765 | static int dspi_remove(struct platform_device *pdev) |
| 766 | { |
Axel Lin | 017145f | 2014-02-14 12:49:12 +0800 | [diff] [blame] | 767 | struct spi_master *master = platform_get_drvdata(pdev); |
| 768 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 769 | |
| 770 | /* Disconnect from the SPI framework */ |
Wei Yongjun | 05209f4 | 2013-10-12 15:15:31 +0800 | [diff] [blame] | 771 | clk_disable_unprepare(dspi->clk); |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 772 | spi_unregister_master(dspi->master); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 773 | |
| 774 | return 0; |
| 775 | } |
| 776 | |
| 777 | static struct platform_driver fsl_dspi_driver = { |
| 778 | .driver.name = DRIVER_NAME, |
| 779 | .driver.of_match_table = fsl_dspi_dt_ids, |
| 780 | .driver.owner = THIS_MODULE, |
| 781 | .driver.pm = &dspi_pm, |
| 782 | .probe = dspi_probe, |
| 783 | .remove = dspi_remove, |
| 784 | }; |
| 785 | module_platform_driver(fsl_dspi_driver); |
| 786 | |
| 787 | MODULE_DESCRIPTION("Freescale DSPI Controller Driver"); |
Uwe Kleine-König | b444d1d | 2013-09-10 10:46:33 +0200 | [diff] [blame] | 788 | MODULE_LICENSE("GPL"); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 789 | MODULE_ALIAS("platform:" DRIVER_NAME); |