Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 1 | /* |
Eric Miao | 38f539a | 2009-01-20 12:09:06 +0800 | [diff] [blame] | 2 | * linux/arch/arm/plat-pxa/gpio.c |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 3 | * |
| 4 | * Generic PXA GPIO handling |
| 5 | * |
| 6 | * Author: Nicolas Pitre |
| 7 | * Created: Jun 15, 2001 |
| 8 | * Copyright: MontaVista Software Inc. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 14 | #include <linux/module.h> |
Haojian Zhuang | 389eda1 | 2011-10-17 21:26:55 +0800 | [diff] [blame] | 15 | #include <linux/clk.h> |
| 16 | #include <linux/err.h> |
Russell King | 2f8163b | 2011-07-26 10:53:52 +0100 | [diff] [blame] | 17 | #include <linux/gpio.h> |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 18 | #include <linux/gpio-pxa.h> |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 19 | #include <linux/init.h> |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 20 | #include <linux/irq.h> |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 21 | #include <linux/irqdomain.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 22 | #include <linux/io.h> |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 23 | #include <linux/of.h> |
| 24 | #include <linux/of_device.h> |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 25 | #include <linux/platform_device.h> |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 26 | #include <linux/syscore_ops.h> |
Daniel Mack | 4aa7826 | 2009-06-19 22:56:09 +0200 | [diff] [blame] | 27 | #include <linux/slab.h> |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 28 | |
Rob Herring | feefe73 | 2012-01-03 15:52:42 -0600 | [diff] [blame] | 29 | #include <mach/irqs.h> |
| 30 | |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 31 | /* |
| 32 | * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with |
| 33 | * one set of registers. The register offsets are organized below: |
| 34 | * |
| 35 | * GPLR GPDR GPSR GPCR GRER GFER GEDR |
| 36 | * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 |
| 37 | * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C |
| 38 | * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 |
| 39 | * |
| 40 | * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 |
| 41 | * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C |
| 42 | * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 |
| 43 | * |
| 44 | * NOTE: |
| 45 | * BANK 3 is only available on PXA27x and later processors. |
| 46 | * BANK 4 and 5 are only available on PXA935 |
| 47 | */ |
| 48 | |
| 49 | #define GPLR_OFFSET 0x00 |
| 50 | #define GPDR_OFFSET 0x0C |
| 51 | #define GPSR_OFFSET 0x18 |
| 52 | #define GPCR_OFFSET 0x24 |
| 53 | #define GRER_OFFSET 0x30 |
| 54 | #define GFER_OFFSET 0x3C |
| 55 | #define GEDR_OFFSET 0x48 |
| 56 | #define GAFR_OFFSET 0x54 |
Haojian Zhuang | be24168 | 2011-10-17 21:07:15 +0800 | [diff] [blame] | 57 | #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 58 | |
| 59 | #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 60 | |
Eric Miao | 3b8e285 | 2009-01-07 11:30:49 +0800 | [diff] [blame] | 61 | int pxa_last_gpio; |
Daniel Mack | 9450be7 | 2012-07-22 16:55:44 +0200 | [diff] [blame^] | 62 | static int irq_base; |
Eric Miao | 3b8e285 | 2009-01-07 11:30:49 +0800 | [diff] [blame] | 63 | |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 64 | #ifdef CONFIG_OF |
| 65 | static struct irq_domain *domain; |
| 66 | #endif |
| 67 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 68 | struct pxa_gpio_chip { |
| 69 | struct gpio_chip chip; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 70 | void __iomem *regbase; |
| 71 | char label[10]; |
| 72 | |
| 73 | unsigned long irq_mask; |
| 74 | unsigned long irq_edge_rise; |
| 75 | unsigned long irq_edge_fall; |
Robert Jarzmik | b95ace5 | 2012-04-22 13:37:24 +0200 | [diff] [blame] | 76 | int (*set_wake)(unsigned int gpio, unsigned int on); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 77 | |
| 78 | #ifdef CONFIG_PM |
| 79 | unsigned long saved_gplr; |
| 80 | unsigned long saved_gpdr; |
| 81 | unsigned long saved_grer; |
| 82 | unsigned long saved_gfer; |
| 83 | #endif |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 84 | }; |
| 85 | |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 86 | enum { |
| 87 | PXA25X_GPIO = 0, |
| 88 | PXA26X_GPIO, |
| 89 | PXA27X_GPIO, |
| 90 | PXA3XX_GPIO, |
| 91 | PXA93X_GPIO, |
| 92 | MMP_GPIO = 0x10, |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 93 | }; |
| 94 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 95 | static DEFINE_SPINLOCK(gpio_lock); |
| 96 | static struct pxa_gpio_chip *pxa_gpio_chips; |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 97 | static int gpio_type; |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 98 | static void __iomem *gpio_reg_base; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 99 | |
| 100 | #define for_each_gpio_chip(i, c) \ |
| 101 | for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) |
| 102 | |
| 103 | static inline void __iomem *gpio_chip_base(struct gpio_chip *c) |
| 104 | { |
| 105 | return container_of(c, struct pxa_gpio_chip, chip)->regbase; |
| 106 | } |
| 107 | |
Linus Walleij | a065685 | 2011-06-13 10:42:19 +0200 | [diff] [blame] | 108 | static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio) |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 109 | { |
| 110 | return &pxa_gpio_chips[gpio_to_bank(gpio)]; |
| 111 | } |
| 112 | |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 113 | static inline int gpio_is_pxa_type(int type) |
| 114 | { |
| 115 | return (type & MMP_GPIO) == 0; |
| 116 | } |
| 117 | |
| 118 | static inline int gpio_is_mmp_type(int type) |
| 119 | { |
| 120 | return (type & MMP_GPIO) != 0; |
| 121 | } |
| 122 | |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 123 | /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, |
| 124 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. |
| 125 | */ |
| 126 | static inline int __gpio_is_inverted(int gpio) |
| 127 | { |
| 128 | if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) |
| 129 | return 1; |
| 130 | return 0; |
| 131 | } |
| 132 | |
| 133 | /* |
| 134 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate |
| 135 | * function of a GPIO, and GPDRx cannot be altered once configured. It |
| 136 | * is attributed as "occupied" here (I know this terminology isn't |
| 137 | * accurate, you are welcome to propose a better one :-) |
| 138 | */ |
| 139 | static inline int __gpio_is_occupied(unsigned gpio) |
| 140 | { |
| 141 | struct pxa_gpio_chip *pxachip; |
| 142 | void __iomem *base; |
| 143 | unsigned long gafr = 0, gpdr = 0; |
| 144 | int ret, af = 0, dir = 0; |
| 145 | |
| 146 | pxachip = gpio_to_pxachip(gpio); |
| 147 | base = gpio_chip_base(&pxachip->chip); |
| 148 | gpdr = readl_relaxed(base + GPDR_OFFSET); |
| 149 | |
| 150 | switch (gpio_type) { |
| 151 | case PXA25X_GPIO: |
| 152 | case PXA26X_GPIO: |
| 153 | case PXA27X_GPIO: |
| 154 | gafr = readl_relaxed(base + GAFR_OFFSET); |
| 155 | af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; |
| 156 | dir = gpdr & GPIO_bit(gpio); |
| 157 | |
| 158 | if (__gpio_is_inverted(gpio)) |
| 159 | ret = (af != 1) || (dir == 0); |
| 160 | else |
| 161 | ret = (af != 0) || (dir != 0); |
| 162 | break; |
| 163 | default: |
| 164 | ret = gpdr & GPIO_bit(gpio); |
| 165 | break; |
| 166 | } |
| 167 | return ret; |
| 168 | } |
| 169 | |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 170 | static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
| 171 | { |
Daniel Mack | 9450be7 | 2012-07-22 16:55:44 +0200 | [diff] [blame^] | 172 | return chip->base + offset + irq_base; |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | int pxa_irq_to_gpio(int irq) |
| 176 | { |
Daniel Mack | 9450be7 | 2012-07-22 16:55:44 +0200 | [diff] [blame^] | 177 | return irq - irq_base; |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 178 | } |
| 179 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 180 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 181 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 182 | void __iomem *base = gpio_chip_base(chip); |
| 183 | uint32_t value, mask = 1 << offset; |
| 184 | unsigned long flags; |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 185 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 186 | spin_lock_irqsave(&gpio_lock, flags); |
| 187 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 188 | value = readl_relaxed(base + GPDR_OFFSET); |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 189 | if (__gpio_is_inverted(chip->base + offset)) |
| 190 | value |= mask; |
| 191 | else |
| 192 | value &= ~mask; |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 193 | writel_relaxed(value, base + GPDR_OFFSET); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 194 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 195 | spin_unlock_irqrestore(&gpio_lock, flags); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 196 | return 0; |
| 197 | } |
| 198 | |
| 199 | static int pxa_gpio_direction_output(struct gpio_chip *chip, |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 200 | unsigned offset, int value) |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 201 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 202 | void __iomem *base = gpio_chip_base(chip); |
| 203 | uint32_t tmp, mask = 1 << offset; |
| 204 | unsigned long flags; |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 205 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 206 | writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 207 | |
| 208 | spin_lock_irqsave(&gpio_lock, flags); |
| 209 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 210 | tmp = readl_relaxed(base + GPDR_OFFSET); |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 211 | if (__gpio_is_inverted(chip->base + offset)) |
| 212 | tmp &= ~mask; |
| 213 | else |
| 214 | tmp |= mask; |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 215 | writel_relaxed(tmp, base + GPDR_OFFSET); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 216 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 217 | spin_unlock_irqrestore(&gpio_lock, flags); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 218 | return 0; |
| 219 | } |
| 220 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 221 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 222 | { |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 223 | return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 224 | } |
| 225 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 226 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 227 | { |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 228 | writel_relaxed(1 << offset, gpio_chip_base(chip) + |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 229 | (value ? GPSR_OFFSET : GPCR_OFFSET)); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 230 | } |
| 231 | |
Robert Jarzmik | b95ace5 | 2012-04-22 13:37:24 +0200 | [diff] [blame] | 232 | static int __devinit pxa_init_gpio_chip(int gpio_end, |
| 233 | int (*set_wake)(unsigned int, unsigned int)) |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 234 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 235 | int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; |
| 236 | struct pxa_gpio_chip *chips; |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 237 | |
Daniel Mack | 4aa7826 | 2009-06-19 22:56:09 +0200 | [diff] [blame] | 238 | chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 239 | if (chips == NULL) { |
| 240 | pr_err("%s: failed to allocate GPIO chips\n", __func__); |
| 241 | return -ENOMEM; |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 242 | } |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 243 | |
| 244 | for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { |
| 245 | struct gpio_chip *c = &chips[i].chip; |
| 246 | |
| 247 | sprintf(chips[i].label, "gpio-%d", i); |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 248 | chips[i].regbase = gpio_reg_base + BANK_OFF(i); |
Robert Jarzmik | b95ace5 | 2012-04-22 13:37:24 +0200 | [diff] [blame] | 249 | chips[i].set_wake = set_wake; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 250 | |
| 251 | c->base = gpio; |
| 252 | c->label = chips[i].label; |
| 253 | |
| 254 | c->direction_input = pxa_gpio_direction_input; |
| 255 | c->direction_output = pxa_gpio_direction_output; |
| 256 | c->get = pxa_gpio_get; |
| 257 | c->set = pxa_gpio_set; |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 258 | c->to_irq = pxa_gpio_to_irq; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 259 | |
| 260 | /* number of GPIOs on last bank may be less than 32 */ |
| 261 | c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; |
| 262 | gpiochip_add(c); |
| 263 | } |
| 264 | pxa_gpio_chips = chips; |
| 265 | return 0; |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 266 | } |
| 267 | |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 268 | /* Update only those GRERx and GFERx edge detection register bits if those |
| 269 | * bits are set in c->irq_mask |
| 270 | */ |
| 271 | static inline void update_edge_detect(struct pxa_gpio_chip *c) |
| 272 | { |
| 273 | uint32_t grer, gfer; |
| 274 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 275 | grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; |
| 276 | gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 277 | grer |= c->irq_edge_rise & c->irq_mask; |
| 278 | gfer |= c->irq_edge_fall & c->irq_mask; |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 279 | writel_relaxed(grer, c->regbase + GRER_OFFSET); |
| 280 | writel_relaxed(gfer, c->regbase + GFER_OFFSET); |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 281 | } |
| 282 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 283 | static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 284 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 285 | struct pxa_gpio_chip *c; |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 286 | int gpio = pxa_irq_to_gpio(d->irq); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 287 | unsigned long gpdr, mask = GPIO_bit(gpio); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 288 | |
Linus Walleij | a065685 | 2011-06-13 10:42:19 +0200 | [diff] [blame] | 289 | c = gpio_to_pxachip(gpio); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 290 | |
| 291 | if (type == IRQ_TYPE_PROBE) { |
| 292 | /* Don't mess with enabled GPIOs using preconfigured edges or |
| 293 | * GPIOs set to alternate function or to output during probe |
| 294 | */ |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 295 | if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 296 | return 0; |
eric miao | 689c04a | 2008-03-04 17:18:38 +0800 | [diff] [blame] | 297 | |
| 298 | if (__gpio_is_occupied(gpio)) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 299 | return 0; |
eric miao | 689c04a | 2008-03-04 17:18:38 +0800 | [diff] [blame] | 300 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 301 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 302 | } |
| 303 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 304 | gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 305 | |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 306 | if (__gpio_is_inverted(gpio)) |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 307 | writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 308 | else |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 309 | writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 310 | |
| 311 | if (type & IRQ_TYPE_EDGE_RISING) |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 312 | c->irq_edge_rise |= mask; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 313 | else |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 314 | c->irq_edge_rise &= ~mask; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 315 | |
| 316 | if (type & IRQ_TYPE_EDGE_FALLING) |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 317 | c->irq_edge_fall |= mask; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 318 | else |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 319 | c->irq_edge_fall &= ~mask; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 320 | |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 321 | update_edge_detect(c); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 322 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 323 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 324 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), |
| 325 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); |
| 326 | return 0; |
| 327 | } |
| 328 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 329 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) |
| 330 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 331 | struct pxa_gpio_chip *c; |
| 332 | int loop, gpio, gpio_base, n; |
| 333 | unsigned long gedr; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 334 | |
| 335 | do { |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 336 | loop = 0; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 337 | for_each_gpio_chip(gpio, c) { |
| 338 | gpio_base = c->chip.base; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 339 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 340 | gedr = readl_relaxed(c->regbase + GEDR_OFFSET); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 341 | gedr = gedr & c->irq_mask; |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 342 | writel_relaxed(gedr, c->regbase + GEDR_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 343 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 344 | n = find_first_bit(&gedr, BITS_PER_LONG); |
| 345 | while (n < BITS_PER_LONG) { |
| 346 | loop = 1; |
| 347 | |
| 348 | generic_handle_irq(gpio_to_irq(gpio_base + n)); |
| 349 | n = find_next_bit(&gedr, BITS_PER_LONG, n + 1); |
| 350 | } |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 351 | } |
| 352 | } while (loop); |
| 353 | } |
| 354 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 355 | static void pxa_ack_muxed_gpio(struct irq_data *d) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 356 | { |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 357 | int gpio = pxa_irq_to_gpio(d->irq); |
Linus Walleij | a065685 | 2011-06-13 10:42:19 +0200 | [diff] [blame] | 358 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 359 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 360 | writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 361 | } |
| 362 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 363 | static void pxa_mask_muxed_gpio(struct irq_data *d) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 364 | { |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 365 | int gpio = pxa_irq_to_gpio(d->irq); |
Linus Walleij | a065685 | 2011-06-13 10:42:19 +0200 | [diff] [blame] | 366 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 367 | uint32_t grer, gfer; |
| 368 | |
| 369 | c->irq_mask &= ~GPIO_bit(gpio); |
| 370 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 371 | grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); |
| 372 | gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio); |
| 373 | writel_relaxed(grer, c->regbase + GRER_OFFSET); |
| 374 | writel_relaxed(gfer, c->regbase + GFER_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 375 | } |
| 376 | |
Robert Jarzmik | b95ace5 | 2012-04-22 13:37:24 +0200 | [diff] [blame] | 377 | static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) |
| 378 | { |
| 379 | int gpio = pxa_irq_to_gpio(d->irq); |
| 380 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
| 381 | |
| 382 | if (c->set_wake) |
| 383 | return c->set_wake(gpio, on); |
| 384 | else |
| 385 | return 0; |
| 386 | } |
| 387 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 388 | static void pxa_unmask_muxed_gpio(struct irq_data *d) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 389 | { |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 390 | int gpio = pxa_irq_to_gpio(d->irq); |
Linus Walleij | a065685 | 2011-06-13 10:42:19 +0200 | [diff] [blame] | 391 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 392 | |
| 393 | c->irq_mask |= GPIO_bit(gpio); |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 394 | update_edge_detect(c); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 395 | } |
| 396 | |
| 397 | static struct irq_chip pxa_muxed_gpio_chip = { |
| 398 | .name = "GPIO", |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 399 | .irq_ack = pxa_ack_muxed_gpio, |
| 400 | .irq_mask = pxa_mask_muxed_gpio, |
| 401 | .irq_unmask = pxa_unmask_muxed_gpio, |
| 402 | .irq_set_type = pxa_gpio_irq_type, |
Robert Jarzmik | b95ace5 | 2012-04-22 13:37:24 +0200 | [diff] [blame] | 403 | .irq_set_wake = pxa_gpio_set_wake, |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 404 | }; |
| 405 | |
Haojian Zhuang | 478e223 | 2011-10-14 16:44:07 +0800 | [diff] [blame] | 406 | static int pxa_gpio_nums(void) |
| 407 | { |
| 408 | int count = 0; |
| 409 | |
| 410 | #ifdef CONFIG_ARCH_PXA |
| 411 | if (cpu_is_pxa25x()) { |
| 412 | #ifdef CONFIG_CPU_PXA26x |
| 413 | count = 89; |
| 414 | gpio_type = PXA26X_GPIO; |
| 415 | #elif defined(CONFIG_PXA25x) |
| 416 | count = 84; |
| 417 | gpio_type = PXA26X_GPIO; |
| 418 | #endif /* CONFIG_CPU_PXA26x */ |
| 419 | } else if (cpu_is_pxa27x()) { |
| 420 | count = 120; |
| 421 | gpio_type = PXA27X_GPIO; |
| 422 | } else if (cpu_is_pxa93x() || cpu_is_pxa95x()) { |
| 423 | count = 191; |
| 424 | gpio_type = PXA93X_GPIO; |
| 425 | } else if (cpu_is_pxa3xx()) { |
| 426 | count = 127; |
| 427 | gpio_type = PXA3XX_GPIO; |
| 428 | } |
| 429 | #endif /* CONFIG_ARCH_PXA */ |
| 430 | |
| 431 | #ifdef CONFIG_ARCH_MMP |
| 432 | if (cpu_is_pxa168() || cpu_is_pxa910()) { |
| 433 | count = 127; |
| 434 | gpio_type = MMP_GPIO; |
| 435 | } else if (cpu_is_mmp2()) { |
| 436 | count = 191; |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 437 | gpio_type = MMP_GPIO; |
Haojian Zhuang | 478e223 | 2011-10-14 16:44:07 +0800 | [diff] [blame] | 438 | } |
| 439 | #endif /* CONFIG_ARCH_MMP */ |
| 440 | return count; |
| 441 | } |
| 442 | |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 443 | static struct of_device_id pxa_gpio_dt_ids[] = { |
| 444 | { .compatible = "mrvl,pxa-gpio" }, |
| 445 | { .compatible = "mrvl,mmp-gpio", .data = (void *)MMP_GPIO }, |
| 446 | {} |
| 447 | }; |
| 448 | |
| 449 | static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, |
| 450 | irq_hw_number_t hw) |
| 451 | { |
| 452 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, |
| 453 | handle_edge_irq); |
| 454 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
| 455 | return 0; |
| 456 | } |
| 457 | |
| 458 | const struct irq_domain_ops pxa_irq_domain_ops = { |
| 459 | .map = pxa_irq_domain_map, |
| 460 | }; |
| 461 | |
| 462 | #ifdef CONFIG_OF |
| 463 | static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev) |
| 464 | { |
Daniel Mack | 9450be7 | 2012-07-22 16:55:44 +0200 | [diff] [blame^] | 465 | int ret, nr_banks, nr_gpios; |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 466 | struct device_node *prev, *next, *np = pdev->dev.of_node; |
| 467 | const struct of_device_id *of_id = |
| 468 | of_match_device(pxa_gpio_dt_ids, &pdev->dev); |
| 469 | |
| 470 | if (!of_id) { |
| 471 | dev_err(&pdev->dev, "Failed to find gpio controller\n"); |
| 472 | return -EFAULT; |
| 473 | } |
| 474 | gpio_type = (int)of_id->data; |
| 475 | |
| 476 | next = of_get_next_child(np, NULL); |
| 477 | prev = next; |
| 478 | if (!next) { |
| 479 | dev_err(&pdev->dev, "Failed to find child gpio node\n"); |
| 480 | ret = -EINVAL; |
| 481 | goto err; |
| 482 | } |
| 483 | for (nr_banks = 1; ; nr_banks++) { |
| 484 | next = of_get_next_child(np, prev); |
| 485 | if (!next) |
| 486 | break; |
| 487 | prev = next; |
| 488 | } |
| 489 | of_node_put(prev); |
| 490 | nr_gpios = nr_banks << 5; |
| 491 | pxa_last_gpio = nr_gpios - 1; |
| 492 | |
| 493 | irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0); |
| 494 | if (irq_base < 0) { |
| 495 | dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); |
| 496 | goto err; |
| 497 | } |
| 498 | domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0, |
| 499 | &pxa_irq_domain_ops, NULL); |
| 500 | return 0; |
| 501 | err: |
| 502 | iounmap(gpio_reg_base); |
| 503 | return ret; |
| 504 | } |
| 505 | #else |
| 506 | #define pxa_gpio_probe_dt(pdev) (-1) |
| 507 | #endif |
| 508 | |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 509 | static int __devinit pxa_gpio_probe(struct platform_device *pdev) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 510 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 511 | struct pxa_gpio_chip *c; |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 512 | struct resource *res; |
Haojian Zhuang | 389eda1 | 2011-10-17 21:26:55 +0800 | [diff] [blame] | 513 | struct clk *clk; |
Robert Jarzmik | b95ace5 | 2012-04-22 13:37:24 +0200 | [diff] [blame] | 514 | struct pxa_gpio_platform_data *info; |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 515 | int gpio, irq, ret, use_of = 0; |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 516 | int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 517 | |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 518 | ret = pxa_gpio_probe_dt(pdev); |
Daniel Mack | 9450be7 | 2012-07-22 16:55:44 +0200 | [diff] [blame^] | 519 | if (ret < 0) { |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 520 | pxa_last_gpio = pxa_gpio_nums(); |
Daniel Mack | 9450be7 | 2012-07-22 16:55:44 +0200 | [diff] [blame^] | 521 | #ifdef CONFIG_ARCH_PXA |
| 522 | if (gpio_is_pxa_type(gpio_type)) |
| 523 | irq_base = PXA_GPIO_TO_IRQ(0); |
| 524 | #endif |
| 525 | #ifdef CONFIG_ARCH_MMP |
| 526 | if (gpio_is_mmp_type(gpio_type)) |
| 527 | irq_base = MMP_GPIO_TO_IRQ(0); |
| 528 | #endif |
| 529 | } else { |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 530 | use_of = 1; |
Daniel Mack | 9450be7 | 2012-07-22 16:55:44 +0200 | [diff] [blame^] | 531 | } |
| 532 | |
Haojian Zhuang | 478e223 | 2011-10-14 16:44:07 +0800 | [diff] [blame] | 533 | if (!pxa_last_gpio) |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 534 | return -EINVAL; |
| 535 | |
| 536 | irq0 = platform_get_irq_byname(pdev, "gpio0"); |
| 537 | irq1 = platform_get_irq_byname(pdev, "gpio1"); |
| 538 | irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); |
| 539 | if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) |
| 540 | || (irq_mux <= 0)) |
| 541 | return -EINVAL; |
| 542 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 543 | if (!res) |
| 544 | return -EINVAL; |
| 545 | gpio_reg_base = ioremap(res->start, resource_size(res)); |
| 546 | if (!gpio_reg_base) |
| 547 | return -EINVAL; |
| 548 | |
| 549 | if (irq0 > 0) |
| 550 | gpio_offset = 2; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 551 | |
Haojian Zhuang | 389eda1 | 2011-10-17 21:26:55 +0800 | [diff] [blame] | 552 | clk = clk_get(&pdev->dev, NULL); |
| 553 | if (IS_ERR(clk)) { |
| 554 | dev_err(&pdev->dev, "Error %ld to get gpio clock\n", |
| 555 | PTR_ERR(clk)); |
| 556 | iounmap(gpio_reg_base); |
| 557 | return PTR_ERR(clk); |
| 558 | } |
| 559 | ret = clk_prepare(clk); |
| 560 | if (ret) { |
| 561 | clk_put(clk); |
| 562 | iounmap(gpio_reg_base); |
| 563 | return ret; |
| 564 | } |
| 565 | ret = clk_enable(clk); |
| 566 | if (ret) { |
| 567 | clk_unprepare(clk); |
| 568 | clk_put(clk); |
| 569 | iounmap(gpio_reg_base); |
| 570 | return ret; |
| 571 | } |
| 572 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 573 | /* Initialize GPIO chips */ |
Robert Jarzmik | b95ace5 | 2012-04-22 13:37:24 +0200 | [diff] [blame] | 574 | info = dev_get_platdata(&pdev->dev); |
| 575 | pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 576 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 577 | /* clear all GPIO edge detects */ |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 578 | for_each_gpio_chip(gpio, c) { |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 579 | writel_relaxed(0, c->regbase + GFER_OFFSET); |
| 580 | writel_relaxed(0, c->regbase + GRER_OFFSET); |
| 581 | writel_relaxed(~0,c->regbase + GEDR_OFFSET); |
Haojian Zhuang | be24168 | 2011-10-17 21:07:15 +0800 | [diff] [blame] | 582 | /* unmask GPIO edge detect for AP side */ |
| 583 | if (gpio_is_mmp_type(gpio_type)) |
| 584 | writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 585 | } |
| 586 | |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 587 | if (!use_of) { |
Haojian Zhuang | 87c49e2 | 2011-10-10 14:38:46 +0800 | [diff] [blame] | 588 | #ifdef CONFIG_ARCH_PXA |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 589 | irq = gpio_to_irq(0); |
Thomas Gleixner | f38c02f | 2011-03-24 13:35:09 +0100 | [diff] [blame] | 590 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, |
| 591 | handle_edge_irq); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 592 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 593 | irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler); |
| 594 | |
| 595 | irq = gpio_to_irq(1); |
| 596 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, |
| 597 | handle_edge_irq); |
| 598 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
| 599 | irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler); |
| 600 | #endif |
| 601 | |
| 602 | for (irq = gpio_to_irq(gpio_offset); |
| 603 | irq <= gpio_to_irq(pxa_last_gpio); irq++) { |
| 604 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, |
| 605 | handle_edge_irq); |
| 606 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
| 607 | } |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 608 | } |
| 609 | |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 610 | irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler); |
| 611 | return 0; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 612 | } |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 613 | |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 614 | static struct platform_driver pxa_gpio_driver = { |
| 615 | .probe = pxa_gpio_probe, |
| 616 | .driver = { |
| 617 | .name = "pxa-gpio", |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 618 | .of_match_table = pxa_gpio_dt_ids, |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 619 | }, |
| 620 | }; |
| 621 | |
| 622 | static int __init pxa_gpio_init(void) |
| 623 | { |
| 624 | return platform_driver_register(&pxa_gpio_driver); |
| 625 | } |
| 626 | postcore_initcall(pxa_gpio_init); |
| 627 | |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 628 | #ifdef CONFIG_PM |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 629 | static int pxa_gpio_suspend(void) |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 630 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 631 | struct pxa_gpio_chip *c; |
| 632 | int gpio; |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 633 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 634 | for_each_gpio_chip(gpio, c) { |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 635 | c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); |
| 636 | c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); |
| 637 | c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); |
| 638 | c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 639 | |
| 640 | /* Clear GPIO transition detect bits */ |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 641 | writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 642 | } |
| 643 | return 0; |
| 644 | } |
| 645 | |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 646 | static void pxa_gpio_resume(void) |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 647 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 648 | struct pxa_gpio_chip *c; |
| 649 | int gpio; |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 650 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 651 | for_each_gpio_chip(gpio, c) { |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 652 | /* restore level with set/clear */ |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 653 | writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET); |
| 654 | writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 655 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 656 | writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); |
| 657 | writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); |
| 658 | writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 659 | } |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 660 | } |
| 661 | #else |
| 662 | #define pxa_gpio_suspend NULL |
| 663 | #define pxa_gpio_resume NULL |
| 664 | #endif |
| 665 | |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 666 | struct syscore_ops pxa_gpio_syscore_ops = { |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 667 | .suspend = pxa_gpio_suspend, |
| 668 | .resume = pxa_gpio_resume, |
| 669 | }; |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 670 | |
| 671 | static int __init pxa_gpio_sysinit(void) |
| 672 | { |
| 673 | register_syscore_ops(&pxa_gpio_syscore_ops); |
| 674 | return 0; |
| 675 | } |
| 676 | postcore_initcall(pxa_gpio_sysinit); |