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Philipp Zabel1c44f5f2008-02-04 22:28:22 -08001/*
Eric Miao38f539a2009-01-20 12:09:06 +08002 * linux/arch/arm/plat-pxa/gpio.c
Philipp Zabel1c44f5f2008-02-04 22:28:22 -08003 *
4 * Generic PXA GPIO handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
Haojian Zhuang7a4d5072012-04-13 15:15:45 +080014#include <linux/module.h>
Haojian Zhuang389eda12011-10-17 21:26:55 +080015#include <linux/clk.h>
16#include <linux/err.h>
Russell King2f8163b2011-07-26 10:53:52 +010017#include <linux/gpio.h>
Haojian Zhuang157d2642011-10-17 20:37:52 +080018#include <linux/gpio-pxa.h>
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080019#include <linux/init.h>
eric miaoe3630db2008-03-04 11:42:26 +080020#include <linux/irq.h>
Haojian Zhuang7a4d5072012-04-13 15:15:45 +080021#include <linux/irqdomain.h>
Russell Kingfced80c2008-09-06 12:10:45 +010022#include <linux/io.h>
Haojian Zhuang7a4d5072012-04-13 15:15:45 +080023#include <linux/of.h>
24#include <linux/of_device.h>
Haojian Zhuang157d2642011-10-17 20:37:52 +080025#include <linux/platform_device.h>
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020026#include <linux/syscore_ops.h>
Daniel Mack4aa78262009-06-19 22:56:09 +020027#include <linux/slab.h>
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080028
Rob Herringfeefe732012-01-03 15:52:42 -060029#include <mach/irqs.h>
30
Haojian Zhuang157d2642011-10-17 20:37:52 +080031/*
32 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
33 * one set of registers. The register offsets are organized below:
34 *
35 * GPLR GPDR GPSR GPCR GRER GFER GEDR
36 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
37 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
38 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
39 *
40 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
41 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
42 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
43 *
44 * NOTE:
45 * BANK 3 is only available on PXA27x and later processors.
46 * BANK 4 and 5 are only available on PXA935
47 */
48
49#define GPLR_OFFSET 0x00
50#define GPDR_OFFSET 0x0C
51#define GPSR_OFFSET 0x18
52#define GPCR_OFFSET 0x24
53#define GRER_OFFSET 0x30
54#define GFER_OFFSET 0x3C
55#define GEDR_OFFSET 0x48
56#define GAFR_OFFSET 0x54
Haojian Zhuangbe241682011-10-17 21:07:15 +080057#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
Haojian Zhuang157d2642011-10-17 20:37:52 +080058
59#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080060
Eric Miao3b8e2852009-01-07 11:30:49 +080061int pxa_last_gpio;
Daniel Mack9450be72012-07-22 16:55:44 +020062static int irq_base;
Eric Miao3b8e2852009-01-07 11:30:49 +080063
Haojian Zhuang7a4d5072012-04-13 15:15:45 +080064#ifdef CONFIG_OF
65static struct irq_domain *domain;
66#endif
67
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080068struct pxa_gpio_chip {
69 struct gpio_chip chip;
Eric Miao0807da52009-01-07 18:01:51 +080070 void __iomem *regbase;
71 char label[10];
72
73 unsigned long irq_mask;
74 unsigned long irq_edge_rise;
75 unsigned long irq_edge_fall;
Robert Jarzmikb95ace52012-04-22 13:37:24 +020076 int (*set_wake)(unsigned int gpio, unsigned int on);
Eric Miao0807da52009-01-07 18:01:51 +080077
78#ifdef CONFIG_PM
79 unsigned long saved_gplr;
80 unsigned long saved_gpdr;
81 unsigned long saved_grer;
82 unsigned long saved_gfer;
83#endif
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080084};
85
Haojian Zhuang4929f5a2011-10-10 16:03:51 +080086enum {
87 PXA25X_GPIO = 0,
88 PXA26X_GPIO,
89 PXA27X_GPIO,
90 PXA3XX_GPIO,
91 PXA93X_GPIO,
92 MMP_GPIO = 0x10,
Haojian Zhuang4929f5a2011-10-10 16:03:51 +080093};
94
Eric Miao0807da52009-01-07 18:01:51 +080095static DEFINE_SPINLOCK(gpio_lock);
96static struct pxa_gpio_chip *pxa_gpio_chips;
Haojian Zhuang4929f5a2011-10-10 16:03:51 +080097static int gpio_type;
Haojian Zhuang157d2642011-10-17 20:37:52 +080098static void __iomem *gpio_reg_base;
Eric Miao0807da52009-01-07 18:01:51 +080099
100#define for_each_gpio_chip(i, c) \
101 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
102
103static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
104{
105 return container_of(c, struct pxa_gpio_chip, chip)->regbase;
106}
107
Linus Walleija0656852011-06-13 10:42:19 +0200108static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
Eric Miao0807da52009-01-07 18:01:51 +0800109{
110 return &pxa_gpio_chips[gpio_to_bank(gpio)];
111}
112
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800113static inline int gpio_is_pxa_type(int type)
114{
115 return (type & MMP_GPIO) == 0;
116}
117
118static inline int gpio_is_mmp_type(int type)
119{
120 return (type & MMP_GPIO) != 0;
121}
122
Haojian Zhuang157d2642011-10-17 20:37:52 +0800123/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
124 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
125 */
126static inline int __gpio_is_inverted(int gpio)
127{
128 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
129 return 1;
130 return 0;
131}
132
133/*
134 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
135 * function of a GPIO, and GPDRx cannot be altered once configured. It
136 * is attributed as "occupied" here (I know this terminology isn't
137 * accurate, you are welcome to propose a better one :-)
138 */
139static inline int __gpio_is_occupied(unsigned gpio)
140{
141 struct pxa_gpio_chip *pxachip;
142 void __iomem *base;
143 unsigned long gafr = 0, gpdr = 0;
144 int ret, af = 0, dir = 0;
145
146 pxachip = gpio_to_pxachip(gpio);
147 base = gpio_chip_base(&pxachip->chip);
148 gpdr = readl_relaxed(base + GPDR_OFFSET);
149
150 switch (gpio_type) {
151 case PXA25X_GPIO:
152 case PXA26X_GPIO:
153 case PXA27X_GPIO:
154 gafr = readl_relaxed(base + GAFR_OFFSET);
155 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
156 dir = gpdr & GPIO_bit(gpio);
157
158 if (__gpio_is_inverted(gpio))
159 ret = (af != 1) || (dir == 0);
160 else
161 ret = (af != 0) || (dir != 0);
162 break;
163 default:
164 ret = gpdr & GPIO_bit(gpio);
165 break;
166 }
167 return ret;
168}
169
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800170static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
171{
Daniel Mack9450be72012-07-22 16:55:44 +0200172 return chip->base + offset + irq_base;
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800173}
174
175int pxa_irq_to_gpio(int irq)
176{
Daniel Mack9450be72012-07-22 16:55:44 +0200177 return irq - irq_base;
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800178}
179
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800180static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
181{
Eric Miao0807da52009-01-07 18:01:51 +0800182 void __iomem *base = gpio_chip_base(chip);
183 uint32_t value, mask = 1 << offset;
184 unsigned long flags;
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800185
Eric Miao0807da52009-01-07 18:01:51 +0800186 spin_lock_irqsave(&gpio_lock, flags);
187
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800188 value = readl_relaxed(base + GPDR_OFFSET);
Eric Miao067455a2008-11-26 18:12:04 +0800189 if (__gpio_is_inverted(chip->base + offset))
190 value |= mask;
191 else
192 value &= ~mask;
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800193 writel_relaxed(value, base + GPDR_OFFSET);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800194
Eric Miao0807da52009-01-07 18:01:51 +0800195 spin_unlock_irqrestore(&gpio_lock, flags);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800196 return 0;
197}
198
199static int pxa_gpio_direction_output(struct gpio_chip *chip,
Eric Miao0807da52009-01-07 18:01:51 +0800200 unsigned offset, int value)
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800201{
Eric Miao0807da52009-01-07 18:01:51 +0800202 void __iomem *base = gpio_chip_base(chip);
203 uint32_t tmp, mask = 1 << offset;
204 unsigned long flags;
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800205
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800206 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
Eric Miao0807da52009-01-07 18:01:51 +0800207
208 spin_lock_irqsave(&gpio_lock, flags);
209
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800210 tmp = readl_relaxed(base + GPDR_OFFSET);
Eric Miao067455a2008-11-26 18:12:04 +0800211 if (__gpio_is_inverted(chip->base + offset))
212 tmp &= ~mask;
213 else
214 tmp |= mask;
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800215 writel_relaxed(tmp, base + GPDR_OFFSET);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800216
Eric Miao0807da52009-01-07 18:01:51 +0800217 spin_unlock_irqrestore(&gpio_lock, flags);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800218 return 0;
219}
220
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800221static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
222{
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800223 return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800224}
225
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800226static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
227{
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800228 writel_relaxed(1 << offset, gpio_chip_base(chip) +
Eric Miao0807da52009-01-07 18:01:51 +0800229 (value ? GPSR_OFFSET : GPCR_OFFSET));
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800230}
231
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200232static int __devinit pxa_init_gpio_chip(int gpio_end,
233 int (*set_wake)(unsigned int, unsigned int))
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800234{
Eric Miao0807da52009-01-07 18:01:51 +0800235 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
236 struct pxa_gpio_chip *chips;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800237
Daniel Mack4aa78262009-06-19 22:56:09 +0200238 chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
Eric Miao0807da52009-01-07 18:01:51 +0800239 if (chips == NULL) {
240 pr_err("%s: failed to allocate GPIO chips\n", __func__);
241 return -ENOMEM;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800242 }
Eric Miao0807da52009-01-07 18:01:51 +0800243
244 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
245 struct gpio_chip *c = &chips[i].chip;
246
247 sprintf(chips[i].label, "gpio-%d", i);
Haojian Zhuang157d2642011-10-17 20:37:52 +0800248 chips[i].regbase = gpio_reg_base + BANK_OFF(i);
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200249 chips[i].set_wake = set_wake;
Eric Miao0807da52009-01-07 18:01:51 +0800250
251 c->base = gpio;
252 c->label = chips[i].label;
253
254 c->direction_input = pxa_gpio_direction_input;
255 c->direction_output = pxa_gpio_direction_output;
256 c->get = pxa_gpio_get;
257 c->set = pxa_gpio_set;
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800258 c->to_irq = pxa_gpio_to_irq;
Eric Miao0807da52009-01-07 18:01:51 +0800259
260 /* number of GPIOs on last bank may be less than 32 */
261 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
262 gpiochip_add(c);
263 }
264 pxa_gpio_chips = chips;
265 return 0;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800266}
267
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800268/* Update only those GRERx and GFERx edge detection register bits if those
269 * bits are set in c->irq_mask
270 */
271static inline void update_edge_detect(struct pxa_gpio_chip *c)
272{
273 uint32_t grer, gfer;
274
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800275 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
276 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800277 grer |= c->irq_edge_rise & c->irq_mask;
278 gfer |= c->irq_edge_fall & c->irq_mask;
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800279 writel_relaxed(grer, c->regbase + GRER_OFFSET);
280 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800281}
282
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100283static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
eric miaoe3630db2008-03-04 11:42:26 +0800284{
Eric Miao0807da52009-01-07 18:01:51 +0800285 struct pxa_gpio_chip *c;
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800286 int gpio = pxa_irq_to_gpio(d->irq);
Eric Miao0807da52009-01-07 18:01:51 +0800287 unsigned long gpdr, mask = GPIO_bit(gpio);
eric miaoe3630db2008-03-04 11:42:26 +0800288
Linus Walleija0656852011-06-13 10:42:19 +0200289 c = gpio_to_pxachip(gpio);
eric miaoe3630db2008-03-04 11:42:26 +0800290
291 if (type == IRQ_TYPE_PROBE) {
292 /* Don't mess with enabled GPIOs using preconfigured edges or
293 * GPIOs set to alternate function or to output during probe
294 */
Eric Miao0807da52009-01-07 18:01:51 +0800295 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
eric miaoe3630db2008-03-04 11:42:26 +0800296 return 0;
eric miao689c04a2008-03-04 17:18:38 +0800297
298 if (__gpio_is_occupied(gpio))
eric miaoe3630db2008-03-04 11:42:26 +0800299 return 0;
eric miao689c04a2008-03-04 17:18:38 +0800300
eric miaoe3630db2008-03-04 11:42:26 +0800301 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
302 }
303
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800304 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
Eric Miao0807da52009-01-07 18:01:51 +0800305
Eric Miao067455a2008-11-26 18:12:04 +0800306 if (__gpio_is_inverted(gpio))
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800307 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
Eric Miao067455a2008-11-26 18:12:04 +0800308 else
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800309 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800310
311 if (type & IRQ_TYPE_EDGE_RISING)
Eric Miao0807da52009-01-07 18:01:51 +0800312 c->irq_edge_rise |= mask;
eric miaoe3630db2008-03-04 11:42:26 +0800313 else
Eric Miao0807da52009-01-07 18:01:51 +0800314 c->irq_edge_rise &= ~mask;
eric miaoe3630db2008-03-04 11:42:26 +0800315
316 if (type & IRQ_TYPE_EDGE_FALLING)
Eric Miao0807da52009-01-07 18:01:51 +0800317 c->irq_edge_fall |= mask;
eric miaoe3630db2008-03-04 11:42:26 +0800318 else
Eric Miao0807da52009-01-07 18:01:51 +0800319 c->irq_edge_fall &= ~mask;
eric miaoe3630db2008-03-04 11:42:26 +0800320
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800321 update_edge_detect(c);
eric miaoe3630db2008-03-04 11:42:26 +0800322
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100323 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
eric miaoe3630db2008-03-04 11:42:26 +0800324 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
325 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
326 return 0;
327}
328
eric miaoe3630db2008-03-04 11:42:26 +0800329static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
330{
Eric Miao0807da52009-01-07 18:01:51 +0800331 struct pxa_gpio_chip *c;
332 int loop, gpio, gpio_base, n;
333 unsigned long gedr;
eric miaoe3630db2008-03-04 11:42:26 +0800334
335 do {
eric miaoe3630db2008-03-04 11:42:26 +0800336 loop = 0;
Eric Miao0807da52009-01-07 18:01:51 +0800337 for_each_gpio_chip(gpio, c) {
338 gpio_base = c->chip.base;
eric miaoe3630db2008-03-04 11:42:26 +0800339
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800340 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
Eric Miao0807da52009-01-07 18:01:51 +0800341 gedr = gedr & c->irq_mask;
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800342 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800343
Eric Miao0807da52009-01-07 18:01:51 +0800344 n = find_first_bit(&gedr, BITS_PER_LONG);
345 while (n < BITS_PER_LONG) {
346 loop = 1;
347
348 generic_handle_irq(gpio_to_irq(gpio_base + n));
349 n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
350 }
eric miaoe3630db2008-03-04 11:42:26 +0800351 }
352 } while (loop);
353}
354
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100355static void pxa_ack_muxed_gpio(struct irq_data *d)
eric miaoe3630db2008-03-04 11:42:26 +0800356{
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800357 int gpio = pxa_irq_to_gpio(d->irq);
Linus Walleija0656852011-06-13 10:42:19 +0200358 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800359
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800360 writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800361}
362
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100363static void pxa_mask_muxed_gpio(struct irq_data *d)
eric miaoe3630db2008-03-04 11:42:26 +0800364{
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800365 int gpio = pxa_irq_to_gpio(d->irq);
Linus Walleija0656852011-06-13 10:42:19 +0200366 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800367 uint32_t grer, gfer;
368
369 c->irq_mask &= ~GPIO_bit(gpio);
370
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800371 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
372 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
373 writel_relaxed(grer, c->regbase + GRER_OFFSET);
374 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800375}
376
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200377static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
378{
379 int gpio = pxa_irq_to_gpio(d->irq);
380 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
381
382 if (c->set_wake)
383 return c->set_wake(gpio, on);
384 else
385 return 0;
386}
387
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100388static void pxa_unmask_muxed_gpio(struct irq_data *d)
eric miaoe3630db2008-03-04 11:42:26 +0800389{
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800390 int gpio = pxa_irq_to_gpio(d->irq);
Linus Walleija0656852011-06-13 10:42:19 +0200391 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800392
393 c->irq_mask |= GPIO_bit(gpio);
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800394 update_edge_detect(c);
eric miaoe3630db2008-03-04 11:42:26 +0800395}
396
397static struct irq_chip pxa_muxed_gpio_chip = {
398 .name = "GPIO",
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100399 .irq_ack = pxa_ack_muxed_gpio,
400 .irq_mask = pxa_mask_muxed_gpio,
401 .irq_unmask = pxa_unmask_muxed_gpio,
402 .irq_set_type = pxa_gpio_irq_type,
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200403 .irq_set_wake = pxa_gpio_set_wake,
eric miaoe3630db2008-03-04 11:42:26 +0800404};
405
Haojian Zhuang478e2232011-10-14 16:44:07 +0800406static int pxa_gpio_nums(void)
407{
408 int count = 0;
409
410#ifdef CONFIG_ARCH_PXA
411 if (cpu_is_pxa25x()) {
412#ifdef CONFIG_CPU_PXA26x
413 count = 89;
414 gpio_type = PXA26X_GPIO;
415#elif defined(CONFIG_PXA25x)
416 count = 84;
417 gpio_type = PXA26X_GPIO;
418#endif /* CONFIG_CPU_PXA26x */
419 } else if (cpu_is_pxa27x()) {
420 count = 120;
421 gpio_type = PXA27X_GPIO;
422 } else if (cpu_is_pxa93x() || cpu_is_pxa95x()) {
423 count = 191;
424 gpio_type = PXA93X_GPIO;
425 } else if (cpu_is_pxa3xx()) {
426 count = 127;
427 gpio_type = PXA3XX_GPIO;
428 }
429#endif /* CONFIG_ARCH_PXA */
430
431#ifdef CONFIG_ARCH_MMP
432 if (cpu_is_pxa168() || cpu_is_pxa910()) {
433 count = 127;
434 gpio_type = MMP_GPIO;
435 } else if (cpu_is_mmp2()) {
436 count = 191;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800437 gpio_type = MMP_GPIO;
Haojian Zhuang478e2232011-10-14 16:44:07 +0800438 }
439#endif /* CONFIG_ARCH_MMP */
440 return count;
441}
442
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800443static struct of_device_id pxa_gpio_dt_ids[] = {
444 { .compatible = "mrvl,pxa-gpio" },
445 { .compatible = "mrvl,mmp-gpio", .data = (void *)MMP_GPIO },
446 {}
447};
448
449static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
450 irq_hw_number_t hw)
451{
452 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
453 handle_edge_irq);
454 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
455 return 0;
456}
457
458const struct irq_domain_ops pxa_irq_domain_ops = {
459 .map = pxa_irq_domain_map,
460};
461
462#ifdef CONFIG_OF
463static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev)
464{
Daniel Mack9450be72012-07-22 16:55:44 +0200465 int ret, nr_banks, nr_gpios;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800466 struct device_node *prev, *next, *np = pdev->dev.of_node;
467 const struct of_device_id *of_id =
468 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
469
470 if (!of_id) {
471 dev_err(&pdev->dev, "Failed to find gpio controller\n");
472 return -EFAULT;
473 }
474 gpio_type = (int)of_id->data;
475
476 next = of_get_next_child(np, NULL);
477 prev = next;
478 if (!next) {
479 dev_err(&pdev->dev, "Failed to find child gpio node\n");
480 ret = -EINVAL;
481 goto err;
482 }
483 for (nr_banks = 1; ; nr_banks++) {
484 next = of_get_next_child(np, prev);
485 if (!next)
486 break;
487 prev = next;
488 }
489 of_node_put(prev);
490 nr_gpios = nr_banks << 5;
491 pxa_last_gpio = nr_gpios - 1;
492
493 irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
494 if (irq_base < 0) {
495 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
496 goto err;
497 }
498 domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0,
499 &pxa_irq_domain_ops, NULL);
500 return 0;
501err:
502 iounmap(gpio_reg_base);
503 return ret;
504}
505#else
506#define pxa_gpio_probe_dt(pdev) (-1)
507#endif
508
Haojian Zhuang157d2642011-10-17 20:37:52 +0800509static int __devinit pxa_gpio_probe(struct platform_device *pdev)
eric miaoe3630db2008-03-04 11:42:26 +0800510{
Eric Miao0807da52009-01-07 18:01:51 +0800511 struct pxa_gpio_chip *c;
Haojian Zhuang157d2642011-10-17 20:37:52 +0800512 struct resource *res;
Haojian Zhuang389eda12011-10-17 21:26:55 +0800513 struct clk *clk;
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200514 struct pxa_gpio_platform_data *info;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800515 int gpio, irq, ret, use_of = 0;
Haojian Zhuang157d2642011-10-17 20:37:52 +0800516 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
eric miaoe3630db2008-03-04 11:42:26 +0800517
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800518 ret = pxa_gpio_probe_dt(pdev);
Daniel Mack9450be72012-07-22 16:55:44 +0200519 if (ret < 0) {
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800520 pxa_last_gpio = pxa_gpio_nums();
Daniel Mack9450be72012-07-22 16:55:44 +0200521#ifdef CONFIG_ARCH_PXA
522 if (gpio_is_pxa_type(gpio_type))
523 irq_base = PXA_GPIO_TO_IRQ(0);
524#endif
525#ifdef CONFIG_ARCH_MMP
526 if (gpio_is_mmp_type(gpio_type))
527 irq_base = MMP_GPIO_TO_IRQ(0);
528#endif
529 } else {
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800530 use_of = 1;
Daniel Mack9450be72012-07-22 16:55:44 +0200531 }
532
Haojian Zhuang478e2232011-10-14 16:44:07 +0800533 if (!pxa_last_gpio)
Haojian Zhuang157d2642011-10-17 20:37:52 +0800534 return -EINVAL;
535
536 irq0 = platform_get_irq_byname(pdev, "gpio0");
537 irq1 = platform_get_irq_byname(pdev, "gpio1");
538 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
539 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
540 || (irq_mux <= 0))
541 return -EINVAL;
542 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
543 if (!res)
544 return -EINVAL;
545 gpio_reg_base = ioremap(res->start, resource_size(res));
546 if (!gpio_reg_base)
547 return -EINVAL;
548
549 if (irq0 > 0)
550 gpio_offset = 2;
eric miaoe3630db2008-03-04 11:42:26 +0800551
Haojian Zhuang389eda12011-10-17 21:26:55 +0800552 clk = clk_get(&pdev->dev, NULL);
553 if (IS_ERR(clk)) {
554 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
555 PTR_ERR(clk));
556 iounmap(gpio_reg_base);
557 return PTR_ERR(clk);
558 }
559 ret = clk_prepare(clk);
560 if (ret) {
561 clk_put(clk);
562 iounmap(gpio_reg_base);
563 return ret;
564 }
565 ret = clk_enable(clk);
566 if (ret) {
567 clk_unprepare(clk);
568 clk_put(clk);
569 iounmap(gpio_reg_base);
570 return ret;
571 }
572
Eric Miao0807da52009-01-07 18:01:51 +0800573 /* Initialize GPIO chips */
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200574 info = dev_get_platdata(&pdev->dev);
575 pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);
Eric Miao0807da52009-01-07 18:01:51 +0800576
eric miaoe3630db2008-03-04 11:42:26 +0800577 /* clear all GPIO edge detects */
Eric Miao0807da52009-01-07 18:01:51 +0800578 for_each_gpio_chip(gpio, c) {
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800579 writel_relaxed(0, c->regbase + GFER_OFFSET);
580 writel_relaxed(0, c->regbase + GRER_OFFSET);
581 writel_relaxed(~0,c->regbase + GEDR_OFFSET);
Haojian Zhuangbe241682011-10-17 21:07:15 +0800582 /* unmask GPIO edge detect for AP side */
583 if (gpio_is_mmp_type(gpio_type))
584 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800585 }
586
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800587 if (!use_of) {
Haojian Zhuang87c49e22011-10-10 14:38:46 +0800588#ifdef CONFIG_ARCH_PXA
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800589 irq = gpio_to_irq(0);
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +0100590 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
591 handle_edge_irq);
eric miaoe3630db2008-03-04 11:42:26 +0800592 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800593 irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
594
595 irq = gpio_to_irq(1);
596 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
597 handle_edge_irq);
598 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
599 irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
600#endif
601
602 for (irq = gpio_to_irq(gpio_offset);
603 irq <= gpio_to_irq(pxa_last_gpio); irq++) {
604 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
605 handle_edge_irq);
606 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
607 }
eric miaoe3630db2008-03-04 11:42:26 +0800608 }
609
Haojian Zhuang157d2642011-10-17 20:37:52 +0800610 irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
611 return 0;
eric miaoe3630db2008-03-04 11:42:26 +0800612}
eric miao663707c2008-03-04 16:13:58 +0800613
Haojian Zhuang157d2642011-10-17 20:37:52 +0800614static struct platform_driver pxa_gpio_driver = {
615 .probe = pxa_gpio_probe,
616 .driver = {
617 .name = "pxa-gpio",
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800618 .of_match_table = pxa_gpio_dt_ids,
Haojian Zhuang157d2642011-10-17 20:37:52 +0800619 },
620};
621
622static int __init pxa_gpio_init(void)
623{
624 return platform_driver_register(&pxa_gpio_driver);
625}
626postcore_initcall(pxa_gpio_init);
627
eric miao663707c2008-03-04 16:13:58 +0800628#ifdef CONFIG_PM
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200629static int pxa_gpio_suspend(void)
eric miao663707c2008-03-04 16:13:58 +0800630{
Eric Miao0807da52009-01-07 18:01:51 +0800631 struct pxa_gpio_chip *c;
632 int gpio;
eric miao663707c2008-03-04 16:13:58 +0800633
Eric Miao0807da52009-01-07 18:01:51 +0800634 for_each_gpio_chip(gpio, c) {
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800635 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
636 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
637 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
638 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800639
640 /* Clear GPIO transition detect bits */
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800641 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800642 }
643 return 0;
644}
645
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200646static void pxa_gpio_resume(void)
eric miao663707c2008-03-04 16:13:58 +0800647{
Eric Miao0807da52009-01-07 18:01:51 +0800648 struct pxa_gpio_chip *c;
649 int gpio;
eric miao663707c2008-03-04 16:13:58 +0800650
Eric Miao0807da52009-01-07 18:01:51 +0800651 for_each_gpio_chip(gpio, c) {
eric miao663707c2008-03-04 16:13:58 +0800652 /* restore level with set/clear */
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800653 writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
654 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800655
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800656 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
657 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
658 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800659 }
eric miao663707c2008-03-04 16:13:58 +0800660}
661#else
662#define pxa_gpio_suspend NULL
663#define pxa_gpio_resume NULL
664#endif
665
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200666struct syscore_ops pxa_gpio_syscore_ops = {
eric miao663707c2008-03-04 16:13:58 +0800667 .suspend = pxa_gpio_suspend,
668 .resume = pxa_gpio_resume,
669};
Haojian Zhuang157d2642011-10-17 20:37:52 +0800670
671static int __init pxa_gpio_sysinit(void)
672{
673 register_syscore_ops(&pxa_gpio_syscore_ops);
674 return 0;
675}
676postcore_initcall(pxa_gpio_sysinit);