blob: b1a8f0f680a73564e39ec4d6c30941c0bfa272b3 [file] [log] [blame]
Daniel Walker62a6cc52010-05-05 07:27:16 -07001/*
2 * Copyright (C) 2008 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18
19#include <linux/dma-mapping.h>
20#include <mach/irqs.h>
21#include <mach/msm_iomap.h>
22#include <mach/dma.h>
23#include <mach/board.h>
24
25#include "devices.h"
26
27#include <asm/mach/flash.h>
28
29#include <mach/mmc.h>
30
31static struct resource resources_uart3[] = {
32 {
33 .start = INT_UART3,
34 .end = INT_UART3,
35 .flags = IORESOURCE_IRQ,
36 },
37 {
38 .start = MSM_UART3_PHYS,
39 .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
40 .flags = IORESOURCE_MEM,
41 },
42};
43
44struct platform_device msm_device_uart3 = {
45 .name = "msm_serial",
46 .id = 2,
47 .num_resources = ARRAY_SIZE(resources_uart3),
48 .resource = resources_uart3,
49};
50
Niranjana Vishwanathapura88b52272010-10-06 13:52:11 -070051struct platform_device msm_device_smd = {
52 .name = "msm_smd",
53 .id = -1,
54};
55
Pavankumar Kondeti7032d512010-12-08 13:37:07 +053056static struct resource resources_otg[] = {
57 {
58 .start = MSM_HSUSB_PHYS,
59 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
60 .flags = IORESOURCE_MEM,
61 },
62 {
63 .start = INT_USB_HS,
64 .end = INT_USB_HS,
65 .flags = IORESOURCE_IRQ,
66 },
67};
68
69struct platform_device msm_device_otg = {
70 .name = "msm_otg",
71 .id = -1,
72 .num_resources = ARRAY_SIZE(resources_otg),
73 .resource = resources_otg,
74 .dev = {
75 .coherent_dma_mask = 0xffffffff,
76 },
77};
78
79static struct resource resources_hsusb[] = {
80 {
81 .start = MSM_HSUSB_PHYS,
82 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
83 .flags = IORESOURCE_MEM,
84 },
85 {
86 .start = INT_USB_HS,
87 .end = INT_USB_HS,
88 .flags = IORESOURCE_IRQ,
89 },
90};
91
92struct platform_device msm_device_hsusb = {
93 .name = "msm_hsusb",
94 .id = -1,
95 .num_resources = ARRAY_SIZE(resources_hsusb),
96 .resource = resources_hsusb,
97 .dev = {
98 .coherent_dma_mask = 0xffffffff,
99 },
100};
101
102static u64 dma_mask = 0xffffffffULL;
103static struct resource resources_hsusb_host[] = {
104 {
105 .start = MSM_HSUSB_PHYS,
106 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
107 .flags = IORESOURCE_MEM,
108 },
109 {
110 .start = INT_USB_HS,
111 .end = INT_USB_HS,
112 .flags = IORESOURCE_IRQ,
113 },
114};
115
116struct platform_device msm_device_hsusb_host = {
117 .name = "msm_hsusb_host",
118 .id = -1,
119 .num_resources = ARRAY_SIZE(resources_hsusb_host),
120 .resource = resources_hsusb_host,
121 .dev = {
122 .dma_mask = &dma_mask,
123 .coherent_dma_mask = 0xffffffffULL,
124 },
125};
126
Sahitya Tummala8b4d95f2011-01-18 11:22:50 +0530127static struct resource resources_sdc1[] = {
128 {
129 .start = MSM_SDC1_PHYS,
130 .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
131 .flags = IORESOURCE_MEM,
132 },
133 {
134 .start = INT_SDC1_0,
135 .end = INT_SDC1_0,
136 .flags = IORESOURCE_IRQ,
137 .name = "cmd_irq",
138 },
139 {
140 .start = INT_SDC1_1,
141 .end = INT_SDC1_1,
142 .flags = IORESOURCE_IRQ,
143 .name = "pio_irq",
144 },
145 {
146 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
147 .name = "status_irq"
148 },
149 {
150 .start = 8,
151 .end = 8,
152 .flags = IORESOURCE_DMA,
153 },
154};
155
156static struct resource resources_sdc2[] = {
157 {
158 .start = MSM_SDC2_PHYS,
159 .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
160 .flags = IORESOURCE_MEM,
161 },
162 {
163 .start = INT_SDC2_0,
164 .end = INT_SDC2_0,
165 .flags = IORESOURCE_IRQ,
166 .name = "cmd_irq",
167 },
168 {
169 .start = INT_SDC2_1,
170 .end = INT_SDC2_1,
171 .flags = IORESOURCE_IRQ,
172 .name = "pio_irq",
173 },
174 {
175 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
176 .name = "status_irq"
177 },
178 {
179 .start = 8,
180 .end = 8,
181 .flags = IORESOURCE_DMA,
182 },
183};
184
185static struct resource resources_sdc3[] = {
186 {
187 .start = MSM_SDC3_PHYS,
188 .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
189 .flags = IORESOURCE_MEM,
190 },
191 {
192 .start = INT_SDC3_0,
193 .end = INT_SDC3_0,
194 .flags = IORESOURCE_IRQ,
195 .name = "cmd_irq",
196 },
197 {
198 .start = INT_SDC3_1,
199 .end = INT_SDC3_1,
200 .flags = IORESOURCE_IRQ,
201 .name = "pio_irq",
202 },
203 {
204 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
205 .name = "status_irq"
206 },
207 {
208 .start = 8,
209 .end = 8,
210 .flags = IORESOURCE_DMA,
211 },
212};
213
214static struct resource resources_sdc4[] = {
215 {
216 .start = MSM_SDC4_PHYS,
217 .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
218 .flags = IORESOURCE_MEM,
219 },
220 {
221 .start = INT_SDC4_0,
222 .end = INT_SDC4_0,
223 .flags = IORESOURCE_IRQ,
224 .name = "cmd_irq",
225 },
226 {
227 .start = INT_SDC4_1,
228 .end = INT_SDC4_1,
229 .flags = IORESOURCE_IRQ,
230 .name = "pio_irq",
231 },
232 {
233 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
234 .name = "status_irq"
235 },
236 {
237 .start = 8,
238 .end = 8,
239 .flags = IORESOURCE_DMA,
240 },
241};
242
243struct platform_device msm_device_sdc1 = {
244 .name = "msm_sdcc",
245 .id = 1,
246 .num_resources = ARRAY_SIZE(resources_sdc1),
247 .resource = resources_sdc1,
248 .dev = {
249 .coherent_dma_mask = 0xffffffff,
250 },
251};
252
253struct platform_device msm_device_sdc2 = {
254 .name = "msm_sdcc",
255 .id = 2,
256 .num_resources = ARRAY_SIZE(resources_sdc2),
257 .resource = resources_sdc2,
258 .dev = {
259 .coherent_dma_mask = 0xffffffff,
260 },
261};
262
263struct platform_device msm_device_sdc3 = {
264 .name = "msm_sdcc",
265 .id = 3,
266 .num_resources = ARRAY_SIZE(resources_sdc3),
267 .resource = resources_sdc3,
268 .dev = {
269 .coherent_dma_mask = 0xffffffff,
270 },
271};
272
273struct platform_device msm_device_sdc4 = {
274 .name = "msm_sdcc",
275 .id = 4,
276 .num_resources = ARRAY_SIZE(resources_sdc4),
277 .resource = resources_sdc4,
278 .dev = {
279 .coherent_dma_mask = 0xffffffff,
280 },
281};
282
283static struct platform_device *msm_sdcc_devices[] __initdata = {
284 &msm_device_sdc1,
285 &msm_device_sdc2,
286 &msm_device_sdc3,
287 &msm_device_sdc4,
288};
289
290int __init msm_add_sdcc(unsigned int controller,
291 struct msm_mmc_platform_data *plat,
292 unsigned int stat_irq, unsigned long stat_irq_flags)
293{
294 struct platform_device *pdev;
295 struct resource *res;
296
297 if (controller < 1 || controller > 4)
298 return -EINVAL;
299
300 pdev = msm_sdcc_devices[controller-1];
301 pdev->dev.platform_data = plat;
302
303 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
304 if (!res)
305 return -EINVAL;
306 else if (stat_irq) {
307 res->start = res->end = stat_irq;
308 res->flags &= ~IORESOURCE_DISABLED;
309 res->flags |= stat_irq_flags;
310 }
311
312 return platform_device_register(pdev);
313}
314
Daniel Walker62a6cc52010-05-05 07:27:16 -0700315struct clk msm_clocks_8x50[] = {
316 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
317 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
318 CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0),
319 CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
320 CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX),
321 CLK_PCOM("gp_clk", GP_CLK, NULL, 0),
322 CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0),
323 CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0),
324 CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0),
325 CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
326 CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0),
327 CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
328 CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
329 CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
330 CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
331 CLK_PCOM("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, 0),
332 CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN),
333 CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
334 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
Sahitya Tummala8b4d95f2011-01-18 11:22:50 +0530335 CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF),
336 CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF),
337 CLK_PCOM("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF),
338 CLK_PCOM("sdc_pclk", SDC2_P_CLK, &msm_device_sdc2.dev, OFF),
339 CLK_PCOM("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF),
340 CLK_PCOM("sdc_pclk", SDC3_P_CLK, &msm_device_sdc3.dev, OFF),
341 CLK_PCOM("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF),
342 CLK_PCOM("sdc_pclk", SDC4_P_CLK, &msm_device_sdc4.dev, OFF),
Daniel Walker62a6cc52010-05-05 07:27:16 -0700343 CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
344 CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0),
345 CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
346 CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
347 CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
348 CLK_PCOM("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF),
349 CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF),
350 CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF),
351 CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0),
352 CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF | CLK_MIN),
353 CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF),
354 CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
355 CLK_PCOM("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
356 CLK_PCOM("usb_hs2_clk", USB_HS2_CLK, NULL, OFF),
357 CLK_PCOM("usb_hs2_pclk", USB_HS2_P_CLK, NULL, OFF),
358 CLK_PCOM("usb_hs3_clk", USB_HS3_CLK, NULL, OFF),
359 CLK_PCOM("usb_hs3_pclk", USB_HS3_P_CLK, NULL, OFF),
360 CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0),
361};
362
363unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
364