blob: 582888db605836f69f3f4b9f44d05dd2c10f4ef1 [file] [log] [blame]
Shawn Guo95ceafd2012-09-06 07:09:11 +00001/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * The OPP code in function cpu0_set_target() is reused from
5 * drivers/cpufreq/omap-cpufreq.c
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <linux/clk.h>
Sudeep KarkadaNageshae1825b22013-09-10 18:59:46 +010015#include <linux/cpu.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000016#include <linux/cpufreq.h>
17#include <linux/err.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/opp.h>
Shawn Guo5553f9e2013-01-30 14:27:49 +000021#include <linux/platform_device.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000022#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24
25static unsigned int transition_latency;
26static unsigned int voltage_tolerance; /* in percentage */
27
28static struct device *cpu_dev;
29static struct clk *cpu_clk;
30static struct regulator *cpu_reg;
31static struct cpufreq_frequency_table *freq_table;
32
Shawn Guo95ceafd2012-09-06 07:09:11 +000033static unsigned int cpu0_get_speed(unsigned int cpu)
34{
35 return clk_get_rate(cpu_clk) / 1000;
36}
37
38static int cpu0_set_target(struct cpufreq_policy *policy,
39 unsigned int target_freq, unsigned int relation)
40{
41 struct cpufreq_freqs freqs;
42 struct opp *opp;
jhbird.choi@samsung.com5df60552013-03-18 08:09:42 +000043 unsigned long volt = 0, volt_old = 0, tol = 0;
Guennadi Liakhovetski0ca68432013-02-25 18:22:37 +010044 long freq_Hz, freq_exact;
Viresh Kumarb43a7ff2013-03-24 11:56:43 +053045 unsigned int index;
Shawn Guo95ceafd2012-09-06 07:09:11 +000046 int ret;
47
48 ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
49 relation, &index);
50 if (ret) {
51 pr_err("failed to match target freqency %d: %d\n",
52 target_freq, ret);
53 return ret;
54 }
55
56 freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
57 if (freq_Hz < 0)
58 freq_Hz = freq_table[index].frequency * 1000;
Guennadi Liakhovetski0ca68432013-02-25 18:22:37 +010059 freq_exact = freq_Hz;
Shawn Guo95ceafd2012-09-06 07:09:11 +000060 freqs.new = freq_Hz / 1000;
61 freqs.old = clk_get_rate(cpu_clk) / 1000;
62
63 if (freqs.old == freqs.new)
64 return 0;
65
Viresh Kumarb43a7ff2013-03-24 11:56:43 +053066 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
Shawn Guo95ceafd2012-09-06 07:09:11 +000067
Mark Brown4a511de2013-08-13 14:58:24 +020068 if (!IS_ERR(cpu_reg)) {
Nishanth Menon78e8eb82013-01-18 19:52:33 +000069 rcu_read_lock();
Shawn Guo95ceafd2012-09-06 07:09:11 +000070 opp = opp_find_freq_ceil(cpu_dev, &freq_Hz);
71 if (IS_ERR(opp)) {
Nishanth Menon78e8eb82013-01-18 19:52:33 +000072 rcu_read_unlock();
Shawn Guo95ceafd2012-09-06 07:09:11 +000073 pr_err("failed to find OPP for %ld\n", freq_Hz);
Viresh Kumarfd143b42013-04-01 12:57:44 +000074 freqs.new = freqs.old;
75 ret = PTR_ERR(opp);
76 goto post_notify;
Shawn Guo95ceafd2012-09-06 07:09:11 +000077 }
78 volt = opp_get_voltage(opp);
Nishanth Menon78e8eb82013-01-18 19:52:33 +000079 rcu_read_unlock();
Shawn Guo95ceafd2012-09-06 07:09:11 +000080 tol = volt * voltage_tolerance / 100;
81 volt_old = regulator_get_voltage(cpu_reg);
82 }
83
84 pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
85 freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
86 freqs.new / 1000, volt ? volt / 1000 : -1);
87
88 /* scaling up? scale voltage before frequency */
Mark Brown4a511de2013-08-13 14:58:24 +020089 if (!IS_ERR(cpu_reg) && freqs.new > freqs.old) {
Shawn Guo95ceafd2012-09-06 07:09:11 +000090 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
91 if (ret) {
92 pr_err("failed to scale voltage up: %d\n", ret);
93 freqs.new = freqs.old;
Viresh Kumarfd143b42013-04-01 12:57:44 +000094 goto post_notify;
Shawn Guo95ceafd2012-09-06 07:09:11 +000095 }
96 }
97
Guennadi Liakhovetski0ca68432013-02-25 18:22:37 +010098 ret = clk_set_rate(cpu_clk, freq_exact);
Shawn Guo95ceafd2012-09-06 07:09:11 +000099 if (ret) {
100 pr_err("failed to set clock rate: %d\n", ret);
Mark Brown4a511de2013-08-13 14:58:24 +0200101 if (!IS_ERR(cpu_reg))
Shawn Guo95ceafd2012-09-06 07:09:11 +0000102 regulator_set_voltage_tol(cpu_reg, volt_old, tol);
Viresh Kumarfd143b42013-04-01 12:57:44 +0000103 freqs.new = freqs.old;
104 goto post_notify;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000105 }
106
107 /* scaling down? scale voltage after frequency */
Mark Brown4a511de2013-08-13 14:58:24 +0200108 if (!IS_ERR(cpu_reg) && freqs.new < freqs.old) {
Shawn Guo95ceafd2012-09-06 07:09:11 +0000109 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
110 if (ret) {
111 pr_err("failed to scale voltage down: %d\n", ret);
112 clk_set_rate(cpu_clk, freqs.old * 1000);
113 freqs.new = freqs.old;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000114 }
115 }
116
Viresh Kumarfd143b42013-04-01 12:57:44 +0000117post_notify:
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530118 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000119
Viresh Kumarfd143b42013-04-01 12:57:44 +0000120 return ret;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000121}
122
123static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
124{
Viresh Kumar78b3d102013-10-03 20:29:09 +0530125 return cpufreq_generic_init(policy, freq_table, transition_latency);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000126}
127
Shawn Guo95ceafd2012-09-06 07:09:11 +0000128static struct cpufreq_driver cpu0_cpufreq_driver = {
129 .flags = CPUFREQ_STICKY,
Viresh Kumarf793d792013-10-03 20:28:00 +0530130 .verify = cpufreq_generic_frequency_table_verify,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000131 .target = cpu0_set_target,
132 .get = cpu0_get_speed,
133 .init = cpu0_cpufreq_init,
Viresh Kumarf793d792013-10-03 20:28:00 +0530134 .exit = cpufreq_generic_exit,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000135 .name = "generic_cpu0",
Viresh Kumarf793d792013-10-03 20:28:00 +0530136 .attr = cpufreq_generic_attr,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000137};
138
Shawn Guo5553f9e2013-01-30 14:27:49 +0000139static int cpu0_cpufreq_probe(struct platform_device *pdev)
Shawn Guo95ceafd2012-09-06 07:09:11 +0000140{
Sudeep KarkadaNageshaf837a9b2013-06-17 15:04:19 +0100141 struct device_node *np;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000142 int ret;
143
Sudeep KarkadaNageshae1825b22013-09-10 18:59:46 +0100144 cpu_dev = get_cpu_device(0);
145 if (!cpu_dev) {
146 pr_err("failed to get cpu0 device\n");
147 return -ENODEV;
148 }
Paolo Pisatif5c3ef22013-03-28 09:24:29 +0000149
Sudeep KarkadaNageshaf837a9b2013-06-17 15:04:19 +0100150 np = of_node_get(cpu_dev->of_node);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000151 if (!np) {
152 pr_err("failed to find cpu0 node\n");
Sudeep KarkadaNageshaf837a9b2013-06-17 15:04:19 +0100153 return -ENOENT;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000154 }
155
Mark Brown7d748972013-08-09 19:07:12 +0100156 cpu_reg = devm_regulator_get_optional(cpu_dev, "cpu0");
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000157 if (IS_ERR(cpu_reg)) {
158 /*
159 * If cpu0 regulator supply node is present, but regulator is
160 * not yet registered, we should try defering probe.
161 */
162 if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
163 dev_err(cpu_dev, "cpu0 regulator not ready, retry\n");
164 ret = -EPROBE_DEFER;
165 goto out_put_node;
166 }
167 pr_warn("failed to get cpu0 regulator: %ld\n",
168 PTR_ERR(cpu_reg));
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000169 }
170
Shawn Guo5553f9e2013-01-30 14:27:49 +0000171 cpu_clk = devm_clk_get(cpu_dev, NULL);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000172 if (IS_ERR(cpu_clk)) {
173 ret = PTR_ERR(cpu_clk);
174 pr_err("failed to get cpu0 clock: %d\n", ret);
175 goto out_put_node;
176 }
177
Shawn Guo95ceafd2012-09-06 07:09:11 +0000178 ret = of_init_opp_table(cpu_dev);
179 if (ret) {
180 pr_err("failed to init OPP table: %d\n", ret);
181 goto out_put_node;
182 }
183
184 ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
185 if (ret) {
186 pr_err("failed to init cpufreq table: %d\n", ret);
187 goto out_put_node;
188 }
189
190 of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
191
192 if (of_property_read_u32(np, "clock-latency", &transition_latency))
193 transition_latency = CPUFREQ_ETERNAL;
194
195 if (cpu_reg) {
196 struct opp *opp;
197 unsigned long min_uV, max_uV;
198 int i;
199
200 /*
201 * OPP is maintained in order of increasing frequency, and
202 * freq_table initialised from OPP is therefore sorted in the
203 * same order.
204 */
205 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
206 ;
Nishanth Menon78e8eb82013-01-18 19:52:33 +0000207 rcu_read_lock();
Shawn Guo95ceafd2012-09-06 07:09:11 +0000208 opp = opp_find_freq_exact(cpu_dev,
209 freq_table[0].frequency * 1000, true);
210 min_uV = opp_get_voltage(opp);
211 opp = opp_find_freq_exact(cpu_dev,
212 freq_table[i-1].frequency * 1000, true);
213 max_uV = opp_get_voltage(opp);
Nishanth Menon78e8eb82013-01-18 19:52:33 +0000214 rcu_read_unlock();
Shawn Guo95ceafd2012-09-06 07:09:11 +0000215 ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
216 if (ret > 0)
217 transition_latency += ret * 1000;
218 }
219
220 ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
221 if (ret) {
222 pr_err("failed register driver: %d\n", ret);
223 goto out_free_table;
224 }
225
226 of_node_put(np);
227 return 0;
228
229out_free_table:
230 opp_free_cpufreq_table(cpu_dev, &freq_table);
231out_put_node:
232 of_node_put(np);
233 return ret;
234}
Shawn Guo5553f9e2013-01-30 14:27:49 +0000235
236static int cpu0_cpufreq_remove(struct platform_device *pdev)
237{
238 cpufreq_unregister_driver(&cpu0_cpufreq_driver);
239 opp_free_cpufreq_table(cpu_dev, &freq_table);
240
241 return 0;
242}
243
244static struct platform_driver cpu0_cpufreq_platdrv = {
245 .driver = {
246 .name = "cpufreq-cpu0",
247 .owner = THIS_MODULE,
248 },
249 .probe = cpu0_cpufreq_probe,
250 .remove = cpu0_cpufreq_remove,
251};
252module_platform_driver(cpu0_cpufreq_platdrv);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000253
254MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
255MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
256MODULE_LICENSE("GPL");