Kuninori Morimoto | 6c01ba4 | 2011-11-10 18:45:52 -0800 | [diff] [blame^] | 1 | /* |
| 2 | * R8A7740 processor support |
| 3 | * |
| 4 | * Copyright (C) 2011 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/serial_sci.h> |
| 24 | #include <linux/sh_timer.h> |
| 25 | #include <mach/r8a7740.h> |
| 26 | #include <asm/mach-types.h> |
| 27 | #include <asm/mach/arch.h> |
| 28 | |
| 29 | /* SCIFA0 */ |
| 30 | static struct plat_sci_port scif0_platform_data = { |
| 31 | .mapbase = 0xe6c40000, |
| 32 | .flags = UPF_BOOT_AUTOCONF, |
| 33 | .scscr = SCSCR_RE | SCSCR_TE, |
| 34 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 35 | .type = PORT_SCIFA, |
| 36 | .irqs = SCIx_IRQ_MUXED(gic_spi(100)), |
| 37 | }; |
| 38 | |
| 39 | static struct platform_device scif0_device = { |
| 40 | .name = "sh-sci", |
| 41 | .id = 0, |
| 42 | .dev = { |
| 43 | .platform_data = &scif0_platform_data, |
| 44 | }, |
| 45 | }; |
| 46 | |
| 47 | /* SCIFA1 */ |
| 48 | static struct plat_sci_port scif1_platform_data = { |
| 49 | .mapbase = 0xe6c50000, |
| 50 | .flags = UPF_BOOT_AUTOCONF, |
| 51 | .scscr = SCSCR_RE | SCSCR_TE, |
| 52 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 53 | .type = PORT_SCIFA, |
| 54 | .irqs = SCIx_IRQ_MUXED(gic_spi(101)), |
| 55 | }; |
| 56 | |
| 57 | static struct platform_device scif1_device = { |
| 58 | .name = "sh-sci", |
| 59 | .id = 1, |
| 60 | .dev = { |
| 61 | .platform_data = &scif1_platform_data, |
| 62 | }, |
| 63 | }; |
| 64 | |
| 65 | /* SCIFA2 */ |
| 66 | static struct plat_sci_port scif2_platform_data = { |
| 67 | .mapbase = 0xe6c60000, |
| 68 | .flags = UPF_BOOT_AUTOCONF, |
| 69 | .scscr = SCSCR_RE | SCSCR_TE, |
| 70 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 71 | .type = PORT_SCIFA, |
| 72 | .irqs = SCIx_IRQ_MUXED(gic_spi(102)), |
| 73 | }; |
| 74 | |
| 75 | static struct platform_device scif2_device = { |
| 76 | .name = "sh-sci", |
| 77 | .id = 2, |
| 78 | .dev = { |
| 79 | .platform_data = &scif2_platform_data, |
| 80 | }, |
| 81 | }; |
| 82 | |
| 83 | /* SCIFA3 */ |
| 84 | static struct plat_sci_port scif3_platform_data = { |
| 85 | .mapbase = 0xe6c70000, |
| 86 | .flags = UPF_BOOT_AUTOCONF, |
| 87 | .scscr = SCSCR_RE | SCSCR_TE, |
| 88 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 89 | .type = PORT_SCIFA, |
| 90 | .irqs = SCIx_IRQ_MUXED(gic_spi(103)), |
| 91 | }; |
| 92 | |
| 93 | static struct platform_device scif3_device = { |
| 94 | .name = "sh-sci", |
| 95 | .id = 3, |
| 96 | .dev = { |
| 97 | .platform_data = &scif3_platform_data, |
| 98 | }, |
| 99 | }; |
| 100 | |
| 101 | /* SCIFA4 */ |
| 102 | static struct plat_sci_port scif4_platform_data = { |
| 103 | .mapbase = 0xe6c80000, |
| 104 | .flags = UPF_BOOT_AUTOCONF, |
| 105 | .scscr = SCSCR_RE | SCSCR_TE, |
| 106 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 107 | .type = PORT_SCIFA, |
| 108 | .irqs = SCIx_IRQ_MUXED(gic_spi(104)), |
| 109 | }; |
| 110 | |
| 111 | static struct platform_device scif4_device = { |
| 112 | .name = "sh-sci", |
| 113 | .id = 4, |
| 114 | .dev = { |
| 115 | .platform_data = &scif4_platform_data, |
| 116 | }, |
| 117 | }; |
| 118 | |
| 119 | /* SCIFA5 */ |
| 120 | static struct plat_sci_port scif5_platform_data = { |
| 121 | .mapbase = 0xe6cb0000, |
| 122 | .flags = UPF_BOOT_AUTOCONF, |
| 123 | .scscr = SCSCR_RE | SCSCR_TE, |
| 124 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 125 | .type = PORT_SCIFA, |
| 126 | .irqs = SCIx_IRQ_MUXED(gic_spi(105)), |
| 127 | }; |
| 128 | |
| 129 | static struct platform_device scif5_device = { |
| 130 | .name = "sh-sci", |
| 131 | .id = 5, |
| 132 | .dev = { |
| 133 | .platform_data = &scif5_platform_data, |
| 134 | }, |
| 135 | }; |
| 136 | |
| 137 | /* SCIFA6 */ |
| 138 | static struct plat_sci_port scif6_platform_data = { |
| 139 | .mapbase = 0xe6cc0000, |
| 140 | .flags = UPF_BOOT_AUTOCONF, |
| 141 | .scscr = SCSCR_RE | SCSCR_TE, |
| 142 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 143 | .type = PORT_SCIFA, |
| 144 | .irqs = SCIx_IRQ_MUXED(gic_spi(106)), |
| 145 | }; |
| 146 | |
| 147 | static struct platform_device scif6_device = { |
| 148 | .name = "sh-sci", |
| 149 | .id = 6, |
| 150 | .dev = { |
| 151 | .platform_data = &scif6_platform_data, |
| 152 | }, |
| 153 | }; |
| 154 | |
| 155 | /* SCIFA7 */ |
| 156 | static struct plat_sci_port scif7_platform_data = { |
| 157 | .mapbase = 0xe6cd0000, |
| 158 | .flags = UPF_BOOT_AUTOCONF, |
| 159 | .scscr = SCSCR_RE | SCSCR_TE, |
| 160 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 161 | .type = PORT_SCIFA, |
| 162 | .irqs = SCIx_IRQ_MUXED(gic_spi(107)), |
| 163 | }; |
| 164 | |
| 165 | static struct platform_device scif7_device = { |
| 166 | .name = "sh-sci", |
| 167 | .id = 7, |
| 168 | .dev = { |
| 169 | .platform_data = &scif7_platform_data, |
| 170 | }, |
| 171 | }; |
| 172 | |
| 173 | /* SCIFB */ |
| 174 | static struct plat_sci_port scifb_platform_data = { |
| 175 | .mapbase = 0xe6c30000, |
| 176 | .flags = UPF_BOOT_AUTOCONF, |
| 177 | .scscr = SCSCR_RE | SCSCR_TE, |
| 178 | .scbrr_algo_id = SCBRR_ALGO_4, |
| 179 | .type = PORT_SCIFB, |
| 180 | .irqs = SCIx_IRQ_MUXED(gic_spi(108)), |
| 181 | }; |
| 182 | |
| 183 | static struct platform_device scifb_device = { |
| 184 | .name = "sh-sci", |
| 185 | .id = 8, |
| 186 | .dev = { |
| 187 | .platform_data = &scifb_platform_data, |
| 188 | }, |
| 189 | }; |
| 190 | |
| 191 | /* CMT */ |
| 192 | static struct sh_timer_config cmt10_platform_data = { |
| 193 | .name = "CMT10", |
| 194 | .channel_offset = 0x10, |
| 195 | .timer_bit = 0, |
| 196 | .clockevent_rating = 125, |
| 197 | .clocksource_rating = 125, |
| 198 | }; |
| 199 | |
| 200 | static struct resource cmt10_resources[] = { |
| 201 | [0] = { |
| 202 | .name = "CMT10", |
| 203 | .start = 0xe6138010, |
| 204 | .end = 0xe613801b, |
| 205 | .flags = IORESOURCE_MEM, |
| 206 | }, |
| 207 | [1] = { |
| 208 | .start = gic_spi(58), |
| 209 | .flags = IORESOURCE_IRQ, |
| 210 | }, |
| 211 | }; |
| 212 | |
| 213 | static struct platform_device cmt10_device = { |
| 214 | .name = "sh_cmt", |
| 215 | .id = 10, |
| 216 | .dev = { |
| 217 | .platform_data = &cmt10_platform_data, |
| 218 | }, |
| 219 | .resource = cmt10_resources, |
| 220 | .num_resources = ARRAY_SIZE(cmt10_resources), |
| 221 | }; |
| 222 | |
| 223 | static struct platform_device *r8a7740_early_devices[] __initdata = { |
| 224 | &scif0_device, |
| 225 | &scif1_device, |
| 226 | &scif2_device, |
| 227 | &scif3_device, |
| 228 | &scif4_device, |
| 229 | &scif5_device, |
| 230 | &scif6_device, |
| 231 | &scif7_device, |
| 232 | &scifb_device, |
| 233 | &cmt10_device, |
| 234 | }; |
| 235 | |
| 236 | void __init r8a7740_add_standard_devices(void) |
| 237 | { |
| 238 | platform_add_devices(r8a7740_early_devices, |
| 239 | ARRAY_SIZE(r8a7740_early_devices)); |
| 240 | } |
| 241 | |
| 242 | void __init r8a7740_add_early_devices(void) |
| 243 | { |
| 244 | early_platform_add_devices(r8a7740_early_devices, |
| 245 | ARRAY_SIZE(r8a7740_early_devices)); |
| 246 | } |