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review.shift-gmbh.com / SHIFTPHONES / android_kernel_shift_sdm845 / 5fda1b65c2ecb2acaceb4418c16cfd929ac138b3 / . / drivers / media / dvb-frontends / cxd2841er.c
blob: c960e8a725cc50191724f4cc1ac50249d54d5603 [file] [log] [blame]
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1/*
2 * cxd2841er.c
3 *
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]4 * Sony digital demodulator driver for
Abylay Ospan9ca17362016-05-16 11:57:04 -0300[diff] [blame]5 * CXD2841ER - DVB-S/S2/T/T2/C/C2
6 * CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]7 *
8 * Copyright 2012 Sony Corporation
9 * Copyright (C) 2014 NetUP Inc.
10 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
11 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28#include <linux/bitops.h>
29#include <linux/math64.h>
30#include <linux/log2.h>
31#include <linux/dynamic_debug.h>
32
33#include "dvb_math.h"
34#include "dvb_frontend.h"
35#include "cxd2841er.h"
36#include "cxd2841er_priv.h"
37
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]38#define MAX_WRITE_REGSIZE 16
39
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]40enum cxd2841er_state {
41 STATE_SHUTDOWN = 0,
42 STATE_SLEEP_S,
43 STATE_ACTIVE_S,
44 STATE_SLEEP_TC,
45 STATE_ACTIVE_TC
46};
47
48struct cxd2841er_priv {
49 struct dvb_frontend frontend;
50 struct i2c_adapter *i2c;
51 u8 i2c_addr_slvx;
52 u8 i2c_addr_slvt;
53 const struct cxd2841er_config *config;
54 enum cxd2841er_state state;
55 u8 system;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]56 enum cxd2841er_xtal xtal;
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]57 enum fe_caps caps;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]58};
59
60static const struct cxd2841er_cnr_data s_cn_data[] = {
61 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
62 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
63 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
64 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
65 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
66 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
67 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
68 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
69 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
70 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
71 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
72 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
73 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
74 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
75 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
76 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
77 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
78 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
79 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
80 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
81 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
82 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
83 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
84 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
85 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
86 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
87 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
88 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
89 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
90 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
91 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
92 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
93 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
94 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
95 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
96 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
97 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
98 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
99 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
100 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
101 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
102 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
103 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
104 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
105 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
106 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
107 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
108 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
109 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
110 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
111 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
112 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
113 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
114 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
115 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
116 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
117 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
118 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
119 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
120 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
121 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
122 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
123 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
124 { 0x0015, 19900 }, { 0x0014, 20000 },
125};
126
127static const struct cxd2841er_cnr_data s2_cn_data[] = {
128 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
129 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
130 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
131 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
132 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
133 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
134 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
135 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
136 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
137 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
138 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
139 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
140 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
141 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
142 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
143 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
144 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
145 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
146 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
147 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
148 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
149 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
150 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
151 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
152 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
153 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
154 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
155 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
156 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
157 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
158 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
159 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
160 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
161 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
162 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
163 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
164 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
165 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
166 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
167 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
168 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
169 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
170 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
171 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
172 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
173 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
174 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
175 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
176 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
177 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
178 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
179 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
180 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
181 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
182 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
183 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
184 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
185 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
186 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
187 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
188 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
189 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
190 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
191 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
192};
193
194#define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]195#define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
196 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
197 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]198
199static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
200 u8 addr, u8 reg, u8 write,
201 const u8 *data, u32 len)
202{
203 dev_dbg(&priv->i2c->dev,
204 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
205 (write == 0 ? "read" : "write"), addr, reg, len);
206 print_hex_dump_bytes("cxd2841er: I2C data: ",
207 DUMP_PREFIX_OFFSET, data, len);
208}
209
210static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
211 u8 addr, u8 reg, const u8 *data, u32 len)
212{
213 int ret;
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]214 u8 buf[MAX_WRITE_REGSIZE + 1];
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]215 u8 i2c_addr = (addr == I2C_SLVX ?
216 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
217 struct i2c_msg msg[1] = {
218 {
219 .addr = i2c_addr,
220 .flags = 0,
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]221 .len = len + 1,
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]222 .buf = buf,
223 }
224 };
225
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]226 if (len + 1 >= sizeof(buf)) {
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]227 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]228 reg, len + 1);
229 return -E2BIG;
230 }
231
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]232 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
233 buf[0] = reg;
234 memcpy(&buf[1], data, len);
235
236 ret = i2c_transfer(priv->i2c, msg, 1);
237 if (ret >= 0 && ret != 1)
238 ret = -EIO;
239 if (ret < 0) {
240 dev_warn(&priv->i2c->dev,
241 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
242 KBUILD_MODNAME, ret, i2c_addr, reg, len);
243 return ret;
244 }
245 return 0;
246}
247
248static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
249 u8 addr, u8 reg, u8 val)
250{
251 return cxd2841er_write_regs(priv, addr, reg, &val, 1);
252}
253
254static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
255 u8 addr, u8 reg, u8 *val, u32 len)
256{
257 int ret;
258 u8 i2c_addr = (addr == I2C_SLVX ?
259 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
260 struct i2c_msg msg[2] = {
261 {
262 .addr = i2c_addr,
263 .flags = 0,
264 .len = 1,
265 .buf = &reg,
266 }, {
267 .addr = i2c_addr,
268 .flags = I2C_M_RD,
269 .len = len,
270 .buf = val,
271 }
272 };
273
274 ret = i2c_transfer(priv->i2c, &msg[0], 1);
275 if (ret >= 0 && ret != 1)
276 ret = -EIO;
277 if (ret < 0) {
278 dev_warn(&priv->i2c->dev,
279 "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
280 KBUILD_MODNAME, ret, i2c_addr, reg);
281 return ret;
282 }
283 ret = i2c_transfer(priv->i2c, &msg[1], 1);
284 if (ret >= 0 && ret != 1)
285 ret = -EIO;
286 if (ret < 0) {
287 dev_warn(&priv->i2c->dev,
288 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
289 KBUILD_MODNAME, ret, i2c_addr, reg);
290 return ret;
291 }
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]292 cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]293 return 0;
294}
295
296static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
297 u8 addr, u8 reg, u8 *val)
298{
299 return cxd2841er_read_regs(priv, addr, reg, val, 1);
300}
301
302static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
303 u8 addr, u8 reg, u8 data, u8 mask)
304{
305 int res;
306 u8 rdata;
307
308 if (mask != 0xff) {
309 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
310 if (res)
311 return res;
312 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
313 }
314 return cxd2841er_write_reg(priv, addr, reg, data);
315}
316
317static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
318 u32 symbol_rate)
319{
320 u32 reg_value = 0;
321 u8 data[3] = {0, 0, 0};
322
323 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
324 /*
325 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
326 * = ((symbolRateKSps * 2^14) + 500) / 1000
327 * = ((symbolRateKSps * 16384) + 500) / 1000
328 */
329 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
330 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
331 dev_err(&priv->i2c->dev,
332 "%s(): reg_value is out of range\n", __func__);
333 return -EINVAL;
334 }
335 data[0] = (u8)((reg_value >> 16) & 0x0F);
336 data[1] = (u8)((reg_value >> 8) & 0xFF);
337 data[2] = (u8)(reg_value & 0xFF);
338 /* Set SLV-T Bank : 0xAE */
339 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
340 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
341 return 0;
342}
343
344static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
345 u8 system);
346
347static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
348 u8 system, u32 symbol_rate)
349{
350 int ret;
351 u8 data[4] = { 0, 0, 0, 0 };
352
353 if (priv->state != STATE_SLEEP_S) {
354 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
355 __func__, (int)priv->state);
356 return -EINVAL;
357 }
358 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
359 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
360 /* Set demod mode */
361 if (system == SYS_DVBS) {
362 data[0] = 0x0A;
363 } else if (system == SYS_DVBS2) {
364 data[0] = 0x0B;
365 } else {
366 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
367 __func__, system);
368 return -EINVAL;
369 }
370 /* Set SLV-X Bank : 0x00 */
371 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
372 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
373 /* DVB-S/S2 */
374 data[0] = 0x00;
375 /* Set SLV-T Bank : 0x00 */
376 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
377 /* Enable S/S2 auto detection 1 */
378 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
379 /* Set SLV-T Bank : 0xAE */
380 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
381 /* Enable S/S2 auto detection 2 */
382 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
383 /* Set SLV-T Bank : 0x00 */
384 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
385 /* Enable demod clock */
386 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
387 /* Enable ADC clock */
388 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
389 /* Enable ADC 1 */
390 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
391 /* Enable ADC 2 */
392 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
393 /* Set SLV-X Bank : 0x00 */
394 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
395 /* Enable ADC 3 */
396 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
397 /* Set SLV-T Bank : 0xA3 */
398 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
399 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
400 data[0] = 0x07;
401 data[1] = 0x3B;
402 data[2] = 0x08;
403 data[3] = 0xC5;
404 /* Set SLV-T Bank : 0xAB */
405 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
406 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
407 data[0] = 0x05;
408 data[1] = 0x80;
409 data[2] = 0x0A;
410 data[3] = 0x80;
411 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
412 data[0] = 0x0C;
413 data[1] = 0xCC;
414 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
415 /* Set demod parameter */
416 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
417 if (ret != 0)
418 return ret;
419 /* Set SLV-T Bank : 0x00 */
420 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
421 /* disable Hi-Z setting 1 */
422 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
423 /* disable Hi-Z setting 2 */
424 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
425 priv->state = STATE_ACTIVE_S;
426 return 0;
427}
428
429static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
430 u32 bandwidth);
431
432static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
433 u32 bandwidth);
434
435static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
436 u32 bandwidth);
437
Mauro Carvalho Chehab76344a3f2016-05-04 18:25:38 -0300[diff] [blame]438static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
439 u32 bandwidth);
440
441static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
442
443static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
444
445static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
446
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]447static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
448 struct dtv_frontend_properties *p)
449{
450 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
451 if (priv->state != STATE_ACTIVE_S &&
452 priv->state != STATE_ACTIVE_TC) {
453 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
454 __func__, priv->state);
455 return -EINVAL;
456 }
457 /* Set SLV-T Bank : 0x00 */
458 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
459 /* disable TS output */
460 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
461 if (priv->state == STATE_ACTIVE_S)
462 return cxd2841er_dvbs2_set_symbol_rate(
463 priv, p->symbol_rate / 1000);
464 else if (priv->state == STATE_ACTIVE_TC) {
465 switch (priv->system) {
466 case SYS_DVBT:
467 return cxd2841er_sleep_tc_to_active_t_band(
468 priv, p->bandwidth_hz);
469 case SYS_DVBT2:
470 return cxd2841er_sleep_tc_to_active_t2_band(
471 priv, p->bandwidth_hz);
472 case SYS_DVBC_ANNEX_A:
473 return cxd2841er_sleep_tc_to_active_c_band(
Mauro Carvalho Chehab76344a3f2016-05-04 18:25:38 -0300[diff] [blame]474 priv, p->bandwidth_hz);
475 case SYS_ISDBT:
476 cxd2841er_active_i_to_sleep_tc(priv);
477 cxd2841er_sleep_tc_to_shutdown(priv);
478 cxd2841er_shutdown_to_sleep_tc(priv);
479 return cxd2841er_sleep_tc_to_active_i(
480 priv, p->bandwidth_hz);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]481 }
482 }
483 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
484 __func__, priv->system);
485 return -EINVAL;
486}
487
488static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
489{
490 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
491 if (priv->state != STATE_ACTIVE_S) {
492 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
493 __func__, priv->state);
494 return -EINVAL;
495 }
496 /* Set SLV-T Bank : 0x00 */
497 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
498 /* disable TS output */
499 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
500 /* enable Hi-Z setting 1 */
501 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
502 /* enable Hi-Z setting 2 */
503 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
504 /* Set SLV-X Bank : 0x00 */
505 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
506 /* disable ADC 1 */
507 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
508 /* Set SLV-T Bank : 0x00 */
509 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
510 /* disable ADC clock */
511 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
512 /* disable ADC 2 */
513 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
514 /* disable ADC 3 */
515 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
516 /* SADC Bias ON */
517 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
518 /* disable demod clock */
519 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
520 /* Set SLV-T Bank : 0xAE */
521 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
522 /* disable S/S2 auto detection1 */
523 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
524 /* Set SLV-T Bank : 0x00 */
525 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
526 /* disable S/S2 auto detection2 */
527 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
528 priv->state = STATE_SLEEP_S;
529 return 0;
530}
531
532static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
533{
534 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
535 if (priv->state != STATE_SLEEP_S) {
536 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
537 __func__, priv->state);
538 return -EINVAL;
539 }
540 /* Set SLV-T Bank : 0x00 */
541 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
542 /* Disable DSQOUT */
543 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
544 /* Disable DSQIN */
545 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
546 /* Set SLV-X Bank : 0x00 */
547 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
548 /* Disable oscillator */
549 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
550 /* Set demod mode */
551 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
552 priv->state = STATE_SHUTDOWN;
553 return 0;
554}
555
556static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
557{
558 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
559 if (priv->state != STATE_SLEEP_TC) {
560 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
561 __func__, priv->state);
562 return -EINVAL;
563 }
564 /* Set SLV-X Bank : 0x00 */
565 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
566 /* Disable oscillator */
567 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
568 /* Set demod mode */
569 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
570 priv->state = STATE_SHUTDOWN;
571 return 0;
572}
573
574static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
575{
576 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
577 if (priv->state != STATE_ACTIVE_TC) {
578 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
579 __func__, priv->state);
580 return -EINVAL;
581 }
582 /* Set SLV-T Bank : 0x00 */
583 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
584 /* disable TS output */
585 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
586 /* enable Hi-Z setting 1 */
587 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
588 /* enable Hi-Z setting 2 */
589 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
590 /* Set SLV-X Bank : 0x00 */
591 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
592 /* disable ADC 1 */
593 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
594 /* Set SLV-T Bank : 0x00 */
595 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
596 /* Disable ADC 2 */
597 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
598 /* Disable ADC 3 */
599 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
600 /* Disable ADC clock */
601 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
602 /* Disable RF level monitor */
603 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
604 /* Disable demod clock */
605 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
606 priv->state = STATE_SLEEP_TC;
607 return 0;
608}
609
610static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
611{
612 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
613 if (priv->state != STATE_ACTIVE_TC) {
614 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
615 __func__, priv->state);
616 return -EINVAL;
617 }
618 /* Set SLV-T Bank : 0x00 */
619 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
620 /* disable TS output */
621 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
622 /* enable Hi-Z setting 1 */
623 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
624 /* enable Hi-Z setting 2 */
625 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
626 /* Cancel DVB-T2 setting */
627 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
628 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
629 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
630 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
631 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
632 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
633 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
634 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
635 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
636 /* Set SLV-X Bank : 0x00 */
637 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
638 /* disable ADC 1 */
639 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
640 /* Set SLV-T Bank : 0x00 */
641 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
642 /* Disable ADC 2 */
643 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
644 /* Disable ADC 3 */
645 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
646 /* Disable ADC clock */
647 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
648 /* Disable RF level monitor */
649 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
650 /* Disable demod clock */
651 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
652 priv->state = STATE_SLEEP_TC;
653 return 0;
654}
655
656static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
657{
658 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
659 if (priv->state != STATE_ACTIVE_TC) {
660 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
661 __func__, priv->state);
662 return -EINVAL;
663 }
664 /* Set SLV-T Bank : 0x00 */
665 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
666 /* disable TS output */
667 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
668 /* enable Hi-Z setting 1 */
669 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
670 /* enable Hi-Z setting 2 */
671 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
672 /* Cancel DVB-C setting */
673 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
674 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
675 /* Set SLV-X Bank : 0x00 */
676 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
677 /* disable ADC 1 */
678 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
679 /* Set SLV-T Bank : 0x00 */
680 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
681 /* Disable ADC 2 */
682 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
683 /* Disable ADC 3 */
684 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
685 /* Disable ADC clock */
686 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
687 /* Disable RF level monitor */
688 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
689 /* Disable demod clock */
690 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
691 priv->state = STATE_SLEEP_TC;
692 return 0;
693}
694
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]695static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
696{
697 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
698 if (priv->state != STATE_ACTIVE_TC) {
699 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
700 __func__, priv->state);
701 return -EINVAL;
702 }
703 /* Set SLV-T Bank : 0x00 */
704 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
705 /* disable TS output */
706 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
707 /* enable Hi-Z setting 1 */
708 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
709 /* enable Hi-Z setting 2 */
710 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
711
712 /* TODO: Cancel demod parameter */
713
714 /* Set SLV-X Bank : 0x00 */
715 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
716 /* disable ADC 1 */
717 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
718 /* Set SLV-T Bank : 0x00 */
719 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
720 /* Disable ADC 2 */
721 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
722 /* Disable ADC 3 */
723 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
724 /* Disable ADC clock */
725 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
726 /* Disable RF level monitor */
727 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
728 /* Disable demod clock */
729 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
730 priv->state = STATE_SLEEP_TC;
731 return 0;
732}
733
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]734static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
735{
736 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
737 if (priv->state != STATE_SHUTDOWN) {
738 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
739 __func__, priv->state);
740 return -EINVAL;
741 }
742 /* Set SLV-X Bank : 0x00 */
743 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
744 /* Clear all demodulator registers */
745 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
746 usleep_range(3000, 5000);
747 /* Set SLV-X Bank : 0x00 */
748 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
749 /* Set demod SW reset */
750 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]751
752 switch (priv->xtal) {
753 case SONY_XTAL_20500:
754 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
755 break;
756 case SONY_XTAL_24000:
757 /* Select demod frequency */
758 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
759 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
760 break;
761 case SONY_XTAL_41000:
762 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
763 break;
764 default:
765 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
766 __func__, priv->xtal);
767 return -EINVAL;
768 }
769
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]770 /* Set demod mode */
771 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
772 /* Clear demod SW reset */
773 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
774 usleep_range(1000, 2000);
775 /* Set SLV-T Bank : 0x00 */
776 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
777 /* enable DSQOUT */
778 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
779 /* enable DSQIN */
780 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
781 /* TADC Bias On */
782 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
783 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
784 /* SADC Bias On */
785 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
786 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
787 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
788 priv->state = STATE_SLEEP_S;
789 return 0;
790}
791
792static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
793{
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]794 u8 data = 0;
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]795
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]796 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
797 if (priv->state != STATE_SHUTDOWN) {
798 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
799 __func__, priv->state);
800 return -EINVAL;
801 }
802 /* Set SLV-X Bank : 0x00 */
803 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
804 /* Clear all demodulator registers */
805 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
806 usleep_range(3000, 5000);
807 /* Set SLV-X Bank : 0x00 */
808 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
809 /* Set demod SW reset */
810 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]811 /* Select ADC clock mode */
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]812 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]813
814 switch (priv->xtal) {
815 case SONY_XTAL_20500:
816 data = 0x0;
817 break;
818 case SONY_XTAL_24000:
819 /* Select demod frequency */
820 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
821 data = 0x3;
822 break;
823 case SONY_XTAL_41000:
824 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
825 data = 0x1;
826 break;
827 }
828 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]829 /* Clear demod SW reset */
830 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
831 usleep_range(1000, 2000);
832 /* Set SLV-T Bank : 0x00 */
833 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
834 /* TADC Bias On */
835 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
836 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
837 /* SADC Bias On */
838 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
839 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
840 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
841 priv->state = STATE_SLEEP_TC;
842 return 0;
843}
844
845static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
846{
847 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
848 /* Set SLV-T Bank : 0x00 */
849 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
850 /* SW Reset */
851 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
852 /* Enable TS output */
853 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
854 return 0;
855}
856
857/* Set TS parallel mode */
858static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
859 u8 system)
860{
861 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
862
863 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
864 /* Set SLV-T Bank : 0x00 */
865 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
866 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
867 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
868 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
869 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
870 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
871
872 /*
873 * slave Bank Addr Bit default Name
874 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
875 */
876 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
877 /*
878 * Disable TS IF Clock
879 * slave Bank Addr Bit default Name
880 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
881 */
882 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
883 /*
884 * slave Bank Addr Bit default Name
885 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
886 */
887 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
888 /*
889 * Enable TS IF Clock
890 * slave Bank Addr Bit default Name
891 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
892 */
893 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
894
895 if (system == SYS_DVBT) {
896 /* Enable parity period for DVB-T */
897 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
898 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
899 } else if (system == SYS_DVBC_ANNEX_A) {
900 /* Enable parity period for DVB-C */
901 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
902 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
903 }
904}
905
906static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
907{
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]908 u8 chip_id = 0;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]909
910 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]911 if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
912 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
913 else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
914 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
915
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]916 return chip_id;
917}
918
919static int cxd2841er_read_status_s(struct dvb_frontend *fe,
920 enum fe_status *status)
921{
922 u8 reg = 0;
923 struct cxd2841er_priv *priv = fe->demodulator_priv;
924
925 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
926 *status = 0;
927 if (priv->state != STATE_ACTIVE_S) {
928 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
929 __func__, priv->state);
930 return -EINVAL;
931 }
932 /* Set SLV-T Bank : 0xA0 */
933 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
934 /*
935 * slave Bank Addr Bit Signal name
936 * <SLV-T> A0h 11h [2] ITSLOCK
937 */
938 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
939 if (reg & 0x04) {
940 *status = FE_HAS_SIGNAL
941 | FE_HAS_CARRIER
942 | FE_HAS_VITERBI
943 | FE_HAS_SYNC
944 | FE_HAS_LOCK;
945 }
946 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
947 return 0;
948}
949
950static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
951 u8 *sync, u8 *tslock, u8 *unlock)
952{
953 u8 data = 0;
954
955 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
956 if (priv->state != STATE_ACTIVE_TC)
957 return -EINVAL;
958 if (priv->system == SYS_DVBT) {
959 /* Set SLV-T Bank : 0x10 */
960 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
961 } else {
962 /* Set SLV-T Bank : 0x20 */
963 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
964 }
965 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
966 if ((data & 0x07) == 0x07) {
967 dev_dbg(&priv->i2c->dev,
968 "%s(): invalid hardware state detected\n", __func__);
969 *sync = 0;
970 *tslock = 0;
971 *unlock = 0;
972 } else {
973 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
974 *tslock = ((data & 0x20) ? 1 : 0);
975 *unlock = ((data & 0x10) ? 1 : 0);
976 }
977 return 0;
978}
979
980static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
981{
982 u8 data;
983
984 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
985 if (priv->state != STATE_ACTIVE_TC)
986 return -EINVAL;
987 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
988 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
989 if ((data & 0x01) == 0) {
990 *tslock = 0;
991 } else {
992 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
993 *tslock = ((data & 0x20) ? 1 : 0);
994 }
995 return 0;
996}
997
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]998static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
999 u8 *sync, u8 *tslock, u8 *unlock)
1000{
1001 u8 data = 0;
1002
1003 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1004 if (priv->state != STATE_ACTIVE_TC)
1005 return -EINVAL;
1006 /* Set SLV-T Bank : 0x60 */
1007 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1008 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1009 dev_dbg(&priv->i2c->dev,
1010 "%s(): lock=0x%x\n", __func__, data);
1011 *sync = ((data & 0x02) ? 1 : 0);
1012 *tslock = ((data & 0x01) ? 1 : 0);
1013 *unlock = ((data & 0x10) ? 1 : 0);
1014 return 0;
1015}
1016
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1017static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1018 enum fe_status *status)
1019{
1020 int ret = 0;
1021 u8 sync = 0;
1022 u8 tslock = 0;
1023 u8 unlock = 0;
1024 struct cxd2841er_priv *priv = fe->demodulator_priv;
1025
1026 *status = 0;
1027 if (priv->state == STATE_ACTIVE_TC) {
1028 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1029 ret = cxd2841er_read_status_t_t2(
1030 priv, &sync, &tslock, &unlock);
1031 if (ret)
1032 goto done;
1033 if (unlock)
1034 goto done;
1035 if (sync)
1036 *status = FE_HAS_SIGNAL |
1037 FE_HAS_CARRIER |
1038 FE_HAS_VITERBI |
1039 FE_HAS_SYNC;
1040 if (tslock)
1041 *status |= FE_HAS_LOCK;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1042 } else if (priv->system == SYS_ISDBT) {
1043 ret = cxd2841er_read_status_i(
1044 priv, &sync, &tslock, &unlock);
1045 if (ret)
1046 goto done;
1047 if (unlock)
1048 goto done;
1049 if (sync)
1050 *status = FE_HAS_SIGNAL |
1051 FE_HAS_CARRIER |
1052 FE_HAS_VITERBI |
1053 FE_HAS_SYNC;
1054 if (tslock)
1055 *status |= FE_HAS_LOCK;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1056 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1057 ret = cxd2841er_read_status_c(priv, &tslock);
1058 if (ret)
1059 goto done;
1060 if (tslock)
1061 *status = FE_HAS_SIGNAL |
1062 FE_HAS_CARRIER |
1063 FE_HAS_VITERBI |
1064 FE_HAS_SYNC |
1065 FE_HAS_LOCK;
1066 }
1067 }
1068done:
1069 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1070 return ret;
1071}
1072
1073static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1074 int *offset)
1075{
1076 u8 data[3];
1077 u8 is_hs_mode;
1078 s32 cfrl_ctrlval;
1079 s32 temp_div, temp_q, temp_r;
1080
1081 if (priv->state != STATE_ACTIVE_S) {
1082 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1083 __func__, priv->state);
1084 return -EINVAL;
1085 }
1086 /*
1087 * Get High Sampling Rate mode
1088 * slave Bank Addr Bit Signal name
1089 * <SLV-T> A0h 10h [0] ITRL_LOCK
1090 */
1091 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1092 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1093 if (data[0] & 0x01) {
1094 /*
1095 * slave Bank Addr Bit Signal name
1096 * <SLV-T> A0h 50h [4] IHSMODE
1097 */
1098 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1099 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1100 } else {
1101 dev_dbg(&priv->i2c->dev,
1102 "%s(): unable to detect sampling rate mode\n",
1103 __func__);
1104 return -EINVAL;
1105 }
1106 /*
1107 * slave Bank Addr Bit Signal name
1108 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
1109 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
1110 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
1111 */
1112 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1113 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1114 (((u32)data[1] & 0xFF) << 8) |
1115 ((u32)data[2] & 0xFF), 20);
1116 temp_div = (is_hs_mode ? 1048576 : 1572864);
1117 if (cfrl_ctrlval > 0) {
1118 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1119 temp_div, &temp_r);
1120 } else {
1121 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1122 temp_div, &temp_r);
1123 }
1124 if (temp_r >= temp_div / 2)
1125 temp_q++;
1126 if (cfrl_ctrlval > 0)
1127 temp_q *= -1;
1128 *offset = temp_q;
1129 return 0;
1130}
1131
Mauro Carvalho Chehab76344a3f2016-05-04 18:25:38 -0300[diff] [blame]1132static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1133 u32 bandwidth, int *offset)
1134{
1135 u8 data[4];
1136
1137 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1138 if (priv->state != STATE_ACTIVE_TC) {
1139 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1140 __func__, priv->state);
1141 return -EINVAL;
1142 }
1143 if (priv->system != SYS_ISDBT) {
1144 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1145 __func__, priv->system);
1146 return -EINVAL;
1147 }
1148 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1149 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1150 *offset = -1 * sign_extend32(
1151 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1152 ((u32)data[2] << 8) | (u32)data[3], 29);
1153
1154 switch (bandwidth) {
1155 case 6000000:
1156 *offset = -1 * ((*offset) * 8/264);
1157 break;
1158 case 7000000:
1159 *offset = -1 * ((*offset) * 8/231);
1160 break;
1161 case 8000000:
1162 *offset = -1 * ((*offset) * 8/198);
1163 break;
1164 default:
1165 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1166 __func__, bandwidth);
1167 return -EINVAL;
1168 }
1169
1170 dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1171 __func__, bandwidth, *offset);
1172
1173 return 0;
1174}
1175
Abylay Ospanc5ea46d2016-04-02 23:31:50 -0300[diff] [blame]1176static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1177 u32 bandwidth, int *offset)
1178{
1179 u8 data[4];
1180
1181 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1182 if (priv->state != STATE_ACTIVE_TC) {
1183 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1184 __func__, priv->state);
1185 return -EINVAL;
1186 }
1187 if (priv->system != SYS_DVBT) {
1188 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1189 __func__, priv->system);
1190 return -EINVAL;
1191 }
1192 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1193 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1194 *offset = -1 * sign_extend32(
1195 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1196 ((u32)data[2] << 8) | (u32)data[3], 29);
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1197 *offset *= (bandwidth / 1000000);
1198 *offset /= 235;
Abylay Ospanc5ea46d2016-04-02 23:31:50 -0300[diff] [blame]1199 return 0;
1200}
1201
Mauro Carvalho Chehabc8946c82015-08-11 15:08:47 -0300[diff] [blame]1202static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1203 u32 bandwidth, int *offset)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1204{
1205 u8 data[4];
1206
1207 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1208 if (priv->state != STATE_ACTIVE_TC) {
1209 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1210 __func__, priv->state);
1211 return -EINVAL;
1212 }
1213 if (priv->system != SYS_DVBT2) {
1214 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1215 __func__, priv->system);
1216 return -EINVAL;
1217 }
1218 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1219 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1220 *offset = -1 * sign_extend32(
1221 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1222 ((u32)data[2] << 8) | (u32)data[3], 27);
1223 switch (bandwidth) {
1224 case 1712000:
1225 *offset /= 582;
1226 break;
1227 case 5000000:
1228 case 6000000:
1229 case 7000000:
1230 case 8000000:
1231 *offset *= (bandwidth / 1000000);
1232 *offset /= 940;
1233 break;
1234 default:
1235 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1236 __func__, bandwidth);
1237 return -EINVAL;
1238 }
1239 return 0;
1240}
1241
Mauro Carvalho Chehabc8946c82015-08-11 15:08:47 -0300[diff] [blame]1242static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1243 int *offset)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1244{
1245 u8 data[2];
1246
1247 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1248 if (priv->state != STATE_ACTIVE_TC) {
1249 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1250 __func__, priv->state);
1251 return -EINVAL;
1252 }
1253 if (priv->system != SYS_DVBC_ANNEX_A) {
1254 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1255 __func__, priv->system);
1256 return -EINVAL;
1257 }
1258 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1259 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1260 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1261 | (u32)data[1], 13), 16384);
1262 return 0;
1263}
1264
1265static int cxd2841er_read_packet_errors_t(
1266 struct cxd2841er_priv *priv, u32 *penum)
1267{
1268 u8 data[3];
1269
1270 *penum = 0;
1271 if (priv->state != STATE_ACTIVE_TC) {
1272 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1273 __func__, priv->state);
1274 return -EINVAL;
1275 }
1276 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1277 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1278 if (data[2] & 0x01)
1279 *penum = ((u32)data[0] << 8) | (u32)data[1];
1280 return 0;
1281}
1282
1283static int cxd2841er_read_packet_errors_t2(
1284 struct cxd2841er_priv *priv, u32 *penum)
1285{
1286 u8 data[3];
1287
1288 *penum = 0;
1289 if (priv->state != STATE_ACTIVE_TC) {
1290 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1291 __func__, priv->state);
1292 return -EINVAL;
1293 }
1294 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1295 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1296 if (data[0] & 0x01)
1297 *penum = ((u32)data[1] << 8) | (u32)data[2];
1298 return 0;
1299}
1300
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1301static int cxd2841er_read_packet_errors_i(
1302 struct cxd2841er_priv *priv, u32 *penum)
1303{
1304 u8 data[2];
1305
1306 *penum = 0;
1307 if (priv->state != STATE_ACTIVE_TC) {
1308 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1309 __func__, priv->state);
1310 return -EINVAL;
1311 }
1312 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1313 cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1314
1315 if (!(data[0] & 0x01))
1316 return 0;
1317
1318 /* Layer A */
1319 cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1320 *penum = ((u32)data[0] << 8) | (u32)data[1];
1321
1322 /* Layer B */
1323 cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1324 *penum += ((u32)data[0] << 8) | (u32)data[1];
1325
1326 /* Layer C */
1327 cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1328 *penum += ((u32)data[0] << 8) | (u32)data[1];
1329
1330 return 0;
1331}
1332
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1333static u32 cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv)
1334{
1335 u8 data[11];
1336 u32 bit_error, bit_count;
1337 u32 temp_q, temp_r;
1338
1339 /* Set SLV-T Bank : 0xA0 */
1340 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1341 /*
1342 * slave Bank Addr Bit Signal name
1343 * <SLV-T> A0h 35h [0] IFVBER_VALID
1344 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1345 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1346 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1347 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1348 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1349 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1350 */
1351 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1352 if (data[0] & 0x01) {
1353 bit_error = ((u32)(data[1] & 0x3F) << 16) |
1354 ((u32)(data[2] & 0xFF) << 8) |
1355 (u32)(data[3] & 0xFF);
1356 bit_count = ((u32)(data[8] & 0x3F) << 16) |
1357 ((u32)(data[9] & 0xFF) << 8) |
1358 (u32)(data[10] & 0xFF);
1359 /*
1360 * BER = bitError / bitCount
1361 * = (bitError * 10^7) / bitCount
1362 * = ((bitError * 625 * 125 * 128) / bitCount
1363 */
1364 if ((bit_count == 0) || (bit_error > bit_count)) {
1365 dev_dbg(&priv->i2c->dev,
1366 "%s(): invalid bit_error %d, bit_count %d\n",
1367 __func__, bit_error, bit_count);
1368 return 0;
1369 }
1370 temp_q = div_u64_rem(10000000ULL * bit_error,
1371 bit_count, &temp_r);
1372 if (bit_count != 1 && temp_r >= bit_count / 2)
1373 temp_q++;
1374 return temp_q;
1375 }
1376 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1377 return 0;
1378}
1379
1380
1381static u32 cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv)
1382{
1383 u8 data[5];
1384 u32 bit_error, period;
1385 u32 temp_q, temp_r;
1386 u32 result = 0;
1387
1388 /* Set SLV-T Bank : 0xB2 */
1389 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1390 /*
1391 * slave Bank Addr Bit Signal name
1392 * <SLV-T> B2h 30h [0] IFLBER_VALID
1393 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1394 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1395 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1396 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1397 */
1398 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1399 if (data[0] & 0x01) {
1400 /* Bit error count */
1401 bit_error = ((u32)(data[1] & 0x0F) << 24) |
1402 ((u32)(data[2] & 0xFF) << 16) |
1403 ((u32)(data[3] & 0xFF) << 8) |
1404 (u32)(data[4] & 0xFF);
1405
1406 /* Set SLV-T Bank : 0xA0 */
1407 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1408 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1409 /* Measurement period */
1410 period = (u32)(1 << (data[0] & 0x0F));
1411 if (period == 0) {
1412 dev_dbg(&priv->i2c->dev,
1413 "%s(): period is 0\n", __func__);
1414 return 0;
1415 }
1416 if (bit_error > (period * 64800)) {
1417 dev_dbg(&priv->i2c->dev,
1418 "%s(): invalid bit_err 0x%x period 0x%x\n",
1419 __func__, bit_error, period);
1420 return 0;
1421 }
1422 /*
1423 * BER = bitError / (period * 64800)
1424 * = (bitError * 10^7) / (period * 64800)
1425 * = (bitError * 10^5) / (period * 648)
1426 * = (bitError * 12500) / (period * 81)
1427 * = (bitError * 10) * 1250 / (period * 81)
1428 */
1429 temp_q = div_u64_rem(12500ULL * bit_error,
1430 period * 81, &temp_r);
1431 if (temp_r >= period * 40)
1432 temp_q++;
1433 result = temp_q;
1434 } else {
1435 dev_dbg(&priv->i2c->dev,
1436 "%s(): no data available\n", __func__);
1437 }
1438 return result;
1439}
1440
1441static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv, u32 *ber)
1442{
1443 u8 data[4];
1444 u32 div, q, r;
1445 u32 bit_err, period_exp, n_ldpc;
1446
1447 *ber = 0;
1448 if (priv->state != STATE_ACTIVE_TC) {
1449 dev_dbg(&priv->i2c->dev,
1450 "%s(): invalid state %d\n", __func__, priv->state);
1451 return -EINVAL;
1452 }
1453 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1454 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1455 if (!(data[0] & 0x10)) {
1456 dev_dbg(&priv->i2c->dev,
1457 "%s(): no valid BER data\n", __func__);
1458 return 0;
1459 }
1460 bit_err = ((u32)(data[0] & 0x0f) << 24) |
1461 ((u32)data[1] << 16) |
1462 ((u32)data[2] << 8) |
1463 (u32)data[3];
1464 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1465 period_exp = data[0] & 0x0f;
1466 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1467 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1468 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1469 if (bit_err > ((1U << period_exp) * n_ldpc)) {
1470 dev_dbg(&priv->i2c->dev,
1471 "%s(): invalid BER value\n", __func__);
1472 return -EINVAL;
1473 }
1474 if (period_exp >= 4) {
1475 div = (1U << (period_exp - 4)) * (n_ldpc / 200);
1476 q = div_u64_rem(3125ULL * bit_err, div, &r);
1477 } else {
1478 div = (1U << period_exp) * (n_ldpc / 200);
1479 q = div_u64_rem(50000ULL * bit_err, div, &r);
1480 }
1481 *ber = (r >= div / 2) ? q + 1 : q;
1482 return 0;
1483}
1484
1485static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv, u32 *ber)
1486{
1487 u8 data[2];
1488 u32 div, q, r;
1489 u32 bit_err, period;
1490
1491 *ber = 0;
1492 if (priv->state != STATE_ACTIVE_TC) {
1493 dev_dbg(&priv->i2c->dev,
1494 "%s(): invalid state %d\n", __func__, priv->state);
1495 return -EINVAL;
1496 }
1497 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1498 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1499 if (!(data[0] & 0x01)) {
1500 dev_dbg(&priv->i2c->dev,
1501 "%s(): no valid BER data\n", __func__);
1502 return 0;
1503 }
1504 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1505 bit_err = ((u32)data[0] << 8) | (u32)data[1];
1506 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1507 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1508 div = period / 128;
1509 q = div_u64_rem(78125ULL * bit_err, div, &r);
1510 *ber = (r >= div / 2) ? q + 1 : q;
1511 return 0;
1512}
1513
1514static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys)
1515{
1516 u8 data[3];
1517 u32 res = 0, value;
1518 int min_index, max_index, index;
1519 static const struct cxd2841er_cnr_data *cn_data;
1520
1521 /* Set SLV-T Bank : 0xA1 */
1522 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1523 /*
1524 * slave Bank Addr Bit Signal name
1525 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1526 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1527 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1528 */
1529 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1530 if (data[0] & 0x01) {
1531 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1532 min_index = 0;
1533 if (delsys == SYS_DVBS) {
1534 cn_data = s_cn_data;
1535 max_index = sizeof(s_cn_data) /
1536 sizeof(s_cn_data[0]) - 1;
1537 } else {
1538 cn_data = s2_cn_data;
1539 max_index = sizeof(s2_cn_data) /
1540 sizeof(s2_cn_data[0]) - 1;
1541 }
1542 if (value >= cn_data[min_index].value) {
1543 res = cn_data[min_index].cnr_x1000;
1544 goto done;
1545 }
1546 if (value <= cn_data[max_index].value) {
1547 res = cn_data[max_index].cnr_x1000;
1548 goto done;
1549 }
1550 while ((max_index - min_index) > 1) {
1551 index = (max_index + min_index) / 2;
1552 if (value == cn_data[index].value) {
1553 res = cn_data[index].cnr_x1000;
1554 goto done;
1555 } else if (value > cn_data[index].value)
1556 max_index = index;
1557 else
1558 min_index = index;
1559 if ((max_index - min_index) <= 1) {
1560 if (value == cn_data[max_index].value) {
1561 res = cn_data[max_index].cnr_x1000;
1562 goto done;
1563 } else {
1564 res = cn_data[min_index].cnr_x1000;
1565 goto done;
1566 }
1567 }
1568 }
1569 } else {
1570 dev_dbg(&priv->i2c->dev,
1571 "%s(): no data available\n", __func__);
1572 }
1573done:
1574 return res;
1575}
1576
1577static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1578{
1579 u32 reg;
1580 u8 data[2];
1581
1582 *snr = 0;
1583 if (priv->state != STATE_ACTIVE_TC) {
1584 dev_dbg(&priv->i2c->dev,
1585 "%s(): invalid state %d\n", __func__, priv->state);
1586 return -EINVAL;
1587 }
1588 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1589 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1590 reg = ((u32)data[0] << 8) | (u32)data[1];
1591 if (reg == 0) {
1592 dev_dbg(&priv->i2c->dev,
1593 "%s(): reg value out of range\n", __func__);
1594 return 0;
1595 }
1596 if (reg > 4996)
1597 reg = 4996;
1598 *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1599 return 0;
1600}
1601
Mauro Carvalho Chehabc8946c82015-08-11 15:08:47 -0300[diff] [blame]1602static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1603{
1604 u32 reg;
1605 u8 data[2];
1606
1607 *snr = 0;
1608 if (priv->state != STATE_ACTIVE_TC) {
1609 dev_dbg(&priv->i2c->dev,
1610 "%s(): invalid state %d\n", __func__, priv->state);
1611 return -EINVAL;
1612 }
1613 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1614 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1615 reg = ((u32)data[0] << 8) | (u32)data[1];
1616 if (reg == 0) {
1617 dev_dbg(&priv->i2c->dev,
1618 "%s(): reg value out of range\n", __func__);
1619 return 0;
1620 }
1621 if (reg > 10876)
1622 reg = 10876;
1623 *snr = 10000 * ((intlog10(reg) -
1624 intlog10(12600 - reg)) >> 24) + 32000;
1625 return 0;
1626}
1627
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1628static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1629{
1630 u32 reg;
1631 u8 data[2];
1632
1633 *snr = 0;
1634 if (priv->state != STATE_ACTIVE_TC) {
1635 dev_dbg(&priv->i2c->dev,
1636 "%s(): invalid state %d\n", __func__,
1637 priv->state);
1638 return -EINVAL;
1639 }
1640
1641 /* Freeze all registers */
1642 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1643
1644
1645 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1646 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1647 reg = ((u32)data[0] << 8) | (u32)data[1];
1648 if (reg == 0) {
1649 dev_dbg(&priv->i2c->dev,
1650 "%s(): reg value out of range\n", __func__);
1651 return 0;
1652 }
1653 if (reg > 4996)
1654 reg = 4996;
1655 *snr = 100 * intlog10(reg) - 9031;
1656 return 0;
1657}
1658
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1659static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1660 u8 delsys)
1661{
1662 u8 data[2];
1663
1664 cxd2841er_write_reg(
1665 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1666 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
Abylay Ospanc5ea46d2016-04-02 23:31:50 -0300[diff] [blame]1667 dev_dbg(&priv->i2c->dev,
1668 "%s(): AGC value=%u\n",
1669 __func__, (((u16)data[0] & 0x0F) << 8) |
1670 (u16)(data[1] & 0xFF));
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1671 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1672}
1673
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1674static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1675 u8 delsys)
1676{
1677 u8 data[2];
1678
1679 cxd2841er_write_reg(
1680 priv, I2C_SLVT, 0x00, 0x60);
1681 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1682
1683 dev_dbg(&priv->i2c->dev,
1684 "%s(): AGC value=%u\n",
1685 __func__, (((u16)data[0] & 0x0F) << 8) |
1686 (u16)(data[1] & 0xFF));
1687 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1688}
1689
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1690static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1691{
1692 u8 data[2];
1693
1694 /* Set SLV-T Bank : 0xA0 */
1695 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1696 /*
1697 * slave Bank Addr Bit Signal name
1698 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1699 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1700 */
1701 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1702 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1703}
1704
1705static int cxd2841er_read_ber(struct dvb_frontend *fe, u32 *ber)
1706{
1707 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1708 struct cxd2841er_priv *priv = fe->demodulator_priv;
1709
1710 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1711 *ber = 0;
1712 switch (p->delivery_system) {
1713 case SYS_DVBS:
1714 *ber = cxd2841er_mon_read_ber_s(priv);
1715 break;
1716 case SYS_DVBS2:
1717 *ber = cxd2841er_mon_read_ber_s2(priv);
1718 break;
1719 case SYS_DVBT:
1720 return cxd2841er_read_ber_t(priv, ber);
1721 case SYS_DVBT2:
1722 return cxd2841er_read_ber_t2(priv, ber);
1723 default:
1724 *ber = 0;
1725 break;
1726 }
1727 return 0;
1728}
1729
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame^]1730static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1731{
1732 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1733 struct cxd2841er_priv *priv = fe->demodulator_priv;
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame^]1734 u32 strength;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1735
1736 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1737 switch (p->delivery_system) {
1738 case SYS_DVBT:
1739 case SYS_DVBT2:
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame^]1740 strength = cxd2841er_read_agc_gain_t_t2(priv,
1741 p->delivery_system);
1742 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1743 /* Formula was empirically determinated @ 410 MHz */
1744 p->strength.stat[0].uvalue = ((s32)strength) * 366 / 100 - 89520;
1745 break; /* Code moved out of the function */
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1746 case SYS_ISDBT:
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame^]1747 strength = 65535 - cxd2841er_read_agc_gain_i(
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1748 priv, p->delivery_system);
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame^]1749 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1750 p->strength.stat[0].uvalue = strength;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1751 break;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1752 case SYS_DVBS:
1753 case SYS_DVBS2:
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame^]1754 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1755 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1756 p->strength.stat[0].uvalue = strength;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1757 break;
1758 default:
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame^]1759 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1760 p->strength.stat[0].uvalue = 0;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1761 break;
1762 }
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1763}
1764
1765static int cxd2841er_read_snr(struct dvb_frontend *fe, u16 *snr)
1766{
1767 u32 tmp = 0;
1768 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1769 struct cxd2841er_priv *priv = fe->demodulator_priv;
1770
1771 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1772 switch (p->delivery_system) {
1773 case SYS_DVBT:
1774 cxd2841er_read_snr_t(priv, &tmp);
1775 break;
1776 case SYS_DVBT2:
1777 cxd2841er_read_snr_t2(priv, &tmp);
1778 break;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1779 case SYS_ISDBT:
1780 cxd2841er_read_snr_i(priv, &tmp);
1781 break;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1782 case SYS_DVBS:
1783 case SYS_DVBS2:
1784 tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system);
1785 break;
1786 default:
1787 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1788 __func__, p->delivery_system);
1789 break;
1790 }
1791 *snr = tmp & 0xffff;
1792 return 0;
1793}
1794
1795static int cxd2841er_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1796{
1797 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1798 struct cxd2841er_priv *priv = fe->demodulator_priv;
1799
1800 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1801 switch (p->delivery_system) {
1802 case SYS_DVBT:
1803 cxd2841er_read_packet_errors_t(priv, ucblocks);
1804 break;
1805 case SYS_DVBT2:
1806 cxd2841er_read_packet_errors_t2(priv, ucblocks);
1807 break;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1808 case SYS_ISDBT:
1809 cxd2841er_read_packet_errors_i(priv, ucblocks);
1810 break;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1811 default:
1812 *ucblocks = 0;
1813 break;
1814 }
1815 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1816 return 0;
1817}
1818
1819static int cxd2841er_dvbt2_set_profile(
1820 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
1821{
1822 u8 tune_mode;
1823 u8 seq_not2d_time;
1824
1825 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1826 switch (profile) {
1827 case DVBT2_PROFILE_BASE:
1828 tune_mode = 0x01;
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1829 /* Set early unlock time */
1830 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1831 break;
1832 case DVBT2_PROFILE_LITE:
1833 tune_mode = 0x05;
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1834 /* Set early unlock time */
1835 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1836 break;
1837 case DVBT2_PROFILE_ANY:
1838 tune_mode = 0x00;
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1839 /* Set early unlock time */
1840 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1841 break;
1842 default:
1843 return -EINVAL;
1844 }
1845 /* Set SLV-T Bank : 0x2E */
1846 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
1847 /* Set profile and tune mode */
1848 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
1849 /* Set SLV-T Bank : 0x2B */
1850 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1851 /* Set early unlock detection time */
1852 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
1853 return 0;
1854}
1855
1856static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
1857 u8 is_auto, u8 plp_id)
1858{
1859 if (is_auto) {
1860 dev_dbg(&priv->i2c->dev,
1861 "%s() using auto PLP selection\n", __func__);
1862 } else {
1863 dev_dbg(&priv->i2c->dev,
1864 "%s() using manual PLP selection, ID %d\n",
1865 __func__, plp_id);
1866 }
1867 /* Set SLV-T Bank : 0x23 */
1868 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
1869 if (!is_auto) {
1870 /* Manual PLP selection mode. Set the data PLP Id. */
1871 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
1872 }
1873 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1874 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
1875 return 0;
1876}
1877
1878static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
1879 u32 bandwidth)
1880{
1881 u32 iffreq;
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1882 u8 data[MAX_WRITE_REGSIZE];
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1883
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1884 const uint8_t nominalRate8bw[3][5] = {
1885 /* TRCG Nominal Rate [37:0] */
1886 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1887 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1888 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
1889 };
1890
1891 const uint8_t nominalRate7bw[3][5] = {
1892 /* TRCG Nominal Rate [37:0] */
1893 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1894 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1895 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
1896 };
1897
1898 const uint8_t nominalRate6bw[3][5] = {
1899 /* TRCG Nominal Rate [37:0] */
1900 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
1901 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1902 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
1903 };
1904
1905 const uint8_t nominalRate5bw[3][5] = {
1906 /* TRCG Nominal Rate [37:0] */
1907 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
1908 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
1909 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
1910 };
1911
1912 const uint8_t nominalRate17bw[3][5] = {
1913 /* TRCG Nominal Rate [37:0] */
1914 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
1915 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
1916 {0x58, 0xE2, 0xAF, 0xE0, 0xBC} /* 41MHz XTal */
1917 };
1918
1919 const uint8_t itbCoef8bw[3][14] = {
1920 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
1921 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
1922 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
1923 0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
1924 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
1925 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
1926 };
1927
1928 const uint8_t itbCoef7bw[3][14] = {
1929 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
1930 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
1931 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
1932 0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
1933 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
1934 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
1935 };
1936
1937 const uint8_t itbCoef6bw[3][14] = {
1938 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1939 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1940 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
1941 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
1942 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1943 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
1944 };
1945
1946 const uint8_t itbCoef5bw[3][14] = {
1947 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1948 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1949 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
1950 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
1951 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1952 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
1953 };
1954
1955 const uint8_t itbCoef17bw[3][14] = {
1956 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
1957 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
1958 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
1959 0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal */
1960 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
1961 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99} /* 41MHz XTal */
1962 };
1963
1964 /* Set SLV-T Bank : 0x20 */
1965 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1966
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1967 switch (bandwidth) {
1968 case 8000000:
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1969 /* <Timing Recovery setting> */
1970 cxd2841er_write_regs(priv, I2C_SLVT,
1971 0x9F, nominalRate8bw[priv->xtal], 5);
1972
1973 /* Set SLV-T Bank : 0x27 */
1974 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
1975 cxd2841er_set_reg_bits(priv, I2C_SLVT,
1976 0x7a, 0x00, 0x0f);
1977
1978 /* Set SLV-T Bank : 0x10 */
1979 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1980
1981 /* Group delay equaliser settings for
1982 * ASCOT2D, ASCOT2E and ASCOT3 tuners
1983 */
1984 cxd2841er_write_regs(priv, I2C_SLVT,
1985 0xA6, itbCoef8bw[priv->xtal], 14);
1986 /* <IF freq setting> */
1987 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
1988 data[0] = (u8) ((iffreq >> 16) & 0xff);
1989 data[1] = (u8)((iffreq >> 8) & 0xff);
1990 data[2] = (u8)(iffreq & 0xff);
1991 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
1992 /* System bandwidth setting */
1993 cxd2841er_set_reg_bits(
1994 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1995 break;
1996 case 7000000:
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1997 /* <Timing Recovery setting> */
1998 cxd2841er_write_regs(priv, I2C_SLVT,
1999 0x9F, nominalRate7bw[priv->xtal], 5);
2000
2001 /* Set SLV-T Bank : 0x27 */
2002 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2003 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2004 0x7a, 0x00, 0x0f);
2005
2006 /* Set SLV-T Bank : 0x10 */
2007 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2008
2009 /* Group delay equaliser settings for
2010 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2011 */
2012 cxd2841er_write_regs(priv, I2C_SLVT,
2013 0xA6, itbCoef7bw[priv->xtal], 14);
2014 /* <IF freq setting> */
2015 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2016 data[0] = (u8) ((iffreq >> 16) & 0xff);
2017 data[1] = (u8)((iffreq >> 8) & 0xff);
2018 data[2] = (u8)(iffreq & 0xff);
2019 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2020 /* System bandwidth setting */
2021 cxd2841er_set_reg_bits(
2022 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2023 break;
2024 case 6000000:
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2025 /* <Timing Recovery setting> */
2026 cxd2841er_write_regs(priv, I2C_SLVT,
2027 0x9F, nominalRate6bw[priv->xtal], 5);
2028
2029 /* Set SLV-T Bank : 0x27 */
2030 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2031 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2032 0x7a, 0x00, 0x0f);
2033
2034 /* Set SLV-T Bank : 0x10 */
2035 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2036
2037 /* Group delay equaliser settings for
2038 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2039 */
2040 cxd2841er_write_regs(priv, I2C_SLVT,
2041 0xA6, itbCoef6bw[priv->xtal], 14);
2042 /* <IF freq setting> */
2043 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2044 data[0] = (u8) ((iffreq >> 16) & 0xff);
2045 data[1] = (u8)((iffreq >> 8) & 0xff);
2046 data[2] = (u8)(iffreq & 0xff);
2047 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2048 /* System bandwidth setting */
2049 cxd2841er_set_reg_bits(
2050 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2051 break;
2052 case 5000000:
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2053 /* <Timing Recovery setting> */
2054 cxd2841er_write_regs(priv, I2C_SLVT,
2055 0x9F, nominalRate5bw[priv->xtal], 5);
2056
2057 /* Set SLV-T Bank : 0x27 */
2058 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2059 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2060 0x7a, 0x00, 0x0f);
2061
2062 /* Set SLV-T Bank : 0x10 */
2063 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2064
2065 /* Group delay equaliser settings for
2066 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2067 */
2068 cxd2841er_write_regs(priv, I2C_SLVT,
2069 0xA6, itbCoef5bw[priv->xtal], 14);
2070 /* <IF freq setting> */
2071 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2072 data[0] = (u8) ((iffreq >> 16) & 0xff);
2073 data[1] = (u8)((iffreq >> 8) & 0xff);
2074 data[2] = (u8)(iffreq & 0xff);
2075 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2076 /* System bandwidth setting */
2077 cxd2841er_set_reg_bits(
2078 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2079 break;
2080 case 1712000:
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2081 /* <Timing Recovery setting> */
2082 cxd2841er_write_regs(priv, I2C_SLVT,
2083 0x9F, nominalRate17bw[priv->xtal], 5);
2084
2085 /* Set SLV-T Bank : 0x27 */
2086 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2087 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2088 0x7a, 0x03, 0x0f);
2089
2090 /* Set SLV-T Bank : 0x10 */
2091 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2092
2093 /* Group delay equaliser settings for
2094 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2095 */
2096 cxd2841er_write_regs(priv, I2C_SLVT,
2097 0xA6, itbCoef17bw[priv->xtal], 14);
2098 /* <IF freq setting> */
2099 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.50);
2100 data[0] = (u8) ((iffreq >> 16) & 0xff);
2101 data[1] = (u8)((iffreq >> 8) & 0xff);
2102 data[2] = (u8)(iffreq & 0xff);
2103 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2104 /* System bandwidth setting */
2105 cxd2841er_set_reg_bits(
2106 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2107 break;
2108 default:
2109 return -EINVAL;
2110 }
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2111 return 0;
2112}
2113
2114static int cxd2841er_sleep_tc_to_active_t_band(
2115 struct cxd2841er_priv *priv, u32 bandwidth)
2116{
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2117 u8 data[MAX_WRITE_REGSIZE];
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2118 u32 iffreq;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2119 u8 nominalRate8bw[3][5] = {
2120 /* TRCG Nominal Rate [37:0] */
2121 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2122 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2123 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
2124 };
2125 u8 nominalRate7bw[3][5] = {
2126 /* TRCG Nominal Rate [37:0] */
2127 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2128 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2129 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
2130 };
2131 u8 nominalRate6bw[3][5] = {
2132 /* TRCG Nominal Rate [37:0] */
2133 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2134 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2135 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
2136 };
2137 u8 nominalRate5bw[3][5] = {
2138 /* TRCG Nominal Rate [37:0] */
2139 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2140 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2141 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
2142 };
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2143
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2144 u8 itbCoef8bw[3][14] = {
2145 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2146 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2147 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2148 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
2149 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2150 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
2151 };
2152 u8 itbCoef7bw[3][14] = {
2153 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2154 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2155 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2156 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
2157 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2158 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
2159 };
2160 u8 itbCoef6bw[3][14] = {
2161 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2162 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2163 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2164 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2165 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2166 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2167 };
2168 u8 itbCoef5bw[3][14] = {
2169 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2170 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2171 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2172 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2173 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2174 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2175 };
2176
2177 /* Set SLV-T Bank : 0x13 */
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2178 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2179 /* Echo performance optimization setting */
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2180 data[0] = 0x01;
2181 data[1] = 0x14;
2182 cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2183
2184 /* Set SLV-T Bank : 0x10 */
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2185 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2186
2187 switch (bandwidth) {
2188 case 8000000:
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2189 /* <Timing Recovery setting> */
2190 cxd2841er_write_regs(priv, I2C_SLVT,
2191 0x9F, nominalRate8bw[priv->xtal], 5);
2192 /* Group delay equaliser settings for
2193 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2194 */
2195 cxd2841er_write_regs(priv, I2C_SLVT,
2196 0xA6, itbCoef8bw[priv->xtal], 14);
2197 /* <IF freq setting> */
2198 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2199 data[0] = (u8) ((iffreq >> 16) & 0xff);
2200 data[1] = (u8)((iffreq >> 8) & 0xff);
2201 data[2] = (u8)(iffreq & 0xff);
2202 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2203 /* System bandwidth setting */
2204 cxd2841er_set_reg_bits(
2205 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2206
2207 /* Demod core latency setting */
2208 if (priv->xtal == SONY_XTAL_24000) {
2209 data[0] = 0x15;
2210 data[1] = 0x28;
2211 } else {
2212 data[0] = 0x01;
2213 data[1] = 0xE0;
2214 }
2215 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2216
2217 /* Notch filter setting */
2218 data[0] = 0x01;
2219 data[1] = 0x02;
2220 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2221 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2222 break;
2223 case 7000000:
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2224 /* <Timing Recovery setting> */
2225 cxd2841er_write_regs(priv, I2C_SLVT,
2226 0x9F, nominalRate7bw[priv->xtal], 5);
2227 /* Group delay equaliser settings for
2228 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2229 */
2230 cxd2841er_write_regs(priv, I2C_SLVT,
2231 0xA6, itbCoef7bw[priv->xtal], 14);
2232 /* <IF freq setting> */
2233 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2234 data[0] = (u8) ((iffreq >> 16) & 0xff);
2235 data[1] = (u8)((iffreq >> 8) & 0xff);
2236 data[2] = (u8)(iffreq & 0xff);
2237 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2238 /* System bandwidth setting */
2239 cxd2841er_set_reg_bits(
2240 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2241
2242 /* Demod core latency setting */
2243 if (priv->xtal == SONY_XTAL_24000) {
2244 data[0] = 0x1F;
2245 data[1] = 0xF8;
2246 } else {
2247 data[0] = 0x12;
2248 data[1] = 0xF8;
2249 }
2250 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2251
2252 /* Notch filter setting */
2253 data[0] = 0x00;
2254 data[1] = 0x03;
2255 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2256 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2257 break;
2258 case 6000000:
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2259 /* <Timing Recovery setting> */
2260 cxd2841er_write_regs(priv, I2C_SLVT,
2261 0x9F, nominalRate6bw[priv->xtal], 5);
2262 /* Group delay equaliser settings for
2263 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2264 */
2265 cxd2841er_write_regs(priv, I2C_SLVT,
2266 0xA6, itbCoef6bw[priv->xtal], 14);
2267 /* <IF freq setting> */
2268 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2269 data[0] = (u8) ((iffreq >> 16) & 0xff);
2270 data[1] = (u8)((iffreq >> 8) & 0xff);
2271 data[2] = (u8)(iffreq & 0xff);
2272 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2273 /* System bandwidth setting */
2274 cxd2841er_set_reg_bits(
2275 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2276
2277 /* Demod core latency setting */
2278 if (priv->xtal == SONY_XTAL_24000) {
2279 data[0] = 0x25;
2280 data[1] = 0x4C;
2281 } else {
2282 data[0] = 0x1F;
2283 data[1] = 0xDC;
2284 }
2285 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2286
2287 /* Notch filter setting */
2288 data[0] = 0x00;
2289 data[1] = 0x03;
2290 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2291 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2292 break;
2293 case 5000000:
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2294 /* <Timing Recovery setting> */
2295 cxd2841er_write_regs(priv, I2C_SLVT,
2296 0x9F, nominalRate5bw[priv->xtal], 5);
2297 /* Group delay equaliser settings for
2298 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2299 */
2300 cxd2841er_write_regs(priv, I2C_SLVT,
2301 0xA6, itbCoef5bw[priv->xtal], 14);
2302 /* <IF freq setting> */
2303 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2304 data[0] = (u8) ((iffreq >> 16) & 0xff);
2305 data[1] = (u8)((iffreq >> 8) & 0xff);
2306 data[2] = (u8)(iffreq & 0xff);
2307 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2308 /* System bandwidth setting */
2309 cxd2841er_set_reg_bits(
2310 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2311
2312 /* Demod core latency setting */
2313 if (priv->xtal == SONY_XTAL_24000) {
2314 data[0] = 0x2C;
2315 data[1] = 0xC2;
2316 } else {
2317 data[0] = 0x26;
2318 data[1] = 0x3C;
2319 }
2320 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2321
2322 /* Notch filter setting */
2323 data[0] = 0x00;
2324 data[1] = 0x03;
2325 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2326 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2327 break;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2328 }
2329
2330 return 0;
2331}
2332
2333static int cxd2841er_sleep_tc_to_active_i_band(
2334 struct cxd2841er_priv *priv, u32 bandwidth)
2335{
2336 u32 iffreq;
2337 u8 data[3];
2338
2339 /* TRCG Nominal Rate */
2340 u8 nominalRate8bw[3][5] = {
2341 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2342 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2343 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2344 };
2345
2346 u8 nominalRate7bw[3][5] = {
2347 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2348 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2349 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2350 };
2351
2352 u8 nominalRate6bw[3][5] = {
2353 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2354 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2355 {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
2356 };
2357
2358 u8 itbCoef8bw[3][14] = {
2359 {0x00}, /* 20.5MHz XTal */
2360 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2361 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2362 {0x0}, /* 41MHz XTal */
2363 };
2364
2365 u8 itbCoef7bw[3][14] = {
2366 {0x00}, /* 20.5MHz XTal */
2367 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2368 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2369 {0x00}, /* 41MHz XTal */
2370 };
2371
2372 u8 itbCoef6bw[3][14] = {
2373 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2374 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2375 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2376 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
2377 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2378 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
2379 };
2380
2381 dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2382 /* Set SLV-T Bank : 0x10 */
2383 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2384
2385 /* 20.5/41MHz Xtal support is not available
2386 * on ISDB-T 7MHzBW and 8MHzBW
2387 */
2388 if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2389 dev_err(&priv->i2c->dev,
2390 "%s(): bandwidth %d supported only for 24MHz xtal\n",
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2391 __func__, bandwidth);
2392 return -EINVAL;
2393 }
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2394
2395 switch (bandwidth) {
2396 case 8000000:
2397 /* TRCG Nominal Rate */
2398 cxd2841er_write_regs(priv, I2C_SLVT,
2399 0x9F, nominalRate8bw[priv->xtal], 5);
2400 /* Group delay equaliser settings for ASCOT tuners optimized */
2401 cxd2841er_write_regs(priv, I2C_SLVT,
2402 0xA6, itbCoef8bw[priv->xtal], 14);
2403
2404 /* IF freq setting */
2405 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75);
2406 data[0] = (u8) ((iffreq >> 16) & 0xff);
2407 data[1] = (u8)((iffreq >> 8) & 0xff);
2408 data[2] = (u8)(iffreq & 0xff);
2409 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2410
2411 /* System bandwidth setting */
2412 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2413
2414 /* Demod core latency setting */
2415 data[0] = 0x13;
2416 data[1] = 0xFC;
2417 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2418
2419 /* Acquisition optimization setting */
2420 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2421 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2422 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2423 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2424 break;
2425 case 7000000:
2426 /* TRCG Nominal Rate */
2427 cxd2841er_write_regs(priv, I2C_SLVT,
2428 0x9F, nominalRate7bw[priv->xtal], 5);
2429 /* Group delay equaliser settings for ASCOT tuners optimized */
2430 cxd2841er_write_regs(priv, I2C_SLVT,
2431 0xA6, itbCoef7bw[priv->xtal], 14);
2432
2433 /* IF freq setting */
2434 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15);
2435 data[0] = (u8) ((iffreq >> 16) & 0xff);
2436 data[1] = (u8)((iffreq >> 8) & 0xff);
2437 data[2] = (u8)(iffreq & 0xff);
2438 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2439
2440 /* System bandwidth setting */
2441 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2442
2443 /* Demod core latency setting */
2444 data[0] = 0x1A;
2445 data[1] = 0xFA;
2446 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2447
2448 /* Acquisition optimization setting */
2449 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2450 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2451 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2452 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2453 break;
2454 case 6000000:
2455 /* TRCG Nominal Rate */
2456 cxd2841er_write_regs(priv, I2C_SLVT,
2457 0x9F, nominalRate6bw[priv->xtal], 5);
2458 /* Group delay equaliser settings for ASCOT tuners optimized */
2459 cxd2841er_write_regs(priv, I2C_SLVT,
2460 0xA6, itbCoef6bw[priv->xtal], 14);
2461
2462 /* IF freq setting */
2463 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55);
2464 data[0] = (u8) ((iffreq >> 16) & 0xff);
2465 data[1] = (u8)((iffreq >> 8) & 0xff);
2466 data[2] = (u8)(iffreq & 0xff);
2467 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2468
2469 /* System bandwidth setting */
2470 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2471
2472 /* Demod core latency setting */
2473 if (priv->xtal == SONY_XTAL_24000) {
2474 data[0] = 0x1F;
2475 data[1] = 0x79;
2476 } else {
2477 data[0] = 0x1A;
2478 data[1] = 0xE2;
2479 }
2480 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2481
2482 /* Acquisition optimization setting */
2483 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2484 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2485 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2486 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2487 break;
2488 default:
2489 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2490 __func__, bandwidth);
2491 return -EINVAL;
2492 }
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2493 return 0;
2494}
2495
2496static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2497 u32 bandwidth)
2498{
2499 u8 bw7_8mhz_b10_a6[] = {
2500 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2501 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2502 u8 bw6mhz_b10_a6[] = {
2503 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2504 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2505 u8 b10_b6[3];
2506 u32 iffreq;
2507
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]2508 dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2509 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2510 switch (bandwidth) {
2511 case 8000000:
2512 case 7000000:
2513 cxd2841er_write_regs(
2514 priv, I2C_SLVT, 0xa6,
2515 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2516 iffreq = MAKE_IFFREQ_CONFIG(4.9);
2517 break;
2518 case 6000000:
2519 cxd2841er_write_regs(
2520 priv, I2C_SLVT, 0xa6,
2521 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2522 iffreq = MAKE_IFFREQ_CONFIG(3.7);
2523 break;
2524 default:
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]2525 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2526 __func__, bandwidth);
2527 return -EINVAL;
2528 }
2529 /* <IF freq setting> */
2530 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2531 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2532 b10_b6[2] = (u8)(iffreq & 0xff);
2533 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2534 /* Set SLV-T Bank : 0x11 */
2535 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2536 switch (bandwidth) {
2537 case 8000000:
2538 case 7000000:
2539 cxd2841er_set_reg_bits(
2540 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2541 break;
2542 case 6000000:
2543 cxd2841er_set_reg_bits(
2544 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2545 break;
2546 }
2547 /* Set SLV-T Bank : 0x40 */
2548 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2549 switch (bandwidth) {
2550 case 8000000:
2551 cxd2841er_set_reg_bits(
2552 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2553 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
2554 break;
2555 case 7000000:
2556 cxd2841er_set_reg_bits(
2557 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2558 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
2559 break;
2560 case 6000000:
2561 cxd2841er_set_reg_bits(
2562 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2563 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
2564 break;
2565 }
2566 return 0;
2567}
2568
2569static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2570 u32 bandwidth)
2571{
2572 u8 data[2] = { 0x09, 0x54 };
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2573 u8 data24m[3] = {0xDC, 0x6C, 0x00};
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2574
2575 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2576 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2577 /* Set SLV-X Bank : 0x00 */
2578 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2579 /* Set demod mode */
2580 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2581 /* Set SLV-T Bank : 0x00 */
2582 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2583 /* Enable demod clock */
2584 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2585 /* Disable RF level monitor */
2586 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2587 /* Enable ADC clock */
2588 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2589 /* Enable ADC 1 */
2590 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2591 /* Enable ADC 2 & 3 */
2592 if (priv->xtal == SONY_XTAL_41000) {
2593 data[0] = 0x0A;
2594 data[1] = 0xD4;
2595 }
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2596 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2597 /* Enable ADC 4 */
2598 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2599 /* Set SLV-T Bank : 0x10 */
2600 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2601 /* IFAGC gain settings */
2602 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2603 /* Set SLV-T Bank : 0x11 */
2604 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2605 /* BBAGC TARGET level setting */
2606 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2607 /* Set SLV-T Bank : 0x10 */
2608 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2609 /* ASCOT setting ON */
2610 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2611 /* Set SLV-T Bank : 0x18 */
2612 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2613 /* Pre-RS BER moniter setting */
2614 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2615 /* FEC Auto Recovery setting */
2616 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2617 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2618 /* Set SLV-T Bank : 0x00 */
2619 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2620 /* TSIF setting */
2621 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2622 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2623
2624 if (priv->xtal == SONY_XTAL_24000) {
2625 /* Set SLV-T Bank : 0x10 */
2626 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2627 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2628 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2629 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2630 }
2631
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2632 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2633 /* Set SLV-T Bank : 0x00 */
2634 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2635 /* Disable HiZ Setting 1 */
2636 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2637 /* Disable HiZ Setting 2 */
2638 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2639 priv->state = STATE_ACTIVE_TC;
2640 return 0;
2641}
2642
2643static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2644 u32 bandwidth)
2645{
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2646 u8 data[MAX_WRITE_REGSIZE];
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2647
2648 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2649 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2650 /* Set SLV-X Bank : 0x00 */
2651 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2652 /* Set demod mode */
2653 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2654 /* Set SLV-T Bank : 0x00 */
2655 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2656 /* Enable demod clock */
2657 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2658 /* Disable RF level monitor */
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2659 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2660 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2661 /* Enable ADC clock */
2662 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2663 /* Enable ADC 1 */
2664 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2665
2666 if (priv->xtal == SONY_XTAL_41000) {
2667 data[0] = 0x0A;
2668 data[1] = 0xD4;
2669 } else {
2670 data[0] = 0x09;
2671 data[1] = 0x54;
2672 }
2673
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2674 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2675 /* Enable ADC 4 */
2676 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2677 /* Set SLV-T Bank : 0x10 */
2678 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2679 /* IFAGC gain settings */
2680 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2681 /* Set SLV-T Bank : 0x11 */
2682 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2683 /* BBAGC TARGET level setting */
2684 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2685 /* Set SLV-T Bank : 0x10 */
2686 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2687 /* ASCOT setting ON */
2688 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2689 /* Set SLV-T Bank : 0x20 */
2690 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2691 /* Acquisition optimization setting */
2692 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2693 /* Set SLV-T Bank : 0x2b */
2694 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2695 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2696 /* Set SLV-T Bank : 0x23 */
2697 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2698 /* L1 Control setting */
2699 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2700 /* Set SLV-T Bank : 0x00 */
2701 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2702 /* TSIF setting */
2703 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2704 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2705 /* DVB-T2 initial setting */
2706 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2707 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2708 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2709 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2710 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2711 /* Set SLV-T Bank : 0x2a */
2712 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2713 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2714 /* Set SLV-T Bank : 0x2b */
2715 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2716 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2717
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2718 /* 24MHz Xtal setting */
2719 if (priv->xtal == SONY_XTAL_24000) {
2720 /* Set SLV-T Bank : 0x11 */
2721 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2722 data[0] = 0xEB;
2723 data[1] = 0x03;
2724 data[2] = 0x3B;
2725 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
2726
2727 /* Set SLV-T Bank : 0x20 */
2728 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2729 data[0] = 0x5E;
2730 data[1] = 0x5E;
2731 data[2] = 0x47;
2732 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
2733
2734 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
2735
2736 data[0] = 0x3F;
2737 data[1] = 0xFF;
2738 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2739
2740 /* Set SLV-T Bank : 0x24 */
2741 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
2742 data[0] = 0x0B;
2743 data[1] = 0x72;
2744 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
2745
2746 data[0] = 0x93;
2747 data[1] = 0xF3;
2748 data[2] = 0x00;
2749 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
2750
2751 data[0] = 0x05;
2752 data[1] = 0xB8;
2753 data[2] = 0xD8;
2754 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
2755
2756 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
2757
2758 /* Set SLV-T Bank : 0x25 */
2759 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
2760 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
2761
2762 /* Set SLV-T Bank : 0x27 */
2763 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2764 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
2765
2766 /* Set SLV-T Bank : 0x2B */
2767 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
2768 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
2769 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
2770
2771 /* Set SLV-T Bank : 0x2D */
2772 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
2773 data[0] = 0x89;
2774 data[1] = 0x89;
2775 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
2776
2777 /* Set SLV-T Bank : 0x5E */
2778 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
2779 data[0] = 0x24;
2780 data[1] = 0x95;
2781 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
2782 }
2783
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2784 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2785
2786 /* Set SLV-T Bank : 0x00 */
2787 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2788 /* Disable HiZ Setting 1 */
2789 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2790 /* Disable HiZ Setting 2 */
2791 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2792 priv->state = STATE_ACTIVE_TC;
2793 return 0;
2794}
2795
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2796/* ISDB-Tb part */
2797static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
2798 u32 bandwidth)
2799{
2800 u8 data[2] = { 0x09, 0x54 };
2801 u8 data24m[2] = {0x60, 0x00};
2802 u8 data24m2[3] = {0xB7, 0x1B, 0x00};
2803
2804 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2805 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2806 /* Set SLV-X Bank : 0x00 */
2807 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2808 /* Set demod mode */
2809 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
2810 /* Set SLV-T Bank : 0x00 */
2811 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2812 /* Enable demod clock */
2813 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2814 /* Enable RF level monitor */
2815 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
2816 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
2817 /* Enable ADC clock */
2818 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2819 /* Enable ADC 1 */
2820 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2821 /* xtal freq 20.5MHz or 24M */
2822 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2823 /* Enable ADC 4 */
2824 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2825 /* ASCOT setting ON */
2826 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2827 /* FEC Auto Recovery setting */
2828 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2829 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
2830 /* ISDB-T initial setting */
2831 /* Set SLV-T Bank : 0x00 */
2832 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2833 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
2834 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
2835 /* Set SLV-T Bank : 0x10 */
2836 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2837 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
2838 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
2839 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
2840 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
2841 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
2842 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
2843 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
2844 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
2845 /* Set SLV-T Bank : 0x15 */
2846 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2847 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
2848 /* Set SLV-T Bank : 0x1E */
2849 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
2850 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
2851 /* Set SLV-T Bank : 0x63 */
2852 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
2853 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
2854
2855 /* for xtal 24MHz */
2856 /* Set SLV-T Bank : 0x10 */
2857 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2858 cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
2859 /* Set SLV-T Bank : 0x60 */
2860 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
2861 cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
2862
2863 cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
2864 /* Set SLV-T Bank : 0x00 */
2865 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2866 /* Disable HiZ Setting 1 */
2867 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2868 /* Disable HiZ Setting 2 */
2869 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2870 priv->state = STATE_ACTIVE_TC;
2871 return 0;
2872}
2873
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2874static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
2875 u32 bandwidth)
2876{
2877 u8 data[2] = { 0x09, 0x54 };
2878
2879 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2880 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
2881 /* Set SLV-X Bank : 0x00 */
2882 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2883 /* Set demod mode */
2884 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
2885 /* Set SLV-T Bank : 0x00 */
2886 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2887 /* Enable demod clock */
2888 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2889 /* Disable RF level monitor */
2890 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2891 /* Enable ADC clock */
2892 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2893 /* Enable ADC 1 */
2894 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2895 /* xtal freq 20.5MHz */
2896 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2897 /* Enable ADC 4 */
2898 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2899 /* Set SLV-T Bank : 0x10 */
2900 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2901 /* IFAGC gain settings */
2902 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
2903 /* Set SLV-T Bank : 0x11 */
2904 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2905 /* BBAGC TARGET level setting */
2906 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
2907 /* Set SLV-T Bank : 0x10 */
2908 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2909 /* ASCOT setting ON */
2910 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2911 /* Set SLV-T Bank : 0x40 */
2912 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2913 /* Demod setting */
2914 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
2915 /* Set SLV-T Bank : 0x00 */
2916 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2917 /* TSIF setting */
2918 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2919 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2920
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]2921 cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2922 /* Set SLV-T Bank : 0x00 */
2923 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2924 /* Disable HiZ Setting 1 */
2925 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2926 /* Disable HiZ Setting 2 */
2927 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2928 priv->state = STATE_ACTIVE_TC;
2929 return 0;
2930}
2931
Mauro Carvalho Chehab7e3e68b2016-02-04 12:58:30 -0200[diff] [blame]2932static int cxd2841er_get_frontend(struct dvb_frontend *fe,
2933 struct dtv_frontend_properties *p)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2934{
2935 enum fe_status status = 0;
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame^]2936 u16 snr = 0;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2937 u32 errors = 0, ber = 0;
2938 struct cxd2841er_priv *priv = fe->demodulator_priv;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2939
2940 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2941 if (priv->state == STATE_ACTIVE_S)
2942 cxd2841er_read_status_s(fe, &status);
2943 else if (priv->state == STATE_ACTIVE_TC)
2944 cxd2841er_read_status_tc(fe, &status);
2945
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame^]2946 cxd2841er_read_signal_strength(fe);
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]2947
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2948 if (status & FE_HAS_LOCK) {
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2949 cxd2841er_read_snr(fe, &snr);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2950 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2951 p->cnr.stat[0].svalue = snr;
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]2952
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2953 cxd2841er_read_ucblocks(fe, &errors);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2954 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2955 p->block_error.stat[0].uvalue = errors;
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]2956
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2957 cxd2841er_read_ber(fe, &ber);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2958 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
2959 p->post_bit_error.stat[0].uvalue = ber;
2960 } else {
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2961 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2962 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2963 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2964 }
2965 return 0;
2966}
2967
2968static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
2969{
2970 int ret = 0, i, timeout, carr_offset;
2971 enum fe_status status;
2972 struct cxd2841er_priv *priv = fe->demodulator_priv;
2973 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2974 u32 symbol_rate = p->symbol_rate/1000;
2975
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2976 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2977 __func__,
2978 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2979 p->frequency, symbol_rate, priv->xtal);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2980 switch (priv->state) {
2981 case STATE_SLEEP_S:
2982 ret = cxd2841er_sleep_s_to_active_s(
2983 priv, p->delivery_system, symbol_rate);
2984 break;
2985 case STATE_ACTIVE_S:
2986 ret = cxd2841er_retune_active(priv, p);
2987 break;
2988 default:
2989 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2990 __func__, priv->state);
2991 ret = -EINVAL;
2992 goto done;
2993 }
2994 if (ret) {
2995 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
2996 goto done;
2997 }
2998 if (fe->ops.i2c_gate_ctrl)
2999 fe->ops.i2c_gate_ctrl(fe, 1);
3000 if (fe->ops.tuner_ops.set_params)
3001 fe->ops.tuner_ops.set_params(fe);
3002 if (fe->ops.i2c_gate_ctrl)
3003 fe->ops.i2c_gate_ctrl(fe, 0);
3004 cxd2841er_tune_done(priv);
3005 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3006 for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
3007 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3008 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3009 cxd2841er_read_status_s(fe, &status);
3010 if (status & FE_HAS_LOCK)
3011 break;
3012 }
3013 if (status & FE_HAS_LOCK) {
3014 if (cxd2841er_get_carrier_offset_s_s2(
3015 priv, &carr_offset)) {
3016 ret = -EINVAL;
3017 goto done;
3018 }
3019 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3020 __func__, carr_offset);
3021 }
3022done:
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]3023 /* Reset stats */
3024 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3025 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3026 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3027 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3028
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3029 return ret;
3030}
3031
3032static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3033{
3034 int ret = 0, timeout;
3035 enum fe_status status;
3036 struct cxd2841er_priv *priv = fe->demodulator_priv;
3037 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3038
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3039 dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3040 __func__, p->delivery_system, p->bandwidth_hz);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3041 if (p->delivery_system == SYS_DVBT) {
3042 priv->system = SYS_DVBT;
3043 switch (priv->state) {
3044 case STATE_SLEEP_TC:
3045 ret = cxd2841er_sleep_tc_to_active_t(
3046 priv, p->bandwidth_hz);
3047 break;
3048 case STATE_ACTIVE_TC:
3049 ret = cxd2841er_retune_active(priv, p);
3050 break;
3051 default:
3052 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3053 __func__, priv->state);
3054 ret = -EINVAL;
3055 }
3056 } else if (p->delivery_system == SYS_DVBT2) {
3057 priv->system = SYS_DVBT2;
3058 cxd2841er_dvbt2_set_plp_config(priv,
3059 (int)(p->stream_id > 255), p->stream_id);
3060 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3061 switch (priv->state) {
3062 case STATE_SLEEP_TC:
3063 ret = cxd2841er_sleep_tc_to_active_t2(priv,
3064 p->bandwidth_hz);
3065 break;
3066 case STATE_ACTIVE_TC:
3067 ret = cxd2841er_retune_active(priv, p);
3068 break;
3069 default:
3070 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3071 __func__, priv->state);
3072 ret = -EINVAL;
3073 }
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]3074 } else if (p->delivery_system == SYS_ISDBT) {
3075 priv->system = SYS_ISDBT;
3076 switch (priv->state) {
3077 case STATE_SLEEP_TC:
3078 ret = cxd2841er_sleep_tc_to_active_i(
3079 priv, p->bandwidth_hz);
3080 break;
3081 case STATE_ACTIVE_TC:
3082 ret = cxd2841er_retune_active(priv, p);
3083 break;
3084 default:
3085 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3086 __func__, priv->state);
3087 ret = -EINVAL;
3088 }
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3089 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3090 p->delivery_system == SYS_DVBC_ANNEX_C) {
3091 priv->system = SYS_DVBC_ANNEX_A;
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3092 /* correct bandwidth */
3093 if (p->bandwidth_hz != 6000000 &&
3094 p->bandwidth_hz != 7000000 &&
3095 p->bandwidth_hz != 8000000) {
3096 p->bandwidth_hz = 8000000;
3097 dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3098 __func__, p->bandwidth_hz);
3099 }
3100
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3101 switch (priv->state) {
3102 case STATE_SLEEP_TC:
3103 ret = cxd2841er_sleep_tc_to_active_c(
3104 priv, p->bandwidth_hz);
3105 break;
3106 case STATE_ACTIVE_TC:
3107 ret = cxd2841er_retune_active(priv, p);
3108 break;
3109 default:
3110 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3111 __func__, priv->state);
3112 ret = -EINVAL;
3113 }
3114 } else {
3115 dev_dbg(&priv->i2c->dev,
3116 "%s(): invalid delivery system %d\n",
3117 __func__, p->delivery_system);
3118 ret = -EINVAL;
3119 }
3120 if (ret)
3121 goto done;
3122 if (fe->ops.i2c_gate_ctrl)
3123 fe->ops.i2c_gate_ctrl(fe, 1);
3124 if (fe->ops.tuner_ops.set_params)
3125 fe->ops.tuner_ops.set_params(fe);
3126 if (fe->ops.i2c_gate_ctrl)
3127 fe->ops.i2c_gate_ctrl(fe, 0);
3128 cxd2841er_tune_done(priv);
3129 timeout = 2500;
3130 while (timeout > 0) {
3131 ret = cxd2841er_read_status_tc(fe, &status);
3132 if (ret)
3133 goto done;
3134 if (status & FE_HAS_LOCK)
3135 break;
3136 msleep(20);
3137 timeout -= 20;
3138 }
3139 if (timeout < 0)
3140 dev_dbg(&priv->i2c->dev,
3141 "%s(): LOCK wait timeout\n", __func__);
3142done:
3143 return ret;
3144}
3145
3146static int cxd2841er_tune_s(struct dvb_frontend *fe,
3147 bool re_tune,
3148 unsigned int mode_flags,
3149 unsigned int *delay,
3150 enum fe_status *status)
3151{
3152 int ret, carrier_offset;
3153 struct cxd2841er_priv *priv = fe->demodulator_priv;
3154 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3155
3156 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3157 if (re_tune) {
3158 ret = cxd2841er_set_frontend_s(fe);
3159 if (ret)
3160 return ret;
3161 cxd2841er_read_status_s(fe, status);
3162 if (*status & FE_HAS_LOCK) {
3163 if (cxd2841er_get_carrier_offset_s_s2(
3164 priv, &carrier_offset))
3165 return -EINVAL;
3166 p->frequency += carrier_offset;
3167 ret = cxd2841er_set_frontend_s(fe);
3168 if (ret)
3169 return ret;
3170 }
3171 }
3172 *delay = HZ / 5;
3173 return cxd2841er_read_status_s(fe, status);
3174}
3175
3176static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3177 bool re_tune,
3178 unsigned int mode_flags,
3179 unsigned int *delay,
3180 enum fe_status *status)
3181{
3182 int ret, carrier_offset;
3183 struct cxd2841er_priv *priv = fe->demodulator_priv;
3184 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3185
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3186 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3187 re_tune, p->bandwidth_hz);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3188 if (re_tune) {
3189 ret = cxd2841er_set_frontend_tc(fe);
3190 if (ret)
3191 return ret;
3192 cxd2841er_read_status_tc(fe, status);
3193 if (*status & FE_HAS_LOCK) {
3194 switch (priv->system) {
Mauro Carvalho Chehab76344a3f2016-05-04 18:25:38 -0300[diff] [blame]3195 case SYS_ISDBT:
3196 ret = cxd2841er_get_carrier_offset_i(
3197 priv, p->bandwidth_hz,
3198 &carrier_offset);
3199 break;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3200 case SYS_DVBT:
Abylay Ospanc5ea46d2016-04-02 23:31:50 -0300[diff] [blame]3201 ret = cxd2841er_get_carrier_offset_t(
3202 priv, p->bandwidth_hz,
3203 &carrier_offset);
3204 break;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3205 case SYS_DVBT2:
3206 ret = cxd2841er_get_carrier_offset_t2(
3207 priv, p->bandwidth_hz,
3208 &carrier_offset);
3209 break;
3210 case SYS_DVBC_ANNEX_A:
3211 ret = cxd2841er_get_carrier_offset_c(
3212 priv, &carrier_offset);
3213 break;
3214 default:
3215 dev_dbg(&priv->i2c->dev,
3216 "%s(): invalid delivery system %d\n",
3217 __func__, priv->system);
3218 return -EINVAL;
3219 }
3220 if (ret)
3221 return ret;
3222 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3223 __func__, carrier_offset);
3224 p->frequency += carrier_offset;
3225 ret = cxd2841er_set_frontend_tc(fe);
3226 if (ret)
3227 return ret;
3228 }
3229 }
3230 *delay = HZ / 5;
3231 return cxd2841er_read_status_tc(fe, status);
3232}
3233
3234static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3235{
3236 struct cxd2841er_priv *priv = fe->demodulator_priv;
3237
3238 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3239 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3240 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3241 return 0;
3242}
3243
3244static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3245{
3246 struct cxd2841er_priv *priv = fe->demodulator_priv;
3247
3248 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3249 if (priv->state == STATE_ACTIVE_TC) {
3250 switch (priv->system) {
3251 case SYS_DVBT:
3252 cxd2841er_active_t_to_sleep_tc(priv);
3253 break;
3254 case SYS_DVBT2:
3255 cxd2841er_active_t2_to_sleep_tc(priv);
3256 break;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]3257 case SYS_ISDBT:
3258 cxd2841er_active_i_to_sleep_tc(priv);
3259 break;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3260 case SYS_DVBC_ANNEX_A:
3261 cxd2841er_active_c_to_sleep_tc(priv);
3262 break;
3263 default:
3264 dev_warn(&priv->i2c->dev,
3265 "%s(): unknown delivery system %d\n",
3266 __func__, priv->system);
3267 }
3268 }
3269 if (priv->state != STATE_SLEEP_TC) {
3270 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3271 __func__, priv->state);
3272 return -EINVAL;
3273 }
3274 cxd2841er_sleep_tc_to_shutdown(priv);
3275 return 0;
3276}
3277
3278static int cxd2841er_send_burst(struct dvb_frontend *fe,
3279 enum fe_sec_mini_cmd burst)
3280{
3281 u8 data;
3282 struct cxd2841er_priv *priv = fe->demodulator_priv;
3283
3284 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3285 (burst == SEC_MINI_A ? "A" : "B"));
3286 if (priv->state != STATE_SLEEP_S &&
3287 priv->state != STATE_ACTIVE_S) {
3288 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3289 __func__, priv->state);
3290 return -EINVAL;
3291 }
3292 data = (burst == SEC_MINI_A ? 0 : 1);
3293 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3294 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3295 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3296 return 0;
3297}
3298
3299static int cxd2841er_set_tone(struct dvb_frontend *fe,
3300 enum fe_sec_tone_mode tone)
3301{
3302 u8 data;
3303 struct cxd2841er_priv *priv = fe->demodulator_priv;
3304
3305 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3306 (tone == SEC_TONE_ON ? "On" : "Off"));
3307 if (priv->state != STATE_SLEEP_S &&
3308 priv->state != STATE_ACTIVE_S) {
3309 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3310 __func__, priv->state);
3311 return -EINVAL;
3312 }
3313 data = (tone == SEC_TONE_ON ? 1 : 0);
3314 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3315 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3316 return 0;
3317}
3318
3319static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3320 struct dvb_diseqc_master_cmd *cmd)
3321{
3322 int i;
3323 u8 data[12];
3324 struct cxd2841er_priv *priv = fe->demodulator_priv;
3325
3326 if (priv->state != STATE_SLEEP_S &&
3327 priv->state != STATE_ACTIVE_S) {
3328 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3329 __func__, priv->state);
3330 return -EINVAL;
3331 }
3332 dev_dbg(&priv->i2c->dev,
3333 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3334 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3335 /* DiDEqC enable */
3336 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3337 /* cmd1 length & data */
3338 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3339 memset(data, 0, sizeof(data));
3340 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3341 data[i] = cmd->msg[i];
3342 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3343 /* repeat count for cmd1 */
3344 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3345 /* repeat count for cmd2: always 0 */
3346 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3347 /* start transmit */
3348 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3349 /* wait for 1 sec timeout */
3350 for (i = 0; i < 50; i++) {
3351 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3352 if (!data[0]) {
3353 dev_dbg(&priv->i2c->dev,
3354 "%s(): DiSEqC cmd has been sent\n", __func__);
3355 return 0;
3356 }
3357 msleep(20);
3358 }
3359 dev_dbg(&priv->i2c->dev,
3360 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3361 return -ETIMEDOUT;
3362}
3363
3364static void cxd2841er_release(struct dvb_frontend *fe)
3365{
3366 struct cxd2841er_priv *priv = fe->demodulator_priv;
3367
3368 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3369 kfree(priv);
3370}
3371
3372static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3373{
3374 struct cxd2841er_priv *priv = fe->demodulator_priv;
3375
3376 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3377 cxd2841er_set_reg_bits(
3378 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3379 return 0;
3380}
3381
3382static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3383{
3384 struct cxd2841er_priv *priv = fe->demodulator_priv;
3385
3386 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3387 return DVBFE_ALGO_HW;
3388}
3389
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]3390static void cxd2841er_init_stats(struct dvb_frontend *fe)
3391{
3392 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3393
3394 p->strength.len = 1;
3395 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3396 p->cnr.len = 1;
3397 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3398 p->block_error.len = 1;
3399 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3400 p->post_bit_error.len = 1;
3401 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3402}
3403
3404
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3405static int cxd2841er_init_s(struct dvb_frontend *fe)
3406{
3407 struct cxd2841er_priv *priv = fe->demodulator_priv;
3408
Abylay Ospan30ae3302016-04-05 15:02:37 -0300[diff] [blame]3409 /* sanity. force demod to SHUTDOWN state */
3410 if (priv->state == STATE_SLEEP_S) {
3411 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3412 __func__);
3413 cxd2841er_sleep_s_to_shutdown(priv);
3414 } else if (priv->state == STATE_ACTIVE_S) {
3415 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3416 __func__);
3417 cxd2841er_active_s_to_sleep_s(priv);
3418 cxd2841er_sleep_s_to_shutdown(priv);
3419 }
3420
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3421 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3422 cxd2841er_shutdown_to_sleep_s(priv);
3423 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3424 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3425 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]3426
3427 cxd2841er_init_stats(fe);
3428
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3429 return 0;
3430}
3431
3432static int cxd2841er_init_tc(struct dvb_frontend *fe)
3433{
3434 struct cxd2841er_priv *priv = fe->demodulator_priv;
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3435 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3436
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3437 dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3438 __func__, p->bandwidth_hz);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3439 cxd2841er_shutdown_to_sleep_tc(priv);
3440 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3441 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3442 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3443 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3444 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3445 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3446 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3447 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]3448
3449 cxd2841er_init_stats(fe);
3450
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3451 return 0;
3452}
3453
3454static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3455static struct dvb_frontend_ops cxd2841er_t_c_ops;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3456
3457static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3458 struct i2c_adapter *i2c,
3459 u8 system)
3460{
3461 u8 chip_id = 0;
3462 const char *type;
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3463 const char *name;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3464 struct cxd2841er_priv *priv = NULL;
3465
3466 /* allocate memory for the internal state */
3467 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3468 if (!priv)
3469 return NULL;
3470 priv->i2c = i2c;
3471 priv->config = cfg;
3472 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3473 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]3474 priv->xtal = cfg->xtal;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3475 priv->frontend.demodulator_priv = priv;
3476 dev_info(&priv->i2c->dev,
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3477 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3478 __func__, priv->i2c,
3479 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3480 chip_id = cxd2841er_chip_id(priv);
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3481 switch (chip_id) {
3482 case CXD2841ER_CHIP_ID:
3483 snprintf(cxd2841er_t_c_ops.info.name, 128,
3484 "Sony CXD2841ER DVB-T/T2/C demodulator");
3485 name = "CXD2841ER";
3486 break;
3487 case CXD2854ER_CHIP_ID:
3488 snprintf(cxd2841er_t_c_ops.info.name, 128,
3489 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3490 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3491 name = "CXD2854ER";
3492 break;
3493 default:
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3494 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3495 __func__, chip_id);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3496 priv->frontend.demodulator_priv = NULL;
3497 kfree(priv);
3498 return NULL;
3499 }
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3500
3501 /* create dvb_frontend */
3502 if (system == SYS_DVBS) {
3503 memcpy(&priv->frontend.ops,
3504 &cxd2841er_dvbs_s2_ops,
3505 sizeof(struct dvb_frontend_ops));
3506 type = "S/S2";
3507 } else {
3508 memcpy(&priv->frontend.ops,
3509 &cxd2841er_t_c_ops,
3510 sizeof(struct dvb_frontend_ops));
3511 type = "T/T2/C/ISDB-T";
3512 }
3513
3514 dev_info(&priv->i2c->dev,
3515 "%s(): attaching %s DVB-%s frontend\n",
3516 __func__, name, type);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3517 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3518 __func__, chip_id);
3519 return &priv->frontend;
3520}
3521
3522struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3523 struct i2c_adapter *i2c)
3524{
3525 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3526}
3527EXPORT_SYMBOL(cxd2841er_attach_s);
3528
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3529struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3530 struct i2c_adapter *i2c)
3531{
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3532 return cxd2841er_attach(cfg, i2c, 0);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3533}
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3534EXPORT_SYMBOL(cxd2841er_attach_t_c);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3535
3536static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3537 .delsys = { SYS_DVBS, SYS_DVBS2 },
3538 .info = {
3539 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
3540 .frequency_min = 500000,
3541 .frequency_max = 2500000,
3542 .frequency_stepsize = 0,
3543 .symbol_rate_min = 1000000,
3544 .symbol_rate_max = 45000000,
3545 .symbol_rate_tolerance = 500,
3546 .caps = FE_CAN_INVERSION_AUTO |
3547 FE_CAN_FEC_AUTO |
3548 FE_CAN_QPSK,
3549 },
3550 .init = cxd2841er_init_s,
3551 .sleep = cxd2841er_sleep_s,
3552 .release = cxd2841er_release,
3553 .set_frontend = cxd2841er_set_frontend_s,
3554 .get_frontend = cxd2841er_get_frontend,
3555 .read_status = cxd2841er_read_status_s,
3556 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3557 .get_frontend_algo = cxd2841er_get_algo,
3558 .set_tone = cxd2841er_set_tone,
3559 .diseqc_send_burst = cxd2841er_send_burst,
3560 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3561 .tune = cxd2841er_tune_s
3562};
3563
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3564static struct dvb_frontend_ops cxd2841er_t_c_ops = {
3565 .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3566 .info = {
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3567 .name = "", /* will set in attach function */
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3568 .caps = FE_CAN_FEC_1_2 |
3569 FE_CAN_FEC_2_3 |
3570 FE_CAN_FEC_3_4 |
3571 FE_CAN_FEC_5_6 |
3572 FE_CAN_FEC_7_8 |
3573 FE_CAN_FEC_AUTO |
3574 FE_CAN_QPSK |
3575 FE_CAN_QAM_16 |
3576 FE_CAN_QAM_32 |
3577 FE_CAN_QAM_64 |
3578 FE_CAN_QAM_128 |
3579 FE_CAN_QAM_256 |
3580 FE_CAN_QAM_AUTO |
3581 FE_CAN_TRANSMISSION_MODE_AUTO |
3582 FE_CAN_GUARD_INTERVAL_AUTO |
3583 FE_CAN_HIERARCHY_AUTO |
3584 FE_CAN_MUTE_TS |
3585 FE_CAN_2G_MODULATION,
3586 .frequency_min = 42000000,
3587 .frequency_max = 1002000000
3588 },
3589 .init = cxd2841er_init_tc,
3590 .sleep = cxd2841er_sleep_tc,
3591 .release = cxd2841er_release,
3592 .set_frontend = cxd2841er_set_frontend_tc,
3593 .get_frontend = cxd2841er_get_frontend,
3594 .read_status = cxd2841er_read_status_tc,
3595 .tune = cxd2841er_tune_tc,
3596 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3597 .get_frontend_algo = cxd2841er_get_algo
3598};
3599
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]3600MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3601MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3602MODULE_LICENSE("GPL");