Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 1 | /* |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 2 | * Synopsys Designware PCIe host controller driver |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
| 5 | * http://www.samsung.com |
| 6 | * |
| 7 | * Author: Jingoo Han <jg1.han@samsung.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 14 | #include <linux/irq.h> |
| 15 | #include <linux/irqdomain.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 16 | #include <linux/kernel.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 17 | #include <linux/module.h> |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 18 | #include <linux/msi.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 19 | #include <linux/of_address.h> |
Lucas Stach | 804f57b | 2014-03-05 14:25:51 +0100 | [diff] [blame] | 20 | #include <linux/of_pci.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 21 | #include <linux/pci.h> |
| 22 | #include <linux/pci_regs.h> |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 23 | #include <linux/platform_device.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 24 | #include <linux/types.h> |
| 25 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 26 | #include "pcie-designware.h" |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 27 | |
| 28 | /* Synopsis specific PCIE configuration registers */ |
| 29 | #define PCIE_PORT_LINK_CONTROL 0x710 |
| 30 | #define PORT_LINK_MODE_MASK (0x3f << 16) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 31 | #define PORT_LINK_MODE_1_LANES (0x1 << 16) |
| 32 | #define PORT_LINK_MODE_2_LANES (0x3 << 16) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 33 | #define PORT_LINK_MODE_4_LANES (0x7 << 16) |
Zhou Wang | 5b0f073 | 2015-05-13 14:44:34 +0800 | [diff] [blame^] | 34 | #define PORT_LINK_MODE_8_LANES (0xf << 16) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 35 | |
| 36 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
| 37 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) |
| 38 | #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 39 | #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) |
| 40 | #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) |
| 41 | #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) |
Zhou Wang | 5b0f073 | 2015-05-13 14:44:34 +0800 | [diff] [blame^] | 42 | #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 43 | |
| 44 | #define PCIE_MSI_ADDR_LO 0x820 |
| 45 | #define PCIE_MSI_ADDR_HI 0x824 |
| 46 | #define PCIE_MSI_INTR0_ENABLE 0x828 |
| 47 | #define PCIE_MSI_INTR0_MASK 0x82C |
| 48 | #define PCIE_MSI_INTR0_STATUS 0x830 |
| 49 | |
| 50 | #define PCIE_ATU_VIEWPORT 0x900 |
| 51 | #define PCIE_ATU_REGION_INBOUND (0x1 << 31) |
| 52 | #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) |
| 53 | #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) |
| 54 | #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) |
| 55 | #define PCIE_ATU_CR1 0x904 |
| 56 | #define PCIE_ATU_TYPE_MEM (0x0 << 0) |
| 57 | #define PCIE_ATU_TYPE_IO (0x2 << 0) |
| 58 | #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) |
| 59 | #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) |
| 60 | #define PCIE_ATU_CR2 0x908 |
| 61 | #define PCIE_ATU_ENABLE (0x1 << 31) |
| 62 | #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) |
| 63 | #define PCIE_ATU_LOWER_BASE 0x90C |
| 64 | #define PCIE_ATU_UPPER_BASE 0x910 |
| 65 | #define PCIE_ATU_LIMIT 0x914 |
| 66 | #define PCIE_ATU_LOWER_TARGET 0x918 |
| 67 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) |
| 68 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) |
| 69 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) |
| 70 | #define PCIE_ATU_UPPER_TARGET 0x91C |
| 71 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 72 | static struct hw_pci dw_pci; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 73 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 74 | static unsigned long global_io_offset; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 75 | |
| 76 | static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) |
| 77 | { |
Lucas Stach | 84a263f | 2014-09-05 09:37:55 -0600 | [diff] [blame] | 78 | BUG_ON(!sys->private_data); |
| 79 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 80 | return sys->private_data; |
| 81 | } |
| 82 | |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 83 | int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 84 | { |
| 85 | *val = readl(addr); |
| 86 | |
| 87 | if (size == 1) |
| 88 | *val = (*val >> (8 * (where & 3))) & 0xff; |
| 89 | else if (size == 2) |
| 90 | *val = (*val >> (8 * (where & 3))) & 0xffff; |
| 91 | else if (size != 4) |
| 92 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 93 | |
| 94 | return PCIBIOS_SUCCESSFUL; |
| 95 | } |
| 96 | |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 97 | int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 98 | { |
| 99 | if (size == 4) |
| 100 | writel(val, addr); |
| 101 | else if (size == 2) |
| 102 | writew(val, addr + (where & 2)); |
| 103 | else if (size == 1) |
| 104 | writeb(val, addr + (where & 3)); |
| 105 | else |
| 106 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 107 | |
| 108 | return PCIBIOS_SUCCESSFUL; |
| 109 | } |
| 110 | |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 111 | static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 112 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 113 | if (pp->ops->readl_rc) |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 114 | pp->ops->readl_rc(pp, pp->dbi_base + reg, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 115 | else |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 116 | *val = readl(pp->dbi_base + reg); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 117 | } |
| 118 | |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 119 | static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 120 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 121 | if (pp->ops->writel_rc) |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 122 | pp->ops->writel_rc(pp, val, pp->dbi_base + reg); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 123 | else |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 124 | writel(val, pp->dbi_base + reg); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 125 | } |
| 126 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 127 | static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, |
| 128 | u32 *val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 129 | { |
| 130 | int ret; |
| 131 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 132 | if (pp->ops->rd_own_conf) |
| 133 | ret = pp->ops->rd_own_conf(pp, where, size, val); |
| 134 | else |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 135 | ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, |
| 136 | size, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 137 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 138 | return ret; |
| 139 | } |
| 140 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 141 | static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, |
| 142 | u32 val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 143 | { |
| 144 | int ret; |
| 145 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 146 | if (pp->ops->wr_own_conf) |
| 147 | ret = pp->ops->wr_own_conf(pp, where, size, val); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 148 | else |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 149 | ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where, |
| 150 | size, val); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 151 | |
| 152 | return ret; |
| 153 | } |
| 154 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 155 | static struct irq_chip dw_msi_irq_chip = { |
| 156 | .name = "PCI-MSI", |
Thomas Gleixner | 280510f | 2014-11-23 12:23:20 +0100 | [diff] [blame] | 157 | .irq_enable = pci_msi_unmask_irq, |
| 158 | .irq_disable = pci_msi_mask_irq, |
| 159 | .irq_mask = pci_msi_mask_irq, |
| 160 | .irq_unmask = pci_msi_unmask_irq, |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 161 | }; |
| 162 | |
| 163 | /* MSI int handler */ |
Lucas Stach | 7f4f16e | 2014-03-28 17:52:58 +0100 | [diff] [blame] | 164 | irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 165 | { |
| 166 | unsigned long val; |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 167 | int i, pos, irq; |
Lucas Stach | 7f4f16e | 2014-03-28 17:52:58 +0100 | [diff] [blame] | 168 | irqreturn_t ret = IRQ_NONE; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 169 | |
| 170 | for (i = 0; i < MAX_MSI_CTRLS; i++) { |
| 171 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, |
| 172 | (u32 *)&val); |
| 173 | if (val) { |
Lucas Stach | 7f4f16e | 2014-03-28 17:52:58 +0100 | [diff] [blame] | 174 | ret = IRQ_HANDLED; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 175 | pos = 0; |
| 176 | while ((pos = find_next_bit(&val, 32, pos)) != 32) { |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 177 | irq = irq_find_mapping(pp->irq_domain, |
| 178 | i * 32 + pos); |
Harro Haan | ca16589 | 2013-12-12 19:29:03 +0100 | [diff] [blame] | 179 | dw_pcie_wr_own_conf(pp, |
| 180 | PCIE_MSI_INTR0_STATUS + i * 12, |
| 181 | 4, 1 << pos); |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 182 | generic_handle_irq(irq); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 183 | pos++; |
| 184 | } |
| 185 | } |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 186 | } |
Lucas Stach | 7f4f16e | 2014-03-28 17:52:58 +0100 | [diff] [blame] | 187 | |
| 188 | return ret; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 189 | } |
| 190 | |
| 191 | void dw_pcie_msi_init(struct pcie_port *pp) |
| 192 | { |
| 193 | pp->msi_data = __get_free_pages(GFP_KERNEL, 0); |
| 194 | |
| 195 | /* program the msi_data */ |
| 196 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, |
| 197 | virt_to_phys((void *)pp->msi_data)); |
| 198 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); |
| 199 | } |
| 200 | |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 201 | static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) |
| 202 | { |
| 203 | unsigned int res, bit, val; |
| 204 | |
| 205 | res = (irq / 32) * 12; |
| 206 | bit = irq % 32; |
| 207 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); |
| 208 | val &= ~(1 << bit); |
| 209 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); |
| 210 | } |
| 211 | |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 212 | static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, |
Jingoo Han | 58275f2f | 2013-12-27 09:30:25 +0900 | [diff] [blame] | 213 | unsigned int nvec, unsigned int pos) |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 214 | { |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 215 | unsigned int i; |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 216 | |
Bjorn Helgaas | 0b8cfb6 | 2013-12-09 15:11:25 -0700 | [diff] [blame] | 217 | for (i = 0; i < nvec; i++) { |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 218 | irq_set_msi_desc_off(irq_base, i, NULL); |
Jingoo Han | 58275f2f | 2013-12-27 09:30:25 +0900 | [diff] [blame] | 219 | /* Disable corresponding interrupt on MSI controller */ |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 220 | if (pp->ops->msi_clear_irq) |
| 221 | pp->ops->msi_clear_irq(pp, pos + i); |
| 222 | else |
| 223 | dw_pcie_msi_clear_irq(pp, pos + i); |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 224 | } |
Lucas Stach | c8df6ac | 2014-09-30 18:36:27 +0200 | [diff] [blame] | 225 | |
| 226 | bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec)); |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 227 | } |
| 228 | |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 229 | static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) |
| 230 | { |
| 231 | unsigned int res, bit, val; |
| 232 | |
| 233 | res = (irq / 32) * 12; |
| 234 | bit = irq % 32; |
| 235 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); |
| 236 | val |= 1 << bit; |
| 237 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); |
| 238 | } |
| 239 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 240 | static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) |
| 241 | { |
Lucas Stach | c8df6ac | 2014-09-30 18:36:27 +0200 | [diff] [blame] | 242 | int irq, pos0, i; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 243 | struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata); |
| 244 | |
Lucas Stach | c8df6ac | 2014-09-30 18:36:27 +0200 | [diff] [blame] | 245 | pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, |
| 246 | order_base_2(no_irqs)); |
| 247 | if (pos0 < 0) |
| 248 | goto no_valid_irq; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 249 | |
Pratyush Anand | 904d0e7 | 2013-10-09 21:32:12 +0900 | [diff] [blame] | 250 | irq = irq_find_mapping(pp->irq_domain, pos0); |
| 251 | if (!irq) |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 252 | goto no_valid_irq; |
| 253 | |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 254 | /* |
| 255 | * irq_create_mapping (called from dw_pcie_host_init) pre-allocates |
| 256 | * descs so there is no need to allocate descs here. We can therefore |
| 257 | * assume that if irq_find_mapping above returns non-zero, then the |
| 258 | * descs are also successfully allocated. |
| 259 | */ |
| 260 | |
Bjorn Helgaas | 0b8cfb6 | 2013-12-09 15:11:25 -0700 | [diff] [blame] | 261 | for (i = 0; i < no_irqs; i++) { |
Bjørn Erik Nilsen | be3f48c | 2013-11-29 14:35:24 +0100 | [diff] [blame] | 262 | if (irq_set_msi_desc_off(irq, i, desc) != 0) { |
| 263 | clear_irq_range(pp, irq, i, pos0); |
| 264 | goto no_valid_irq; |
| 265 | } |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 266 | /*Enable corresponding interrupt in MSI interrupt controller */ |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 267 | if (pp->ops->msi_set_irq) |
| 268 | pp->ops->msi_set_irq(pp, pos0 + i); |
| 269 | else |
| 270 | dw_pcie_msi_set_irq(pp, pos0 + i); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 271 | } |
| 272 | |
| 273 | *pos = pos0; |
| 274 | return irq; |
| 275 | |
| 276 | no_valid_irq: |
| 277 | *pos = pos0; |
| 278 | return -ENOSPC; |
| 279 | } |
| 280 | |
Yijing Wang | c2791b8 | 2014-11-11 17:45:45 -0700 | [diff] [blame] | 281 | static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 282 | struct msi_desc *desc) |
| 283 | { |
Lucas Stach | 91f8ae8 | 2014-09-30 18:36:26 +0200 | [diff] [blame] | 284 | int irq, pos; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 285 | struct msi_msg msg; |
| 286 | struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); |
| 287 | |
Lucas Stach | 19c5392 | 2015-01-27 10:24:53 -0600 | [diff] [blame] | 288 | if (desc->msi_attrib.is_msix) |
| 289 | return -EINVAL; |
| 290 | |
Lucas Stach | 91f8ae8 | 2014-09-30 18:36:26 +0200 | [diff] [blame] | 291 | irq = assign_irq(1, desc, &pos); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 292 | if (irq < 0) |
| 293 | return irq; |
| 294 | |
Minghuan Lian | 450e344 | 2014-09-23 22:28:58 +0800 | [diff] [blame] | 295 | if (pp->ops->get_msi_addr) |
| 296 | msg.address_lo = pp->ops->get_msi_addr(pp); |
Murali Karicheri | 2f37c5a | 2014-07-21 12:58:42 -0400 | [diff] [blame] | 297 | else |
| 298 | msg.address_lo = virt_to_phys((void *)pp->msi_data); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 299 | msg.address_hi = 0x0; |
Minghuan Lian | 24832b4 | 2014-09-23 22:28:59 +0800 | [diff] [blame] | 300 | |
| 301 | if (pp->ops->get_msi_data) |
| 302 | msg.data = pp->ops->get_msi_data(pp, pos); |
| 303 | else |
| 304 | msg.data = pos; |
| 305 | |
Jiang Liu | 83a1891 | 2014-11-09 23:10:34 +0800 | [diff] [blame] | 306 | pci_write_msi_msg(irq, &msg); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 307 | |
| 308 | return 0; |
| 309 | } |
| 310 | |
Yijing Wang | c2791b8 | 2014-11-11 17:45:45 -0700 | [diff] [blame] | 311 | static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 312 | { |
Lucas Stach | 91f8ae8 | 2014-09-30 18:36:26 +0200 | [diff] [blame] | 313 | struct irq_data *data = irq_get_irq_data(irq); |
| 314 | struct msi_desc *msi = irq_data_get_msi(data); |
| 315 | struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata); |
| 316 | |
| 317 | clear_irq_range(pp, irq, 1, data->hwirq); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 318 | } |
| 319 | |
Yijing Wang | c2791b8 | 2014-11-11 17:45:45 -0700 | [diff] [blame] | 320 | static struct msi_controller dw_pcie_msi_chip = { |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 321 | .setup_irq = dw_msi_setup_irq, |
| 322 | .teardown_irq = dw_msi_teardown_irq, |
| 323 | }; |
| 324 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 325 | int dw_pcie_link_up(struct pcie_port *pp) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 326 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 327 | if (pp->ops->link_up) |
| 328 | return pp->ops->link_up(pp); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 329 | else |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 330 | return 0; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 331 | } |
| 332 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 333 | static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, |
| 334 | irq_hw_number_t hwirq) |
| 335 | { |
| 336 | irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq); |
| 337 | irq_set_chip_data(irq, domain->host_data); |
| 338 | set_irq_flags(irq, IRQF_VALID); |
| 339 | |
| 340 | return 0; |
| 341 | } |
| 342 | |
| 343 | static const struct irq_domain_ops msi_domain_ops = { |
| 344 | .map = dw_pcie_msi_map, |
| 345 | }; |
| 346 | |
Matwey V. Kornilov | a43f32d | 2015-02-19 20:41:48 +0300 | [diff] [blame] | 347 | int dw_pcie_host_init(struct pcie_port *pp) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 348 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 349 | struct device_node *np = pp->dev->of_node; |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 350 | struct platform_device *pdev = to_platform_device(pp->dev); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 351 | struct of_pci_range range; |
| 352 | struct of_pci_range_parser parser; |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 353 | struct resource *cfg_res; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 354 | u32 val, na, ns; |
| 355 | const __be32 *addrp; |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 356 | int i, index, ret; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 357 | |
| 358 | /* Find the address cell size and the number of cells in order to get |
| 359 | * the untranslated address. |
| 360 | */ |
| 361 | of_property_read_u32(np, "#address-cells", &na); |
| 362 | ns = of_n_size_cells(np); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 363 | |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 364 | cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); |
| 365 | if (cfg_res) { |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 366 | pp->cfg0_size = resource_size(cfg_res)/2; |
| 367 | pp->cfg1_size = resource_size(cfg_res)/2; |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 368 | pp->cfg0_base = cfg_res->start; |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 369 | pp->cfg1_base = cfg_res->start + pp->cfg0_size; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 370 | |
| 371 | /* Find the untranslated configuration space address */ |
| 372 | index = of_property_match_string(np, "reg-names", "config"); |
Fabio Estevam | 9f0dbe0 | 2014-09-22 14:52:07 -0600 | [diff] [blame] | 373 | addrp = of_get_address(np, index, NULL, NULL); |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 374 | pp->cfg0_mod_base = of_read_number(addrp, ns); |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 375 | pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size; |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 376 | } else { |
| 377 | dev_err(pp->dev, "missing *config* reg space\n"); |
| 378 | } |
| 379 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 380 | if (of_pci_range_parser_init(&parser, np)) { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 381 | dev_err(pp->dev, "missing ranges property\n"); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 382 | return -EINVAL; |
| 383 | } |
| 384 | |
| 385 | /* Get the I/O and memory ranges from DT */ |
| 386 | for_each_of_pci_range(&parser, &range) { |
| 387 | unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; |
Jingoo Han | 2c992f3 | 2014-11-12 12:27:04 +0900 | [diff] [blame] | 388 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 389 | if (restype == IORESOURCE_IO) { |
| 390 | of_pci_range_to_resource(&range, np, &pp->io); |
| 391 | pp->io.name = "I/O"; |
| 392 | pp->io.start = max_t(resource_size_t, |
| 393 | PCIBIOS_MIN_IO, |
| 394 | range.pci_addr + global_io_offset); |
| 395 | pp->io.end = min_t(resource_size_t, |
| 396 | IO_SPACE_LIMIT, |
| 397 | range.pci_addr + range.size |
Minghuan Lian | 0c61ea7 | 2014-09-23 22:28:57 +0800 | [diff] [blame] | 398 | + global_io_offset - 1); |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 399 | pp->io_size = resource_size(&pp->io); |
| 400 | pp->io_bus_addr = range.pci_addr; |
Pratyush Anand | fce8591 | 2013-12-11 15:08:33 +0530 | [diff] [blame] | 401 | pp->io_base = range.cpu_addr; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 402 | |
| 403 | /* Find the untranslated IO space address */ |
| 404 | pp->io_mod_base = of_read_number(parser.range - |
| 405 | parser.np + na, ns); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 406 | } |
| 407 | if (restype == IORESOURCE_MEM) { |
| 408 | of_pci_range_to_resource(&range, np, &pp->mem); |
| 409 | pp->mem.name = "MEM"; |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 410 | pp->mem_size = resource_size(&pp->mem); |
| 411 | pp->mem_bus_addr = range.pci_addr; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 412 | |
| 413 | /* Find the untranslated MEM space address */ |
| 414 | pp->mem_mod_base = of_read_number(parser.range - |
| 415 | parser.np + na, ns); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 416 | } |
| 417 | if (restype == 0) { |
| 418 | of_pci_range_to_resource(&range, np, &pp->cfg); |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 419 | pp->cfg0_size = resource_size(&pp->cfg)/2; |
| 420 | pp->cfg1_size = resource_size(&pp->cfg)/2; |
Kishon Vijay Abraham I | 4dd964d | 2014-07-17 14:30:40 +0530 | [diff] [blame] | 421 | pp->cfg0_base = pp->cfg.start; |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 422 | pp->cfg1_base = pp->cfg.start + pp->cfg0_size; |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 423 | |
| 424 | /* Find the untranslated configuration space address */ |
| 425 | pp->cfg0_mod_base = of_read_number(parser.range - |
| 426 | parser.np + na, ns); |
| 427 | pp->cfg1_mod_base = pp->cfg0_mod_base + |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 428 | pp->cfg0_size; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 429 | } |
| 430 | } |
| 431 | |
Lucas Stach | 4f2ebe0 | 2014-07-23 19:52:38 +0200 | [diff] [blame] | 432 | ret = of_pci_parse_bus_range(np, &pp->busn); |
| 433 | if (ret < 0) { |
| 434 | pp->busn.name = np->name; |
| 435 | pp->busn.start = 0; |
| 436 | pp->busn.end = 0xff; |
| 437 | pp->busn.flags = IORESOURCE_BUS; |
| 438 | dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n", |
| 439 | ret, &pp->busn); |
| 440 | } |
| 441 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 442 | if (!pp->dbi_base) { |
| 443 | pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, |
| 444 | resource_size(&pp->cfg)); |
| 445 | if (!pp->dbi_base) { |
| 446 | dev_err(pp->dev, "error with ioremap\n"); |
| 447 | return -ENOMEM; |
| 448 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 449 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 450 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 451 | pp->mem_base = pp->mem.start; |
| 452 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 453 | if (!pp->va_cfg0_base) { |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 454 | pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 455 | pp->cfg0_size); |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 456 | if (!pp->va_cfg0_base) { |
| 457 | dev_err(pp->dev, "error with ioremap in function\n"); |
| 458 | return -ENOMEM; |
| 459 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 460 | } |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 461 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 462 | if (!pp->va_cfg1_base) { |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 463 | pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base, |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 464 | pp->cfg1_size); |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 465 | if (!pp->va_cfg1_base) { |
| 466 | dev_err(pp->dev, "error with ioremap\n"); |
| 467 | return -ENOMEM; |
| 468 | } |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 469 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 470 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 471 | if (of_property_read_u32(np, "num-lanes", &pp->lanes)) { |
| 472 | dev_err(pp->dev, "Failed to parse the number of lanes\n"); |
| 473 | return -EINVAL; |
| 474 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 475 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 476 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 477 | if (!pp->ops->msi_host_init) { |
| 478 | pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, |
| 479 | MAX_MSI_IRQS, &msi_domain_ops, |
| 480 | &dw_pcie_msi_chip); |
| 481 | if (!pp->irq_domain) { |
| 482 | dev_err(pp->dev, "irq domain init failed\n"); |
| 483 | return -ENXIO; |
| 484 | } |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 485 | |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 486 | for (i = 0; i < MAX_MSI_IRQS; i++) |
| 487 | irq_create_mapping(pp->irq_domain, i); |
| 488 | } else { |
| 489 | ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip); |
| 490 | if (ret < 0) |
| 491 | return ret; |
| 492 | } |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 493 | } |
| 494 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 495 | if (pp->ops->host_init) |
| 496 | pp->ops->host_init(pp); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 497 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 498 | dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); |
| 499 | |
| 500 | /* program correct class for RC */ |
| 501 | dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); |
| 502 | |
| 503 | dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); |
| 504 | val |= PORT_LOGIC_SPEED_CHANGE; |
| 505 | dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); |
| 506 | |
Yijing Wang | 0815f95 | 2014-11-11 15:38:07 -0700 | [diff] [blame] | 507 | #ifdef CONFIG_PCI_MSI |
| 508 | dw_pcie_msi_chip.dev = pp->dev; |
| 509 | dw_pci.msi_ctrl = &dw_pcie_msi_chip; |
| 510 | #endif |
| 511 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 512 | dw_pci.nr_controllers = 1; |
| 513 | dw_pci.private_data = (void **)&pp; |
| 514 | |
Lucas Stach | 804f57b | 2014-03-05 14:25:51 +0100 | [diff] [blame] | 515 | pci_common_init_dev(pp->dev, &dw_pci); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 516 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 517 | return 0; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 518 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 519 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 520 | static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) |
| 521 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 522 | /* Program viewport 0 : OUTBOUND : CFG0 */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 523 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, |
| 524 | PCIE_ATU_VIEWPORT); |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 525 | dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE); |
| 526 | dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE); |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 527 | dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->cfg0_size - 1, |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 528 | PCIE_ATU_LIMIT); |
| 529 | dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); |
| 530 | dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); |
| 531 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1); |
| 532 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 533 | } |
| 534 | |
| 535 | static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) |
| 536 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 537 | /* Program viewport 1 : OUTBOUND : CFG1 */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 538 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, |
| 539 | PCIE_ATU_VIEWPORT); |
| 540 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1); |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 541 | dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE); |
| 542 | dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE); |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 543 | dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->cfg1_size - 1, |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 544 | PCIE_ATU_LIMIT); |
| 545 | dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); |
| 546 | dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); |
Mohit Kumar | a19f88b | 2014-04-14 14:22:55 -0600 | [diff] [blame] | 547 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 548 | } |
| 549 | |
| 550 | static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) |
| 551 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 552 | /* Program viewport 0 : OUTBOUND : MEM */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 553 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, |
| 554 | PCIE_ATU_VIEWPORT); |
| 555 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 556 | dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE); |
| 557 | dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE); |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 558 | dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->mem_size - 1, |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 559 | PCIE_ATU_LIMIT); |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 560 | dw_pcie_writel_rc(pp, pp->mem_bus_addr, PCIE_ATU_LOWER_TARGET); |
| 561 | dw_pcie_writel_rc(pp, upper_32_bits(pp->mem_bus_addr), |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 562 | PCIE_ATU_UPPER_TARGET); |
Mohit Kumar | a19f88b | 2014-04-14 14:22:55 -0600 | [diff] [blame] | 563 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 564 | } |
| 565 | |
| 566 | static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) |
| 567 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 568 | /* Program viewport 1 : OUTBOUND : IO */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 569 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, |
| 570 | PCIE_ATU_VIEWPORT); |
| 571 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1); |
Kishon Vijay Abraham I | f4c55c5 | 2014-07-17 14:30:41 +0530 | [diff] [blame] | 572 | dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE); |
| 573 | dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE); |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 574 | dw_pcie_writel_rc(pp, pp->io_mod_base + pp->io_size - 1, |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 575 | PCIE_ATU_LIMIT); |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 576 | dw_pcie_writel_rc(pp, pp->io_bus_addr, PCIE_ATU_LOWER_TARGET); |
| 577 | dw_pcie_writel_rc(pp, upper_32_bits(pp->io_bus_addr), |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 578 | PCIE_ATU_UPPER_TARGET); |
Mohit Kumar | a19f88b | 2014-04-14 14:22:55 -0600 | [diff] [blame] | 579 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 580 | } |
| 581 | |
| 582 | static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
| 583 | u32 devfn, int where, int size, u32 *val) |
| 584 | { |
| 585 | int ret = PCIBIOS_SUCCESSFUL; |
| 586 | u32 address, busdev; |
| 587 | |
| 588 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
| 589 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); |
| 590 | address = where & ~0x3; |
| 591 | |
| 592 | if (bus->parent->number == pp->root_bus_nr) { |
| 593 | dw_pcie_prog_viewport_cfg0(pp, busdev); |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 594 | ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size, |
| 595 | val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 596 | dw_pcie_prog_viewport_mem_outbound(pp); |
| 597 | } else { |
| 598 | dw_pcie_prog_viewport_cfg1(pp, busdev); |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 599 | ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size, |
| 600 | val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 601 | dw_pcie_prog_viewport_io_outbound(pp); |
| 602 | } |
| 603 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 604 | return ret; |
| 605 | } |
| 606 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 607 | static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
| 608 | u32 devfn, int where, int size, u32 val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 609 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 610 | int ret = PCIBIOS_SUCCESSFUL; |
| 611 | u32 address, busdev; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 612 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 613 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
| 614 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); |
| 615 | address = where & ~0x3; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 616 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 617 | if (bus->parent->number == pp->root_bus_nr) { |
| 618 | dw_pcie_prog_viewport_cfg0(pp, busdev); |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 619 | ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size, |
| 620 | val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 621 | dw_pcie_prog_viewport_mem_outbound(pp); |
| 622 | } else { |
| 623 | dw_pcie_prog_viewport_cfg1(pp, busdev); |
Pratyush Anand | a01ef59 | 2013-12-11 15:08:32 +0530 | [diff] [blame] | 624 | ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size, |
| 625 | val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 626 | dw_pcie_prog_viewport_io_outbound(pp); |
| 627 | } |
| 628 | |
| 629 | return ret; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 630 | } |
| 631 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 632 | static int dw_pcie_valid_config(struct pcie_port *pp, |
| 633 | struct pci_bus *bus, int dev) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 634 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 635 | /* If there is no link, then there is no device */ |
| 636 | if (bus->number != pp->root_bus_nr) { |
| 637 | if (!dw_pcie_link_up(pp)) |
| 638 | return 0; |
| 639 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 640 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 641 | /* access only one slot on each root port */ |
| 642 | if (bus->number == pp->root_bus_nr && dev > 0) |
| 643 | return 0; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 644 | |
| 645 | /* |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 646 | * do not read more than one device on the bus directly attached |
| 647 | * to RC's (Virtual Bridge's) DS side. |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 648 | */ |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 649 | if (bus->primary == pp->root_bus_nr && dev > 0) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 650 | return 0; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 651 | |
| 652 | return 1; |
| 653 | } |
| 654 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 655 | static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
| 656 | int size, u32 *val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 657 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 658 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 659 | int ret; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 660 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 661 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { |
| 662 | *val = 0xffffffff; |
| 663 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 664 | } |
| 665 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 666 | if (bus->number != pp->root_bus_nr) |
Murali Karicheri | a1c0ae9 | 2014-07-21 12:58:41 -0400 | [diff] [blame] | 667 | if (pp->ops->rd_other_conf) |
| 668 | ret = pp->ops->rd_other_conf(pp, bus, devfn, |
| 669 | where, size, val); |
| 670 | else |
| 671 | ret = dw_pcie_rd_other_conf(pp, bus, devfn, |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 672 | where, size, val); |
| 673 | else |
| 674 | ret = dw_pcie_rd_own_conf(pp, where, size, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 675 | |
| 676 | return ret; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 677 | } |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 678 | |
| 679 | static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
| 680 | int where, int size, u32 val) |
| 681 | { |
| 682 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 683 | int ret; |
| 684 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 685 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) |
| 686 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 687 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 688 | if (bus->number != pp->root_bus_nr) |
Murali Karicheri | a1c0ae9 | 2014-07-21 12:58:41 -0400 | [diff] [blame] | 689 | if (pp->ops->wr_other_conf) |
| 690 | ret = pp->ops->wr_other_conf(pp, bus, devfn, |
| 691 | where, size, val); |
| 692 | else |
| 693 | ret = dw_pcie_wr_other_conf(pp, bus, devfn, |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 694 | where, size, val); |
| 695 | else |
| 696 | ret = dw_pcie_wr_own_conf(pp, where, size, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 697 | |
| 698 | return ret; |
| 699 | } |
| 700 | |
| 701 | static struct pci_ops dw_pcie_ops = { |
| 702 | .read = dw_pcie_rd_conf, |
| 703 | .write = dw_pcie_wr_conf, |
| 704 | }; |
| 705 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 706 | static int dw_pcie_setup(int nr, struct pci_sys_data *sys) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 707 | { |
| 708 | struct pcie_port *pp; |
| 709 | |
| 710 | pp = sys_to_pcie(sys); |
| 711 | |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 712 | if (global_io_offset < SZ_1M && pp->io_size > 0) { |
| 713 | sys->io_offset = global_io_offset - pp->io_bus_addr; |
Pratyush Anand | fce8591 | 2013-12-11 15:08:33 +0530 | [diff] [blame] | 714 | pci_ioremap_io(global_io_offset, pp->io_base); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 715 | global_io_offset += SZ_64K; |
| 716 | pci_add_resource_offset(&sys->resources, &pp->io, |
| 717 | sys->io_offset); |
| 718 | } |
| 719 | |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 720 | sys->mem_offset = pp->mem.start - pp->mem_bus_addr; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 721 | pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); |
Lucas Stach | 4f2ebe0 | 2014-07-23 19:52:38 +0200 | [diff] [blame] | 722 | pci_add_resource(&sys->resources, &pp->busn); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 723 | |
| 724 | return 1; |
| 725 | } |
| 726 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 727 | static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 728 | { |
| 729 | struct pci_bus *bus; |
| 730 | struct pcie_port *pp = sys_to_pcie(sys); |
| 731 | |
Lucas Stach | 92483df | 2014-07-23 19:52:39 +0200 | [diff] [blame] | 732 | pp->root_bus_nr = sys->busnr; |
| 733 | bus = pci_create_root_bus(pp->dev, sys->busnr, |
| 734 | &dw_pcie_ops, sys, &sys->resources); |
| 735 | if (!bus) |
| 736 | return NULL; |
| 737 | |
| 738 | pci_scan_child_bus(bus); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 739 | |
Murali Karicheri | b14a3d1 | 2014-07-23 14:54:51 -0400 | [diff] [blame] | 740 | if (bus && pp->ops->scan_bus) |
| 741 | pp->ops->scan_bus(pp); |
| 742 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 743 | return bus; |
| 744 | } |
| 745 | |
Bjorn Helgaas | 73e4085 | 2013-10-09 09:12:37 -0600 | [diff] [blame] | 746 | static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 747 | { |
| 748 | struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); |
Lucas Stach | 804f57b | 2014-03-05 14:25:51 +0100 | [diff] [blame] | 749 | int irq; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 750 | |
Lucas Stach | 804f57b | 2014-03-05 14:25:51 +0100 | [diff] [blame] | 751 | irq = of_irq_parse_and_map_pci(dev, slot, pin); |
| 752 | if (!irq) |
| 753 | irq = pp->irq; |
| 754 | |
| 755 | return irq; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 756 | } |
| 757 | |
| 758 | static struct hw_pci dw_pci = { |
| 759 | .setup = dw_pcie_setup, |
| 760 | .scan = dw_pcie_scan_bus, |
| 761 | .map_irq = dw_pcie_map_irq, |
| 762 | }; |
| 763 | |
| 764 | void dw_pcie_setup_rc(struct pcie_port *pp) |
| 765 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 766 | u32 val; |
| 767 | u32 membase; |
| 768 | u32 memlimit; |
| 769 | |
Mohit Kumar | 66c5c34 | 2014-04-14 14:22:54 -0600 | [diff] [blame] | 770 | /* set the number of lanes */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 771 | dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 772 | val &= ~PORT_LINK_MODE_MASK; |
| 773 | switch (pp->lanes) { |
| 774 | case 1: |
| 775 | val |= PORT_LINK_MODE_1_LANES; |
| 776 | break; |
| 777 | case 2: |
| 778 | val |= PORT_LINK_MODE_2_LANES; |
| 779 | break; |
| 780 | case 4: |
| 781 | val |= PORT_LINK_MODE_4_LANES; |
| 782 | break; |
Zhou Wang | 5b0f073 | 2015-05-13 14:44:34 +0800 | [diff] [blame^] | 783 | case 8: |
| 784 | val |= PORT_LINK_MODE_8_LANES; |
| 785 | break; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 786 | } |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 787 | dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 788 | |
| 789 | /* set link width speed control register */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 790 | dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 791 | val &= ~PORT_LOGIC_LINK_WIDTH_MASK; |
| 792 | switch (pp->lanes) { |
| 793 | case 1: |
| 794 | val |= PORT_LOGIC_LINK_WIDTH_1_LANES; |
| 795 | break; |
| 796 | case 2: |
| 797 | val |= PORT_LOGIC_LINK_WIDTH_2_LANES; |
| 798 | break; |
| 799 | case 4: |
| 800 | val |= PORT_LOGIC_LINK_WIDTH_4_LANES; |
| 801 | break; |
Zhou Wang | 5b0f073 | 2015-05-13 14:44:34 +0800 | [diff] [blame^] | 802 | case 8: |
| 803 | val |= PORT_LOGIC_LINK_WIDTH_8_LANES; |
| 804 | break; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 805 | } |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 806 | dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 807 | |
| 808 | /* setup RC BARs */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 809 | dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); |
Mohit Kumar | dbffdd6 | 2014-02-19 17:34:35 +0530 | [diff] [blame] | 810 | dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 811 | |
| 812 | /* setup interrupt pins */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 813 | dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 814 | val &= 0xffff00ff; |
| 815 | val |= 0x00000100; |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 816 | dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 817 | |
| 818 | /* setup bus numbers */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 819 | dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 820 | val &= 0xff000000; |
| 821 | val |= 0x00010100; |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 822 | dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 823 | |
| 824 | /* setup memory base, memory limit */ |
| 825 | membase = ((u32)pp->mem_base & 0xfff00000) >> 16; |
Pratyush Anand | adf70fc | 2014-09-05 17:48:54 -0600 | [diff] [blame] | 826 | memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 827 | val = memlimit | membase; |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 828 | dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 829 | |
| 830 | /* setup command register */ |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 831 | dw_pcie_readl_rc(pp, PCI_COMMAND, &val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 832 | val &= 0xffff0000; |
| 833 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
| 834 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; |
Seungwon Jeon | f7b7868 | 2013-08-28 20:53:30 +0900 | [diff] [blame] | 835 | dw_pcie_writel_rc(pp, val, PCI_COMMAND); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 836 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 837 | |
| 838 | MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 839 | MODULE_DESCRIPTION("Designware PCIe host controller driver"); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 840 | MODULE_LICENSE("GPL v2"); |