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review.shift-gmbh.com / SHIFTPHONES / android_kernel_shift_sdm845 / 56fb4df6da76c35dca22036174e2d1edef83ff1f / . / arch / sparc64 / kernel / tsb.S
blob: 50752c518773d3897a68143e7ca5282101049c76 [file] [log] [blame]
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]1/* tsb.S: Sparc64 TSB table handling.
2 *
3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
4 */
5
6#include <asm/tsb.h>
7
8 .text
9 .align 32
10
11 /* Invoked from TLB miss handler, we are in the
12 * MMU global registers and they are setup like
13 * this:
14 *
15 * %g1: TSB entry pointer
16 * %g2: available temporary
17 * %g3: FAULT_CODE_{D,I}TLB
18 * %g4: available temporary
19 * %g5: available temporary
20 * %g6: TAG TARGET
21 * %g7: physical address base of the linux page
22 * tables for the current address space
23 */
24 .globl tsb_miss_dtlb
25tsb_miss_dtlb:
26 mov TLB_TAG_ACCESS, %g4
27 ldxa [%g4] ASI_DMMU, %g4
28 ba,pt %xcc, tsb_miss_page_table_walk
29 nop
30
31 .globl tsb_miss_itlb
32tsb_miss_itlb:
33 mov TLB_TAG_ACCESS, %g4
34 ldxa [%g4] ASI_IMMU, %g4
35 ba,pt %xcc, tsb_miss_page_table_walk
36 nop
37
38tsb_miss_page_table_walk:
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame^]39 /* This clobbers %g1 and %g6, preserve them... */
40 mov %g1, %g5
41 mov %g6, %g2
42
43 TRAP_LOAD_PGD_PHYS
44
45 mov %g2, %g6
46 mov %g5, %g1
47
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]48 USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
49
50tsb_reload:
51 TSB_LOCK_TAG(%g1, %g2, %g4)
52
53 /* Load and check PTE. */
54 ldxa [%g5] ASI_PHYS_USE_EC, %g5
55 brgez,a,pn %g5, tsb_do_fault
56 stx %g0, [%g1]
57
58 TSB_WRITE(%g1, %g5, %g6)
59
60 /* Finally, load TLB and return from trap. */
61tsb_tlb_reload:
62 cmp %g3, FAULT_CODE_DTLB
63 bne,pn %xcc, tsb_itlb_load
64 nop
65
66tsb_dtlb_load:
67 stxa %g5, [%g0] ASI_DTLB_DATA_IN
68 retry
69
70tsb_itlb_load:
71 stxa %g5, [%g0] ASI_ITLB_DATA_IN
72 retry
73
74 /* No valid entry in the page tables, do full fault
75 * processing.
76 */
77
78 .globl tsb_do_fault
79tsb_do_fault:
80 cmp %g3, FAULT_CODE_DTLB
81 rdpr %pstate, %g5
82 bne,pn %xcc, tsb_do_itlb_fault
83 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
84
85tsb_do_dtlb_fault:
86 rdpr %tl, %g4
87 cmp %g4, 1
88 mov TLB_TAG_ACCESS, %g4
89 ldxa [%g4] ASI_DMMU, %g5
90 be,pt %xcc, sparc64_realfault_common
91 mov FAULT_CODE_DTLB, %g4
92 ba,pt %xcc, winfix_trampoline
93 nop
94
95tsb_do_itlb_fault:
96 rdpr %tpc, %g5
97 ba,pt %xcc, sparc64_realfault_common
98 mov FAULT_CODE_ITLB, %g4
99
100 .globl sparc64_realfault_common
101sparc64_realfault_common:
102 stb %g4, [%g6 + TI_FAULT_CODE] ! Save fault code
103 stx %g5, [%g6 + TI_FAULT_ADDR] ! Save fault address
104 ba,pt %xcc, etrap ! Save trap state
1051: rd %pc, %g7 ! ...
106 call do_sparc64_fault ! Call fault handler
107 add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
108 ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
109 nop ! Delay slot (fill me)
110
111 .globl winfix_trampoline
112winfix_trampoline:
113 rdpr %tpc, %g3 ! Prepare winfixup TNPC
114 or %g3, 0x7c, %g3 ! Compute branch offset
115 wrpr %g3, %tnpc ! Write it into TNPC
116 done ! Trap return
117
118 /* Reload MMU related context switch state at
119 * schedule() time.
120 *
121 * %o0: page table physical address
122 * %o1: TSB address
123 */
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame^]124 .align 32
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]125 .globl tsb_context_switch
126tsb_context_switch:
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame^]127 rdpr %pstate, %o5
128 wrpr %o5, PSTATE_IE, %pstate
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]129
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame^]130 ldub [%g6 + TI_CPU], %o3
131 sethi %hi(trap_block), %o4
132 sllx %o3, TRAP_BLOCK_SZ_SHIFT, %o3
133 or %o4, %lo(trap_block), %o4
134 add %o4, %o3, %o4
135 stx %o0, [%o4 + TRAP_PER_CPU_PGD_PADDR]
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]136
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame^]137 brgez %o1, 9f
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]138 nop
139
140 /* Lock TSB into D-TLB. */
141 sethi %hi(PAGE_SIZE), %o3
142 and %o3, %o1, %o3
143 sethi %hi(TSBMAP_BASE), %o2
144 add %o2, %o3, %o2
145
146 /* XXX handle PAGE_SIZE != 8K correctly... */
147 mov TSB_REG, %g1
148 stxa %o2, [%g1] ASI_DMMU
149 membar #Sync
150
151 stxa %o2, [%g1] ASI_IMMU
152 membar #Sync
153
154#define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZBITS)^0xfffff80000000000)
155#define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W | _PAGE_L)
156 sethi %uhi(KERN_HIGHBITS), %g2
157 or %g2, %ulo(KERN_HIGHBITS), %g2
158 sllx %g2, 32, %g2
159 or %g2, KERN_LOWBITS, %g2
160#undef KERN_HIGHBITS
161#undef KERN_LOWBITS
162
163 xor %o1, %g2, %o1
164
165 /* We use entry 61 for this locked entry. This is the spitfire
166 * TLB entry number, and luckily cheetah masks the value with
167 * 15 ending us up with entry 13 which is what we want in that
168 * case too.
169 *
170 * XXX Interactions with prom_world()...
171 */
172 mov TLB_TAG_ACCESS, %g1
173 stxa %o2, [%g1] ASI_DMMU
174 membar #Sync
175 mov (61 << 3), %g1
176 stxa %o1, [%g1] ASI_DTLB_DATA_ACCESS
177 membar #Sync
178
1799:
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame^]180 wrpr %o5, %pstate
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]181
182 retl
183 mov %o2, %o0