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Stephen Rothwellcabb5582005-09-30 16:16:52 +10001#include <linux/config.h>
2#ifdef CONFIG_PPC64
3#include <asm/page.h>
Paul Mackerras4a288562005-10-10 22:38:46 +10004#else
5#define PAGE_SIZE 4096
Stephen Rothwellcabb5582005-09-30 16:16:52 +10006#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +10007#include <asm-generic/vmlinux.lds.h>
8
Stephen Rothwellcabb5582005-09-30 16:16:52 +10009#ifdef CONFIG_PPC64
10OUTPUT_ARCH(powerpc:common64)
11jiffies = jiffies_64;
12#else
Paul Mackerras14cf11a2005-09-26 16:04:21 +100013OUTPUT_ARCH(powerpc:common)
14jiffies = jiffies_64 + 4;
Stephen Rothwellcabb5582005-09-30 16:16:52 +100015#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +100016SECTIONS
17{
Stephen Rothwellcabb5582005-09-30 16:16:52 +100018 /* Sections to be discarded. */
19 /DISCARD/ : {
20 *(.exitcall.exit)
Stephen Rothwellcabb5582005-09-30 16:16:52 +100021 *(.exit.data)
Stephen Rothwellcabb5582005-09-30 16:16:52 +100022 }
23
24
Paul Mackerras14cf11a2005-09-26 16:04:21 +100025 /* Read-only sections, merged into text segment: */
Stephen Rothwellcabb5582005-09-30 16:16:52 +100026#ifdef CONFIG_PPC32
Paul Mackerras14cf11a2005-09-26 16:04:21 +100027 . = + SIZEOF_HEADERS;
28 .interp : { *(.interp) }
29 .hash : { *(.hash) }
30 .dynsym : { *(.dynsym) }
31 .dynstr : { *(.dynstr) }
32 .rel.text : { *(.rel.text) }
33 .rela.text : { *(.rela.text) }
34 .rel.data : { *(.rel.data) }
35 .rela.data : { *(.rela.data) }
36 .rel.rodata : { *(.rel.rodata) }
37 .rela.rodata : { *(.rela.rodata) }
38 .rel.got : { *(.rel.got) }
39 .rela.got : { *(.rela.got) }
40 .rel.ctors : { *(.rel.ctors) }
41 .rela.ctors : { *(.rela.ctors) }
42 .rel.dtors : { *(.rel.dtors) }
43 .rela.dtors : { *(.rela.dtors) }
44 .rel.bss : { *(.rel.bss) }
45 .rela.bss : { *(.rela.bss) }
46 .rel.plt : { *(.rel.plt) }
47 .rela.plt : { *(.rela.plt) }
48/* .init : { *(.init) } =0*/
49 .plt : { *(.plt) }
Stephen Rothwellcabb5582005-09-30 16:16:52 +100050#endif
51 .text : {
Stephen Rothwellcabb5582005-09-30 16:16:52 +100052 *(.text .text.*)
Paul Mackerras14cf11a2005-09-26 16:04:21 +100053 SCHED_TEXT
54 LOCK_TEXT
Stephen Rothwellcabb5582005-09-30 16:16:52 +100055 KPROBES_TEXT
Paul Mackerras14cf11a2005-09-26 16:04:21 +100056 *(.fixup)
Stephen Rothwellcabb5582005-09-30 16:16:52 +100057#ifdef CONFIG_PPC32
Paul Mackerras14cf11a2005-09-26 16:04:21 +100058 *(.got1)
59 __got2_start = .;
60 *(.got2)
61 __got2_end = .;
Stephen Rothwellcabb5582005-09-30 16:16:52 +100062#else
63 . = ALIGN(PAGE_SIZE);
64 _etext = .;
65#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +100066 }
Stephen Rothwellcabb5582005-09-30 16:16:52 +100067#ifdef CONFIG_PPC32
Paul Mackerras14cf11a2005-09-26 16:04:21 +100068 _etext = .;
69 PROVIDE (etext = .);
70
71 RODATA
72 .fini : { *(.fini) } =0
73 .ctors : { *(.ctors) }
74 .dtors : { *(.dtors) }
75
76 .fixup : { *(.fixup) }
Stephen Rothwellcabb5582005-09-30 16:16:52 +100077#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +100078
79 __ex_table : {
80 __start___ex_table = .;
81 *(__ex_table)
82 __stop___ex_table = .;
83 }
84
85 __bug_table : {
86 __start___bug_table = .;
87 *(__bug_table)
88 __stop___bug_table = .;
89 }
90
Stephen Rothwellcabb5582005-09-30 16:16:52 +100091#ifdef CONFIG_PPC64
92 __ftr_fixup : {
93 __start___ftr_fixup = .;
94 *(__ftr_fixup)
95 __stop___ftr_fixup = .;
96 }
97
98 RODATA
99#endif
100
101#ifdef CONFIG_PPC32
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000102 /* Read-write section, merged into data segment: */
Paul Mackerras4a288562005-10-10 22:38:46 +1000103 . = ALIGN(PAGE_SIZE);
Paul Mackerrasc16ff7e2005-10-06 13:28:31 +1000104 _sdata = .;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000105 .data :
106 {
107 *(.data)
108 *(.data1)
109 *(.sdata)
110 *(.sdata2)
111 *(.got.plt) *(.got)
112 *(.dynamic)
113 CONSTRUCTORS
114 }
115
Paul Mackerras4a288562005-10-10 22:38:46 +1000116 . = ALIGN(PAGE_SIZE);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000117 __nosave_begin = .;
118 .data_nosave : { *(.data.nosave) }
Paul Mackerras4a288562005-10-10 22:38:46 +1000119 . = ALIGN(PAGE_SIZE);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000120 __nosave_end = .;
121
122 . = ALIGN(32);
123 .data.cacheline_aligned : { *(.data.cacheline_aligned) }
124
125 _edata = .;
126 PROVIDE (edata = .);
127
128 . = ALIGN(8192);
129 .data.init_task : { *(.data.init_task) }
Paul Mackerras4a288562005-10-10 22:38:46 +1000130#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000131
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000132 /* will be freed after init */
133 . = ALIGN(PAGE_SIZE);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000134 __init_begin = .;
135 .init.text : {
136 _sinittext = .;
137 *(.init.text)
138 _einittext = .;
139 }
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000140#ifdef CONFIG_PPC32
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000141 /* .exit.text is discarded at runtime, not link time,
142 to deal with references from __bug_table */
143 .exit.text : { *(.exit.text) }
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000144#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000145 .init.data : {
146 *(.init.data);
147 __vtop_table_begin = .;
148 *(.vtop_fixup);
149 __vtop_table_end = .;
150 __ptov_table_begin = .;
151 *(.ptov_fixup);
152 __ptov_table_end = .;
153 }
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000154
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000155 . = ALIGN(16);
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000156 .init.setup : {
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000157 __setup_start = .;
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000158 *(.init.setup)
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000159 __setup_end = .;
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000160 }
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000161
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000162 .initcall.init : {
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000163 __initcall_start = .;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000164 *(.initcall1.init)
165 *(.initcall2.init)
166 *(.initcall3.init)
167 *(.initcall4.init)
168 *(.initcall5.init)
169 *(.initcall6.init)
170 *(.initcall7.init)
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000171 __initcall_end = .;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000172 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000173
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000174 .con_initcall.init : {
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000175 __con_initcall_start = .;
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000176 *(.con_initcall.init)
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000177 __con_initcall_end = .;
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000178 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000179
180 SECURITY_INIT
181
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000182#ifdef CONFIG_PPC32
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000183 __start___ftr_fixup = .;
184 __ftr_fixup : { *(__ftr_fixup) }
185 __stop___ftr_fixup = .;
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000186#else
187 . = ALIGN(PAGE_SIZE);
188 .init.ramfs : {
189 __initramfs_start = .;
190 *(.init.ramfs)
191 __initramfs_end = .;
192 }
193#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000194
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000195#ifdef CONFIG_PPC32
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000196 . = ALIGN(32);
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000197#endif
198 .data.percpu : {
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000199 __per_cpu_start = .;
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000200 *(.data.percpu)
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000201 __per_cpu_end = .;
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000202 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000203
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000204 . = ALIGN(PAGE_SIZE);
Paul Mackerras4a288562005-10-10 22:38:46 +1000205#ifdef CONFIG_PPC64
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000206 . = ALIGN(16384);
207 __init_end = .;
208 /* freed after init ends here */
209
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000210 /* Read/write sections */
211 . = ALIGN(PAGE_SIZE);
212 . = ALIGN(16384);
Paul Mackerras4a288562005-10-10 22:38:46 +1000213 _sdata = .;
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000214 /* The initial task and kernel stack */
215 .data.init_task : {
216 *(.data.init_task)
217 }
218
219 . = ALIGN(PAGE_SIZE);
220 .data.page_aligned : {
221 *(.data.page_aligned)
222 }
223
224 .data.cacheline_aligned : {
225 *(.data.cacheline_aligned)
226 }
227
228 .data : {
229 *(.data .data.rel* .toc1)
230 *(.branch_lt)
231 }
232
233 .opd : {
234 *(.opd)
235 }
236
237 .got : {
238 __toc_start = .;
239 *(.got)
240 *(.toc)
241 . = ALIGN(PAGE_SIZE);
242 _edata = .;
243 }
244
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000245 . = ALIGN(PAGE_SIZE);
246#else
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000247 __initramfs_start = .;
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000248 .init.ramfs : {
249 *(.init.ramfs)
250 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000251 __initramfs_end = .;
252
253 . = ALIGN(4096);
254 __init_end = .;
255
256 . = ALIGN(4096);
257 _sextratext = .;
258 _eextratext = .;
259
260 __bss_start = .;
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000261#endif
Paul Mackerras4a288562005-10-10 22:38:46 +1000262
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000263 .bss : {
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000264 __bss_start = .;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000265 *(.sbss) *(.scommon)
266 *(.dynbss)
267 *(.bss)
268 *(COMMON)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000269 __bss_stop = .;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000270 }
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000271
272#ifdef CONFIG_PPC64
273 . = ALIGN(PAGE_SIZE);
274#endif
275 _end = . ;
276#ifdef CONFIG_PPC32
277 PROVIDE (end = .);
278#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000279}