Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/kernel/irq/chip.c |
| 3 | * |
| 4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
| 5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King |
| 6 | * |
| 7 | * This file contains the core interrupt handling code, for irq-chip |
| 8 | * based architectures. |
| 9 | * |
| 10 | * Detailed information is available in Documentation/DocBook/genericirq |
| 11 | */ |
| 12 | |
| 13 | #include <linux/irq.h> |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 14 | #include <linux/msi.h> |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 15 | #include <linux/module.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/kernel_stat.h> |
| 18 | |
| 19 | #include "internals.h" |
| 20 | |
| 21 | /** |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 22 | * dynamic_irq_init - initialize a dynamically allocated irq |
| 23 | * @irq: irq number to initialize |
| 24 | */ |
| 25 | void dynamic_irq_init(unsigned int irq) |
| 26 | { |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 27 | struct irq_desc *desc; |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 28 | unsigned long flags; |
| 29 | |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 30 | desc = irq_to_desc(irq); |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 31 | if (!desc) { |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 32 | WARN(1, KERN_ERR "Trying to initialize invalid IRQ%d\n", irq); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 33 | return; |
| 34 | } |
| 35 | |
| 36 | /* Ensure we don't have left over values from a previous use of this irq */ |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 37 | spin_lock_irqsave(&desc->lock, flags); |
| 38 | desc->status = IRQ_DISABLED; |
| 39 | desc->chip = &no_irq_chip; |
| 40 | desc->handle_irq = handle_bad_irq; |
| 41 | desc->depth = 1; |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 42 | desc->msi_desc = NULL; |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 43 | desc->handler_data = NULL; |
| 44 | desc->chip_data = NULL; |
| 45 | desc->action = NULL; |
| 46 | desc->irq_count = 0; |
| 47 | desc->irqs_unhandled = 0; |
| 48 | #ifdef CONFIG_SMP |
Rusty Russell | 0de2652 | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 49 | cpumask_setall(&desc->affinity); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 50 | #endif |
| 51 | spin_unlock_irqrestore(&desc->lock, flags); |
| 52 | } |
| 53 | |
| 54 | /** |
| 55 | * dynamic_irq_cleanup - cleanup a dynamically allocated irq |
| 56 | * @irq: irq number to initialize |
| 57 | */ |
| 58 | void dynamic_irq_cleanup(unsigned int irq) |
| 59 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 60 | struct irq_desc *desc = irq_to_desc(irq); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 61 | unsigned long flags; |
| 62 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 63 | if (!desc) { |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 64 | WARN(1, KERN_ERR "Trying to cleanup invalid IRQ%d\n", irq); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 65 | return; |
| 66 | } |
| 67 | |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 68 | spin_lock_irqsave(&desc->lock, flags); |
Eric W. Biederman | 1f80025 | 2006-10-04 02:16:56 -0700 | [diff] [blame] | 69 | if (desc->action) { |
| 70 | spin_unlock_irqrestore(&desc->lock, flags); |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 71 | WARN(1, KERN_ERR "Destroying IRQ%d without calling free_irq\n", |
Eric W. Biederman | 1f80025 | 2006-10-04 02:16:56 -0700 | [diff] [blame] | 72 | irq); |
Eric W. Biederman | 1f80025 | 2006-10-04 02:16:56 -0700 | [diff] [blame] | 73 | return; |
| 74 | } |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 75 | desc->msi_desc = NULL; |
| 76 | desc->handler_data = NULL; |
| 77 | desc->chip_data = NULL; |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 78 | desc->handle_irq = handle_bad_irq; |
| 79 | desc->chip = &no_irq_chip; |
Dean Nelson | b6f3b78 | 2008-10-18 16:06:56 -0700 | [diff] [blame] | 80 | desc->name = NULL; |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 81 | spin_unlock_irqrestore(&desc->lock, flags); |
| 82 | } |
| 83 | |
| 84 | |
| 85 | /** |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 86 | * set_irq_chip - set the irq chip for an irq |
| 87 | * @irq: irq number |
| 88 | * @chip: pointer to irq chip description structure |
| 89 | */ |
| 90 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) |
| 91 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 92 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 93 | unsigned long flags; |
| 94 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 95 | if (!desc) { |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 96 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 97 | return -EINVAL; |
| 98 | } |
| 99 | |
| 100 | if (!chip) |
| 101 | chip = &no_irq_chip; |
| 102 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 103 | spin_lock_irqsave(&desc->lock, flags); |
| 104 | irq_chip_set_defaults(chip); |
| 105 | desc->chip = chip; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 106 | spin_unlock_irqrestore(&desc->lock, flags); |
| 107 | |
| 108 | return 0; |
| 109 | } |
| 110 | EXPORT_SYMBOL(set_irq_chip); |
| 111 | |
| 112 | /** |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 113 | * set_irq_type - set the irq trigger type for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 114 | * @irq: irq number |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 115 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 116 | */ |
| 117 | int set_irq_type(unsigned int irq, unsigned int type) |
| 118 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 119 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 120 | unsigned long flags; |
| 121 | int ret = -ENXIO; |
| 122 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 123 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 124 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
| 125 | return -ENODEV; |
| 126 | } |
| 127 | |
David Brownell | f2b662d | 2008-12-01 14:31:38 -0800 | [diff] [blame] | 128 | type &= IRQ_TYPE_SENSE_MASK; |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 129 | if (type == IRQ_TYPE_NONE) |
| 130 | return 0; |
| 131 | |
| 132 | spin_lock_irqsave(&desc->lock, flags); |
Chris Friesen | 0b3682ba3 | 2008-10-20 12:41:58 -0600 | [diff] [blame] | 133 | ret = __irq_set_trigger(desc, irq, type); |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 134 | spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 135 | return ret; |
| 136 | } |
| 137 | EXPORT_SYMBOL(set_irq_type); |
| 138 | |
| 139 | /** |
| 140 | * set_irq_data - set irq type data for an irq |
| 141 | * @irq: Interrupt number |
| 142 | * @data: Pointer to interrupt specific data |
| 143 | * |
| 144 | * Set the hardware irq controller data for an irq |
| 145 | */ |
| 146 | int set_irq_data(unsigned int irq, void *data) |
| 147 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 148 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 149 | unsigned long flags; |
| 150 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 151 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 152 | printk(KERN_ERR |
| 153 | "Trying to install controller data for IRQ%d\n", irq); |
| 154 | return -EINVAL; |
| 155 | } |
| 156 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 157 | spin_lock_irqsave(&desc->lock, flags); |
| 158 | desc->handler_data = data; |
| 159 | spin_unlock_irqrestore(&desc->lock, flags); |
| 160 | return 0; |
| 161 | } |
| 162 | EXPORT_SYMBOL(set_irq_data); |
| 163 | |
| 164 | /** |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 165 | * set_irq_data - set irq type data for an irq |
| 166 | * @irq: Interrupt number |
Randy Dunlap | 472900b | 2007-02-16 01:28:25 -0800 | [diff] [blame] | 167 | * @entry: Pointer to MSI descriptor data |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 168 | * |
| 169 | * Set the hardware irq controller data for an irq |
| 170 | */ |
| 171 | int set_irq_msi(unsigned int irq, struct msi_desc *entry) |
| 172 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 173 | struct irq_desc *desc = irq_to_desc(irq); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 174 | unsigned long flags; |
| 175 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 176 | if (!desc) { |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 177 | printk(KERN_ERR |
| 178 | "Trying to install msi data for IRQ%d\n", irq); |
| 179 | return -EINVAL; |
| 180 | } |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 181 | |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 182 | spin_lock_irqsave(&desc->lock, flags); |
| 183 | desc->msi_desc = entry; |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 184 | if (entry) |
| 185 | entry->irq = irq; |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 186 | spin_unlock_irqrestore(&desc->lock, flags); |
| 187 | return 0; |
| 188 | } |
| 189 | |
| 190 | /** |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 191 | * set_irq_chip_data - set irq chip data for an irq |
| 192 | * @irq: Interrupt number |
| 193 | * @data: Pointer to chip specific data |
| 194 | * |
| 195 | * Set the hardware irq chip data for an irq |
| 196 | */ |
| 197 | int set_irq_chip_data(unsigned int irq, void *data) |
| 198 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 199 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 200 | unsigned long flags; |
| 201 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 202 | if (!desc) { |
| 203 | printk(KERN_ERR |
| 204 | "Trying to install chip data for IRQ%d\n", irq); |
| 205 | return -EINVAL; |
| 206 | } |
| 207 | |
| 208 | if (!desc->chip) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 209 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
| 210 | return -EINVAL; |
| 211 | } |
| 212 | |
| 213 | spin_lock_irqsave(&desc->lock, flags); |
| 214 | desc->chip_data = data; |
| 215 | spin_unlock_irqrestore(&desc->lock, flags); |
| 216 | |
| 217 | return 0; |
| 218 | } |
| 219 | EXPORT_SYMBOL(set_irq_chip_data); |
| 220 | |
| 221 | /* |
| 222 | * default enable function |
| 223 | */ |
| 224 | static void default_enable(unsigned int irq) |
| 225 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 226 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 227 | |
| 228 | desc->chip->unmask(irq); |
| 229 | desc->status &= ~IRQ_MASKED; |
| 230 | } |
| 231 | |
| 232 | /* |
| 233 | * default disable function |
| 234 | */ |
| 235 | static void default_disable(unsigned int irq) |
| 236 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | /* |
| 240 | * default startup function |
| 241 | */ |
| 242 | static unsigned int default_startup(unsigned int irq) |
| 243 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 244 | struct irq_desc *desc = irq_to_desc(irq); |
Yinghai Lu | 08678b0 | 2008-08-19 20:50:05 -0700 | [diff] [blame] | 245 | |
Yinghai Lu | 08678b0 | 2008-08-19 20:50:05 -0700 | [diff] [blame] | 246 | desc->chip->enable(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 247 | return 0; |
| 248 | } |
| 249 | |
| 250 | /* |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 251 | * default shutdown function |
| 252 | */ |
| 253 | static void default_shutdown(unsigned int irq) |
| 254 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 255 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 256 | |
| 257 | desc->chip->mask(irq); |
| 258 | desc->status |= IRQ_MASKED; |
| 259 | } |
| 260 | |
| 261 | /* |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 262 | * Fixup enable/disable function pointers |
| 263 | */ |
| 264 | void irq_chip_set_defaults(struct irq_chip *chip) |
| 265 | { |
| 266 | if (!chip->enable) |
| 267 | chip->enable = default_enable; |
| 268 | if (!chip->disable) |
| 269 | chip->disable = default_disable; |
| 270 | if (!chip->startup) |
| 271 | chip->startup = default_startup; |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 272 | /* |
| 273 | * We use chip->disable, when the user provided its own. When |
| 274 | * we have default_disable set for chip->disable, then we need |
| 275 | * to use default_shutdown, otherwise the irq line is not |
| 276 | * disabled on free_irq(): |
| 277 | */ |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 278 | if (!chip->shutdown) |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 279 | chip->shutdown = chip->disable != default_disable ? |
| 280 | chip->disable : default_shutdown; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 281 | if (!chip->name) |
| 282 | chip->name = chip->typename; |
Zhang, Yanmin | b86432b | 2006-11-16 01:19:10 -0800 | [diff] [blame] | 283 | if (!chip->end) |
| 284 | chip->end = dummy_irq_chip.end; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 285 | } |
| 286 | |
| 287 | static inline void mask_ack_irq(struct irq_desc *desc, int irq) |
| 288 | { |
| 289 | if (desc->chip->mask_ack) |
| 290 | desc->chip->mask_ack(irq); |
| 291 | else { |
| 292 | desc->chip->mask(irq); |
| 293 | desc->chip->ack(irq); |
| 294 | } |
| 295 | } |
| 296 | |
| 297 | /** |
| 298 | * handle_simple_irq - Simple and software-decoded IRQs. |
| 299 | * @irq: the interrupt number |
| 300 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 301 | * |
| 302 | * Simple interrupts are either sent from a demultiplexing interrupt |
| 303 | * handler or come from hardware, where no interrupt hardware control |
| 304 | * is necessary. |
| 305 | * |
| 306 | * Note: The caller is expected to handle the ack, clear, mask and |
| 307 | * unmask issues if necessary. |
| 308 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 309 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 310 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 311 | { |
| 312 | struct irqaction *action; |
| 313 | irqreturn_t action_ret; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 314 | |
| 315 | spin_lock(&desc->lock); |
| 316 | |
| 317 | if (unlikely(desc->status & IRQ_INPROGRESS)) |
| 318 | goto out_unlock; |
Steven Rostedt | 971e5b35f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 319 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 320 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 321 | |
| 322 | action = desc->action; |
Steven Rostedt | 971e5b35f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 323 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 324 | goto out_unlock; |
| 325 | |
| 326 | desc->status |= IRQ_INPROGRESS; |
| 327 | spin_unlock(&desc->lock); |
| 328 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 329 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 330 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 331 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 332 | |
| 333 | spin_lock(&desc->lock); |
| 334 | desc->status &= ~IRQ_INPROGRESS; |
| 335 | out_unlock: |
| 336 | spin_unlock(&desc->lock); |
| 337 | } |
| 338 | |
| 339 | /** |
| 340 | * handle_level_irq - Level type irq handler |
| 341 | * @irq: the interrupt number |
| 342 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 343 | * |
| 344 | * Level type interrupts are active as long as the hardware line has |
| 345 | * the active level. This may require to mask the interrupt and unmask |
| 346 | * it after the associated handler has acknowledged the device, so the |
| 347 | * interrupt line is back to inactive. |
| 348 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 349 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 350 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 351 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 352 | struct irqaction *action; |
| 353 | irqreturn_t action_ret; |
| 354 | |
| 355 | spin_lock(&desc->lock); |
| 356 | mask_ack_irq(desc, irq); |
Yinghai Lu | 48a1b10 | 2008-12-11 00:15:01 -0800 | [diff] [blame] | 357 | desc = irq_remap_to_desc(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 358 | |
| 359 | if (unlikely(desc->status & IRQ_INPROGRESS)) |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 360 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 361 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 362 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 363 | |
| 364 | /* |
| 365 | * If its disabled or no action available |
| 366 | * keep it masked and get out of here |
| 367 | */ |
| 368 | action = desc->action; |
Thomas Gleixner | 4966342 | 2007-08-12 15:46:34 +0000 | [diff] [blame] | 369 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 370 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 371 | |
| 372 | desc->status |= IRQ_INPROGRESS; |
| 373 | spin_unlock(&desc->lock); |
| 374 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 375 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 376 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 377 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 378 | |
| 379 | spin_lock(&desc->lock); |
| 380 | desc->status &= ~IRQ_INPROGRESS; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 381 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) |
| 382 | desc->chip->unmask(irq); |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 383 | out_unlock: |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 384 | spin_unlock(&desc->lock); |
| 385 | } |
| 386 | |
| 387 | /** |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 388 | * handle_fasteoi_irq - irq handler for transparent controllers |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 389 | * @irq: the interrupt number |
| 390 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 391 | * |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 392 | * Only a single callback will be issued to the chip: an ->eoi() |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 393 | * call when the interrupt has been serviced. This enables support |
| 394 | * for modern forms of interrupt handlers, which handle the flow |
| 395 | * details in hardware, transparently. |
| 396 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 397 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 398 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 399 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 400 | struct irqaction *action; |
| 401 | irqreturn_t action_ret; |
| 402 | |
| 403 | spin_lock(&desc->lock); |
| 404 | |
| 405 | if (unlikely(desc->status & IRQ_INPROGRESS)) |
| 406 | goto out; |
| 407 | |
| 408 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 409 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 410 | |
| 411 | /* |
| 412 | * If its disabled or no action available |
Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 413 | * then mask it and get out of here: |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 414 | */ |
| 415 | action = desc->action; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 416 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
| 417 | desc->status |= IRQ_PENDING; |
Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 418 | if (desc->chip->mask) |
| 419 | desc->chip->mask(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 420 | goto out; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 421 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 422 | |
| 423 | desc->status |= IRQ_INPROGRESS; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 424 | desc->status &= ~IRQ_PENDING; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 425 | spin_unlock(&desc->lock); |
| 426 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 427 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 428 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 429 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 430 | |
| 431 | spin_lock(&desc->lock); |
| 432 | desc->status &= ~IRQ_INPROGRESS; |
| 433 | out: |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 434 | desc->chip->eoi(irq); |
Yinghai Lu | 48a1b10 | 2008-12-11 00:15:01 -0800 | [diff] [blame] | 435 | desc = irq_remap_to_desc(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 436 | |
| 437 | spin_unlock(&desc->lock); |
| 438 | } |
| 439 | |
| 440 | /** |
| 441 | * handle_edge_irq - edge type IRQ handler |
| 442 | * @irq: the interrupt number |
| 443 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 444 | * |
| 445 | * Interrupt occures on the falling and/or rising edge of a hardware |
| 446 | * signal. The occurence is latched into the irq controller hardware |
| 447 | * and must be acked in order to be reenabled. After the ack another |
| 448 | * interrupt can happen on the same source even before the first one |
| 449 | * is handled by the assosiacted event handler. If this happens it |
| 450 | * might be necessary to disable (mask) the interrupt depending on the |
| 451 | * controller hardware. This requires to reenable the interrupt inside |
| 452 | * of the loop which handles the interrupts which have arrived while |
| 453 | * the handler was running. If all pending interrupts are handled, the |
| 454 | * loop is left. |
| 455 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 456 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 457 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 458 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 459 | spin_lock(&desc->lock); |
| 460 | |
| 461 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
| 462 | |
| 463 | /* |
| 464 | * If we're currently running this IRQ, or its disabled, |
| 465 | * we shouldn't process the IRQ. Mark it pending, handle |
| 466 | * the necessary masking and go out |
| 467 | */ |
| 468 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || |
| 469 | !desc->action)) { |
| 470 | desc->status |= (IRQ_PENDING | IRQ_MASKED); |
| 471 | mask_ack_irq(desc, irq); |
Yinghai Lu | 48a1b10 | 2008-12-11 00:15:01 -0800 | [diff] [blame] | 472 | desc = irq_remap_to_desc(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 473 | goto out_unlock; |
| 474 | } |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 475 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 476 | |
| 477 | /* Start handling the irq */ |
| 478 | desc->chip->ack(irq); |
Yinghai Lu | 48a1b10 | 2008-12-11 00:15:01 -0800 | [diff] [blame] | 479 | desc = irq_remap_to_desc(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 480 | |
| 481 | /* Mark the IRQ currently in progress.*/ |
| 482 | desc->status |= IRQ_INPROGRESS; |
| 483 | |
| 484 | do { |
| 485 | struct irqaction *action = desc->action; |
| 486 | irqreturn_t action_ret; |
| 487 | |
| 488 | if (unlikely(!action)) { |
| 489 | desc->chip->mask(irq); |
| 490 | goto out_unlock; |
| 491 | } |
| 492 | |
| 493 | /* |
| 494 | * When another irq arrived while we were handling |
| 495 | * one, we could have masked the irq. |
| 496 | * Renable it, if it was not disabled in meantime. |
| 497 | */ |
| 498 | if (unlikely((desc->status & |
| 499 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == |
| 500 | (IRQ_PENDING | IRQ_MASKED))) { |
| 501 | desc->chip->unmask(irq); |
| 502 | desc->status &= ~IRQ_MASKED; |
| 503 | } |
| 504 | |
| 505 | desc->status &= ~IRQ_PENDING; |
| 506 | spin_unlock(&desc->lock); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 507 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 508 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 509 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 510 | spin_lock(&desc->lock); |
| 511 | |
| 512 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); |
| 513 | |
| 514 | desc->status &= ~IRQ_INPROGRESS; |
| 515 | out_unlock: |
| 516 | spin_unlock(&desc->lock); |
| 517 | } |
| 518 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 519 | /** |
| 520 | * handle_percpu_IRQ - Per CPU local irq handler |
| 521 | * @irq: the interrupt number |
| 522 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 523 | * |
| 524 | * Per CPU interrupts on SMP machines without locking requirements |
| 525 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 526 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 527 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 528 | { |
| 529 | irqreturn_t action_ret; |
| 530 | |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 531 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 532 | |
| 533 | if (desc->chip->ack) |
| 534 | desc->chip->ack(irq); |
| 535 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 536 | action_ret = handle_IRQ_event(irq, desc->action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 537 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 538 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 539 | |
Yinghai Lu | 48a1b10 | 2008-12-11 00:15:01 -0800 | [diff] [blame] | 540 | if (desc->chip->eoi) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 541 | desc->chip->eoi(irq); |
Yinghai Lu | 48a1b10 | 2008-12-11 00:15:01 -0800 | [diff] [blame] | 542 | desc = irq_remap_to_desc(irq, desc); |
| 543 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 544 | } |
| 545 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 546 | void |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 547 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
| 548 | const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 549 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 550 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 551 | unsigned long flags; |
| 552 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 553 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 554 | printk(KERN_ERR |
| 555 | "Trying to install type control for IRQ%d\n", irq); |
| 556 | return; |
| 557 | } |
| 558 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 559 | if (!handle) |
| 560 | handle = handle_bad_irq; |
Thomas Gleixner | 9d7ac8b | 2006-12-22 01:08:14 -0800 | [diff] [blame] | 561 | else if (desc->chip == &no_irq_chip) { |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 562 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
Geert Uytterhoeven | b039db8 | 2006-12-20 15:59:48 +0100 | [diff] [blame] | 563 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 564 | /* |
| 565 | * Some ARM implementations install a handler for really dumb |
| 566 | * interrupt hardware without setting an irq_chip. This worked |
| 567 | * with the ARM no_irq_chip but the check in setup_irq would |
| 568 | * prevent us to setup the interrupt at all. Switch it to |
| 569 | * dummy_irq_chip for easy transition. |
| 570 | */ |
| 571 | desc->chip = &dummy_irq_chip; |
| 572 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 573 | |
| 574 | spin_lock_irqsave(&desc->lock, flags); |
| 575 | |
| 576 | /* Uninstall? */ |
| 577 | if (handle == handle_bad_irq) { |
Yinghai Lu | 48a1b10 | 2008-12-11 00:15:01 -0800 | [diff] [blame] | 578 | if (desc->chip != &no_irq_chip) { |
Jan Beulich | 5575ddf | 2007-02-16 01:28:26 -0800 | [diff] [blame] | 579 | mask_ack_irq(desc, irq); |
Yinghai Lu | 48a1b10 | 2008-12-11 00:15:01 -0800 | [diff] [blame] | 580 | desc = irq_remap_to_desc(irq, desc); |
| 581 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 582 | desc->status |= IRQ_DISABLED; |
| 583 | desc->depth = 1; |
| 584 | } |
| 585 | desc->handle_irq = handle; |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 586 | desc->name = name; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 587 | |
| 588 | if (handle != handle_bad_irq && is_chained) { |
| 589 | desc->status &= ~IRQ_DISABLED; |
| 590 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; |
| 591 | desc->depth = 0; |
Pawel MOLL | 7e6e178 | 2008-09-01 10:12:11 +0100 | [diff] [blame] | 592 | desc->chip->startup(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 593 | } |
| 594 | spin_unlock_irqrestore(&desc->lock, flags); |
| 595 | } |
| 596 | |
| 597 | void |
| 598 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
David Howells | 57a58a9 | 2006-10-05 13:06:34 +0100 | [diff] [blame] | 599 | irq_flow_handler_t handle) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 600 | { |
| 601 | set_irq_chip(irq, chip); |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 602 | __set_irq_handler(irq, handle, 0, NULL); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 603 | } |
| 604 | |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 605 | void |
| 606 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
| 607 | irq_flow_handler_t handle, const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 608 | { |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 609 | set_irq_chip(irq, chip); |
| 610 | __set_irq_handler(irq, handle, 0, name); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 611 | } |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 612 | |
| 613 | void __init set_irq_noprobe(unsigned int irq) |
| 614 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 615 | struct irq_desc *desc = irq_to_desc(irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 616 | unsigned long flags; |
| 617 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 618 | if (!desc) { |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 619 | printk(KERN_ERR "Trying to mark IRQ%d non-probeable\n", irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 620 | return; |
| 621 | } |
| 622 | |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 623 | spin_lock_irqsave(&desc->lock, flags); |
| 624 | desc->status |= IRQ_NOPROBE; |
| 625 | spin_unlock_irqrestore(&desc->lock, flags); |
| 626 | } |
| 627 | |
| 628 | void __init set_irq_probe(unsigned int irq) |
| 629 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 630 | struct irq_desc *desc = irq_to_desc(irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 631 | unsigned long flags; |
| 632 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 633 | if (!desc) { |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 634 | printk(KERN_ERR "Trying to mark IRQ%d probeable\n", irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 635 | return; |
| 636 | } |
| 637 | |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 638 | spin_lock_irqsave(&desc->lock, flags); |
| 639 | desc->status &= ~IRQ_NOPROBE; |
| 640 | spin_unlock_irqrestore(&desc->lock, flags); |
| 641 | } |