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Magnus Damm44358042013-02-18 23:28:34 +09001/*
2 * Renesas INTC External IRQ Pin Driver
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/irqdomain.h>
28#include <linux/err.h>
29#include <linux/slab.h>
30#include <linux/module.h>
31#include <linux/platform_data/irq-renesas-intc-irqpin.h>
32
33#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
34
35#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
36#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
37#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
38#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
39#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
40#define INTC_IRQPIN_REG_NR 5
41
42/* INTC external IRQ PIN hardware register access:
43 *
44 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
45 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
46 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
47 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
48 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
49 *
50 * (*) May be accessed by more than one driver instance - lock needed
51 * (**) Read-modify-write access by one driver instance - lock needed
52 * (***) Accessed by one driver instance only - no locking needed
53 */
54
55struct intc_irqpin_iomem {
56 void __iomem *iomem;
57 unsigned long (*read)(void __iomem *iomem);
58 void (*write)(void __iomem *iomem, unsigned long data);
59 int width;
Magnus Damm862d3092013-02-26 20:58:44 +090060};
Magnus Damm44358042013-02-18 23:28:34 +090061
62struct intc_irqpin_irq {
63 int hw_irq;
Magnus Damm33f958f2013-02-26 20:58:54 +090064 int requested_irq;
65 int domain_irq;
Magnus Damm44358042013-02-18 23:28:34 +090066 struct intc_irqpin_priv *p;
Magnus Damm862d3092013-02-26 20:58:44 +090067};
Magnus Damm44358042013-02-18 23:28:34 +090068
69struct intc_irqpin_priv {
70 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
71 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
72 struct renesas_intc_irqpin_config config;
73 unsigned int number_of_irqs;
74 struct platform_device *pdev;
75 struct irq_chip irq_chip;
76 struct irq_domain *irq_domain;
77};
78
79static unsigned long intc_irqpin_read32(void __iomem *iomem)
80{
81 return ioread32(iomem);
82}
83
84static unsigned long intc_irqpin_read8(void __iomem *iomem)
85{
86 return ioread8(iomem);
87}
88
89static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
90{
91 iowrite32(data, iomem);
92}
93
94static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
95{
96 iowrite8(data, iomem);
97}
98
99static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
100 int reg)
101{
102 struct intc_irqpin_iomem *i = &p->iomem[reg];
Magnus Damm862d3092013-02-26 20:58:44 +0900103
Magnus Damm44358042013-02-18 23:28:34 +0900104 return i->read(i->iomem);
105}
106
107static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
108 int reg, unsigned long data)
109{
110 struct intc_irqpin_iomem *i = &p->iomem[reg];
Magnus Damm862d3092013-02-26 20:58:44 +0900111
Magnus Damm44358042013-02-18 23:28:34 +0900112 i->write(i->iomem, data);
113}
114
115static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
116 int reg, int hw_irq)
117{
118 return BIT((p->iomem[reg].width - 1) - hw_irq);
119}
120
121static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
122 int reg, int hw_irq)
123{
124 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
125}
126
127static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
128
129static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
130 int reg, int shift,
131 int width, int value)
132{
133 unsigned long flags;
134 unsigned long tmp;
135
136 raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
137
138 tmp = intc_irqpin_read(p, reg);
139 tmp &= ~(((1 << width) - 1) << shift);
140 tmp |= value << shift;
141 intc_irqpin_write(p, reg, tmp);
142
143 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
144}
145
146static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
147 int irq, int do_mask)
148{
149 int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
150 int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
151
152 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
153 shift, bitfield_width,
154 do_mask ? 0 : (1 << bitfield_width) - 1);
155}
156
157static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
158{
159 int bitfield_width = p->config.sense_bitfield_width;
160 int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
161
162 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
163
164 if (value >= (1 << bitfield_width))
165 return -EINVAL;
166
167 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
168 bitfield_width, value);
169 return 0;
170}
171
172static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
173{
174 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
Magnus Damm33f958f2013-02-26 20:58:54 +0900175 str, i->requested_irq, i->hw_irq, i->domain_irq);
Magnus Damm44358042013-02-18 23:28:34 +0900176}
177
178static void intc_irqpin_irq_enable(struct irq_data *d)
179{
180 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
181 int hw_irq = irqd_to_hwirq(d);
182
183 intc_irqpin_dbg(&p->irq[hw_irq], "enable");
184 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
185}
186
187static void intc_irqpin_irq_disable(struct irq_data *d)
188{
189 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
190 int hw_irq = irqd_to_hwirq(d);
191
192 intc_irqpin_dbg(&p->irq[hw_irq], "disable");
193 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
194}
195
196static void intc_irqpin_irq_enable_force(struct irq_data *d)
197{
198 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
Magnus Damm33f958f2013-02-26 20:58:54 +0900199 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
Magnus Damm44358042013-02-18 23:28:34 +0900200
201 intc_irqpin_irq_enable(d);
202 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
203}
204
205static void intc_irqpin_irq_disable_force(struct irq_data *d)
206{
207 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
Magnus Damm33f958f2013-02-26 20:58:54 +0900208 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
Magnus Damm44358042013-02-18 23:28:34 +0900209
210 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
211 intc_irqpin_irq_disable(d);
212}
213
214#define INTC_IRQ_SENSE_VALID 0x10
215#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
216
217static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
218 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
219 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
220 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
221 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
222 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
223};
224
225static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
226{
227 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
228 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
229
230 if (!(value & INTC_IRQ_SENSE_VALID))
231 return -EINVAL;
232
233 return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
234 value ^ INTC_IRQ_SENSE_VALID);
235}
236
237static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
238{
239 struct intc_irqpin_irq *i = dev_id;
240 struct intc_irqpin_priv *p = i->p;
241 unsigned long bit;
242
243 intc_irqpin_dbg(i, "demux1");
244 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
245
246 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
247 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
248 intc_irqpin_dbg(i, "demux2");
Magnus Damm33f958f2013-02-26 20:58:54 +0900249 generic_handle_irq(i->domain_irq);
Magnus Damm44358042013-02-18 23:28:34 +0900250 return IRQ_HANDLED;
251 }
252 return IRQ_NONE;
253}
254
255static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
256 irq_hw_number_t hw)
257{
258 struct intc_irqpin_priv *p = h->host_data;
259
Magnus Damm33f958f2013-02-26 20:58:54 +0900260 p->irq[hw].domain_irq = virq;
261 p->irq[hw].hw_irq = hw;
262
Magnus Damm44358042013-02-18 23:28:34 +0900263 intc_irqpin_dbg(&p->irq[hw], "map");
264 irq_set_chip_data(virq, h->host_data);
265 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
266 set_irq_flags(virq, IRQF_VALID); /* kill me now */
267 return 0;
268}
269
270static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
271 .map = intc_irqpin_irq_domain_map,
272};
273
274static int intc_irqpin_probe(struct platform_device *pdev)
275{
276 struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data;
277 struct intc_irqpin_priv *p;
278 struct intc_irqpin_iomem *i;
279 struct resource *io[INTC_IRQPIN_REG_NR];
280 struct resource *irq;
281 struct irq_chip *irq_chip;
282 void (*enable_fn)(struct irq_data *d);
283 void (*disable_fn)(struct irq_data *d);
284 const char *name = dev_name(&pdev->dev);
285 int ret;
286 int k;
287
288 p = kzalloc(sizeof(*p), GFP_KERNEL);
289 if (!p) {
290 dev_err(&pdev->dev, "failed to allocate driver data\n");
291 ret = -ENOMEM;
292 goto err0;
293 }
294
295 /* deal with driver instance configuration */
296 if (pdata)
297 memcpy(&p->config, pdata, sizeof(*pdata));
298 if (!p->config.sense_bitfield_width)
299 p->config.sense_bitfield_width = 4; /* default to 4 bits */
300
301 p->pdev = pdev;
302 platform_set_drvdata(pdev, p);
303
304 /* get hold of manadatory IOMEM */
305 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
306 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
307 if (!io[k]) {
308 dev_err(&pdev->dev, "not enough IOMEM resources\n");
309 ret = -EINVAL;
310 goto err1;
311 }
312 }
313
314 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
315 for (k = 0; k < INTC_IRQPIN_MAX; k++) {
316 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
317 if (!irq)
318 break;
319
Magnus Damm44358042013-02-18 23:28:34 +0900320 p->irq[k].p = p;
Magnus Damm33f958f2013-02-26 20:58:54 +0900321 p->irq[k].requested_irq = irq->start;
Magnus Damm44358042013-02-18 23:28:34 +0900322 }
323
324 p->number_of_irqs = k;
325 if (p->number_of_irqs < 1) {
326 dev_err(&pdev->dev, "not enough IRQ resources\n");
327 ret = -EINVAL;
328 goto err1;
329 }
330
331 /* ioremap IOMEM and setup read/write callbacks */
332 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
333 i = &p->iomem[k];
334
335 switch (resource_size(io[k])) {
336 case 1:
337 i->width = 8;
338 i->read = intc_irqpin_read8;
339 i->write = intc_irqpin_write8;
340 break;
341 case 4:
342 i->width = 32;
343 i->read = intc_irqpin_read32;
344 i->write = intc_irqpin_write32;
345 break;
346 default:
347 dev_err(&pdev->dev, "IOMEM size mismatch\n");
348 ret = -EINVAL;
349 goto err2;
350 }
351
352 i->iomem = ioremap_nocache(io[k]->start, resource_size(io[k]));
353 if (!i->iomem) {
354 dev_err(&pdev->dev, "failed to remap IOMEM\n");
355 ret = -ENXIO;
356 goto err2;
357 }
358 }
359
360 /* mask all interrupts using priority */
361 for (k = 0; k < p->number_of_irqs; k++)
362 intc_irqpin_mask_unmask_prio(p, k, 1);
363
364 /* use more severe masking method if requested */
365 if (p->config.control_parent) {
366 enable_fn = intc_irqpin_irq_enable_force;
367 disable_fn = intc_irqpin_irq_disable_force;
368 } else {
369 enable_fn = intc_irqpin_irq_enable;
370 disable_fn = intc_irqpin_irq_disable;
371 }
372
373 irq_chip = &p->irq_chip;
374 irq_chip->name = name;
375 irq_chip->irq_mask = disable_fn;
376 irq_chip->irq_unmask = enable_fn;
377 irq_chip->irq_enable = enable_fn;
378 irq_chip->irq_disable = disable_fn;
379 irq_chip->irq_set_type = intc_irqpin_irq_set_type;
380 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
381
382 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
383 p->number_of_irqs,
384 p->config.irq_base,
385 &intc_irqpin_irq_domain_ops, p);
386 if (!p->irq_domain) {
387 ret = -ENXIO;
388 dev_err(&pdev->dev, "cannot initialize irq domain\n");
389 goto err2;
390 }
391
392 /* request and set priority on interrupts one by one */
393 for (k = 0; k < p->number_of_irqs; k++) {
Magnus Damm33f958f2013-02-26 20:58:54 +0900394 if (request_irq(p->irq[k].requested_irq,
395 intc_irqpin_irq_handler,
Magnus Damm44358042013-02-18 23:28:34 +0900396 0, name, &p->irq[k])) {
397 dev_err(&pdev->dev, "failed to request low IRQ\n");
398 ret = -ENOENT;
399 goto err3;
400 }
401 intc_irqpin_mask_unmask_prio(p, k, 0);
402 }
403
404 dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
405
406 /* warn in case of mismatch if irq base is specified */
407 if (p->config.irq_base) {
Magnus Damm33f958f2013-02-26 20:58:54 +0900408 if (p->config.irq_base != p->irq[0].domain_irq)
Magnus Damm44358042013-02-18 23:28:34 +0900409 dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
Magnus Damm33f958f2013-02-26 20:58:54 +0900410 p->config.irq_base, p->irq[0].domain_irq);
Magnus Damm44358042013-02-18 23:28:34 +0900411 }
Magnus Damm862d3092013-02-26 20:58:44 +0900412
Magnus Damm44358042013-02-18 23:28:34 +0900413 return 0;
414
415err3:
416 for (; k >= 0; k--)
Magnus Damm33f958f2013-02-26 20:58:54 +0900417 free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]);
Magnus Damm44358042013-02-18 23:28:34 +0900418
419 irq_domain_remove(p->irq_domain);
420err2:
421 for (k = 0; k < INTC_IRQPIN_REG_NR; k++)
422 iounmap(p->iomem[k].iomem);
423err1:
424 kfree(p);
425err0:
426 return ret;
427}
428
429static int intc_irqpin_remove(struct platform_device *pdev)
430{
431 struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
432 int k;
433
434 for (k = 0; k < p->number_of_irqs; k++)
Magnus Damm33f958f2013-02-26 20:58:54 +0900435 free_irq(p->irq[k].requested_irq, &p->irq[k]);
Magnus Damm44358042013-02-18 23:28:34 +0900436
437 irq_domain_remove(p->irq_domain);
438
439 for (k = 0; k < INTC_IRQPIN_REG_NR; k++)
440 iounmap(p->iomem[k].iomem);
441
442 kfree(p);
443 return 0;
444}
445
446static struct platform_driver intc_irqpin_device_driver = {
447 .probe = intc_irqpin_probe,
448 .remove = intc_irqpin_remove,
449 .driver = {
450 .name = "renesas_intc_irqpin",
451 }
452};
453
454static int __init intc_irqpin_init(void)
455{
456 return platform_driver_register(&intc_irqpin_device_driver);
457}
458postcore_initcall(intc_irqpin_init);
459
460static void __exit intc_irqpin_exit(void)
461{
462 platform_driver_unregister(&intc_irqpin_device_driver);
463}
464module_exit(intc_irqpin_exit);
465
466MODULE_AUTHOR("Magnus Damm");
467MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
468MODULE_LICENSE("GPL v2");