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Anver sadhique276e2a42021-02-16 11:35:57 +05301/* Copyright (c) 2012-2019, 2021, The Linux Foundation. All rights reserved.
Alexander Martinz28de9412021-09-09 17:05:05 +02002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef _MSM_PCM_ROUTING_H
13#define _MSM_PCM_ROUTING_H
14#include <dsp/apr_audio-v2.h>
15
16/*
17 * These names are used by HAL to specify the BE. If any changes are
18 * made to the string names or the max name length corresponding
19 * changes need to be made in the HAL to ensure they still match.
20 */
21#define LPASS_BE_NAME_MAX_LENGTH 24
22#define LPASS_BE_PRI_I2S_RX "PRIMARY_I2S_RX"
23#define LPASS_BE_PRI_I2S_TX "PRIMARY_I2S_TX"
24#define LPASS_BE_SLIMBUS_0_RX "SLIMBUS_0_RX"
25#define LPASS_BE_SLIMBUS_0_TX "SLIMBUS_0_TX"
26#define LPASS_BE_HDMI "HDMI"
27#define LPASS_BE_DISPLAY_PORT "DISPLAY_PORT"
28#define LPASS_BE_INT_BT_SCO_RX "INT_BT_SCO_RX"
29#define LPASS_BE_INT_BT_SCO_TX "INT_BT_SCO_TX"
30#define LPASS_BE_INT_BT_A2DP_RX "INT_BT_A2DP_RX"
31#define LPASS_BE_INT_FM_RX "INT_FM_RX"
32#define LPASS_BE_INT_FM_TX "INT_FM_TX"
33#define LPASS_BE_AFE_PCM_RX "RT_PROXY_DAI_001_RX"
34#define LPASS_BE_AFE_PCM_TX "RT_PROXY_DAI_002_TX"
35#define LPASS_BE_AUXPCM_RX "AUX_PCM_RX"
36#define LPASS_BE_AUXPCM_TX "AUX_PCM_TX"
37#define LPASS_BE_SEC_AUXPCM_RX "SEC_AUX_PCM_RX"
38#define LPASS_BE_SEC_AUXPCM_TX "SEC_AUX_PCM_TX"
39#define LPASS_BE_TERT_AUXPCM_RX "TERT_AUX_PCM_RX"
40#define LPASS_BE_TERT_AUXPCM_TX "TERT_AUX_PCM_TX"
41#define LPASS_BE_QUAT_AUXPCM_RX "QUAT_AUX_PCM_RX"
42#define LPASS_BE_QUAT_AUXPCM_TX "QUAT_AUX_PCM_TX"
43#define LPASS_BE_QUIN_AUXPCM_RX "QUIN_AUX_PCM_RX"
44#define LPASS_BE_QUIN_AUXPCM_TX "QUIN_AUX_PCM_TX"
45#define LPASS_BE_VOICE_PLAYBACK_TX "VOICE_PLAYBACK_TX"
46#define LPASS_BE_VOICE2_PLAYBACK_TX "VOICE2_PLAYBACK_TX"
47#define LPASS_BE_INCALL_RECORD_RX "INCALL_RECORD_RX"
48#define LPASS_BE_INCALL_RECORD_TX "INCALL_RECORD_TX"
Anver sadhique276e2a42021-02-16 11:35:57 +053049#define LPASS_BE_PROXY_RX "PROXY_RX"
50#define LPASS_BE_PROXY_TX "PROXY_TX"
Alexander Martinz28de9412021-09-09 17:05:05 +020051#define LPASS_BE_SEC_I2S_RX "SECONDARY_I2S_RX"
52#define LPASS_BE_SPDIF_RX "SPDIF_RX"
53
54#define LPASS_BE_MI2S_RX "MI2S_RX"
55#define LPASS_BE_MI2S_TX "MI2S_TX"
56#define LPASS_BE_QUAT_MI2S_RX "QUAT_MI2S_RX"
57#define LPASS_BE_QUAT_MI2S_TX "QUAT_MI2S_TX"
58#define LPASS_BE_SEC_MI2S_RX "SEC_MI2S_RX"
59#define LPASS_BE_SEC_MI2S_RX_SD1 "SEC_MI2S_RX_SD1"
60#define LPASS_BE_SEC_MI2S_TX "SEC_MI2S_TX"
61#define LPASS_BE_PRI_MI2S_RX "PRI_MI2S_RX"
62#define LPASS_BE_PRI_MI2S_TX "PRI_MI2S_TX"
63#define LPASS_BE_TERT_MI2S_RX "TERT_MI2S_RX"
64#define LPASS_BE_TERT_MI2S_TX "TERT_MI2S_TX"
65#define LPASS_BE_AUDIO_I2S_RX "AUDIO_I2S_RX"
66#define LPASS_BE_STUB_RX "STUB_RX"
67#define LPASS_BE_STUB_TX "STUB_TX"
68#define LPASS_BE_SLIMBUS_1_RX "SLIMBUS_1_RX"
69#define LPASS_BE_SLIMBUS_1_TX "SLIMBUS_1_TX"
70#define LPASS_BE_STUB_1_TX "STUB_1_TX"
71#define LPASS_BE_SLIMBUS_2_RX "SLIMBUS_2_RX"
72#define LPASS_BE_SLIMBUS_2_TX "SLIMBUS_2_TX"
73#define LPASS_BE_SLIMBUS_3_RX "SLIMBUS_3_RX"
74#define LPASS_BE_SLIMBUS_3_TX "SLIMBUS_3_TX"
75#define LPASS_BE_SLIMBUS_4_RX "SLIMBUS_4_RX"
76#define LPASS_BE_SLIMBUS_4_TX "SLIMBUS_4_TX"
77#define LPASS_BE_SLIMBUS_TX_VI "SLIMBUS_TX_VI"
78#define LPASS_BE_SLIMBUS_5_RX "SLIMBUS_5_RX"
79#define LPASS_BE_SLIMBUS_5_TX "SLIMBUS_5_TX"
80#define LPASS_BE_SLIMBUS_6_RX "SLIMBUS_6_RX"
81#define LPASS_BE_SLIMBUS_6_TX "SLIMBUS_6_TX"
82#define LPASS_BE_QUIN_MI2S_RX "QUIN_MI2S_RX"
83#define LPASS_BE_QUIN_MI2S_TX "QUIN_MI2S_TX"
84#define LPASS_BE_SENARY_MI2S_TX "SENARY_MI2S_TX"
85
86#define LPASS_BE_PRI_TDM_RX_0 "PRI_TDM_RX_0"
87#define LPASS_BE_PRI_TDM_TX_0 "PRI_TDM_TX_0"
88#define LPASS_BE_PRI_TDM_RX_1 "PRI_TDM_RX_1"
89#define LPASS_BE_PRI_TDM_TX_1 "PRI_TDM_TX_1"
90#define LPASS_BE_PRI_TDM_RX_2 "PRI_TDM_RX_2"
91#define LPASS_BE_PRI_TDM_TX_2 "PRI_TDM_TX_2"
92#define LPASS_BE_PRI_TDM_RX_3 "PRI_TDM_RX_3"
93#define LPASS_BE_PRI_TDM_TX_3 "PRI_TDM_TX_3"
94#define LPASS_BE_PRI_TDM_RX_4 "PRI_TDM_RX_4"
95#define LPASS_BE_PRI_TDM_TX_4 "PRI_TDM_TX_4"
96#define LPASS_BE_PRI_TDM_RX_5 "PRI_TDM_RX_5"
97#define LPASS_BE_PRI_TDM_TX_5 "PRI_TDM_TX_5"
98#define LPASS_BE_PRI_TDM_RX_6 "PRI_TDM_RX_6"
99#define LPASS_BE_PRI_TDM_TX_6 "PRI_TDM_TX_6"
100#define LPASS_BE_PRI_TDM_RX_7 "PRI_TDM_RX_7"
101#define LPASS_BE_PRI_TDM_TX_7 "PRI_TDM_TX_7"
102#define LPASS_BE_SEC_TDM_RX_0 "SEC_TDM_RX_0"
103#define LPASS_BE_SEC_TDM_TX_0 "SEC_TDM_TX_0"
104#define LPASS_BE_SEC_TDM_RX_1 "SEC_TDM_RX_1"
105#define LPASS_BE_SEC_TDM_TX_1 "SEC_TDM_TX_1"
106#define LPASS_BE_SEC_TDM_RX_2 "SEC_TDM_RX_2"
107#define LPASS_BE_SEC_TDM_TX_2 "SEC_TDM_TX_2"
108#define LPASS_BE_SEC_TDM_RX_3 "SEC_TDM_RX_3"
109#define LPASS_BE_SEC_TDM_TX_3 "SEC_TDM_TX_3"
110#define LPASS_BE_SEC_TDM_RX_4 "SEC_TDM_RX_4"
111#define LPASS_BE_SEC_TDM_TX_4 "SEC_TDM_TX_4"
112#define LPASS_BE_SEC_TDM_RX_5 "SEC_TDM_RX_5"
113#define LPASS_BE_SEC_TDM_TX_5 "SEC_TDM_TX_5"
114#define LPASS_BE_SEC_TDM_RX_6 "SEC_TDM_RX_6"
115#define LPASS_BE_SEC_TDM_TX_6 "SEC_TDM_TX_6"
116#define LPASS_BE_SEC_TDM_RX_7 "SEC_TDM_RX_7"
117#define LPASS_BE_SEC_TDM_TX_7 "SEC_TDM_TX_7"
118#define LPASS_BE_TERT_TDM_RX_0 "TERT_TDM_RX_0"
119#define LPASS_BE_TERT_TDM_TX_0 "TERT_TDM_TX_0"
120#define LPASS_BE_TERT_TDM_RX_1 "TERT_TDM_RX_1"
121#define LPASS_BE_TERT_TDM_TX_1 "TERT_TDM_TX_1"
122#define LPASS_BE_TERT_TDM_RX_2 "TERT_TDM_RX_2"
123#define LPASS_BE_TERT_TDM_TX_2 "TERT_TDM_TX_2"
124#define LPASS_BE_TERT_TDM_RX_3 "TERT_TDM_RX_3"
125#define LPASS_BE_TERT_TDM_TX_3 "TERT_TDM_TX_3"
126#define LPASS_BE_TERT_TDM_RX_4 "TERT_TDM_RX_4"
127#define LPASS_BE_TERT_TDM_TX_4 "TERT_TDM_TX_4"
128#define LPASS_BE_TERT_TDM_RX_5 "TERT_TDM_RX_5"
129#define LPASS_BE_TERT_TDM_TX_5 "TERT_TDM_TX_5"
130#define LPASS_BE_TERT_TDM_RX_6 "TERT_TDM_RX_6"
131#define LPASS_BE_TERT_TDM_TX_6 "TERT_TDM_TX_6"
132#define LPASS_BE_TERT_TDM_RX_7 "TERT_TDM_RX_7"
133#define LPASS_BE_TERT_TDM_TX_7 "TERT_TDM_TX_7"
134#define LPASS_BE_QUAT_TDM_RX_0 "QUAT_TDM_RX_0"
135#define LPASS_BE_QUAT_TDM_TX_0 "QUAT_TDM_TX_0"
136#define LPASS_BE_QUAT_TDM_RX_1 "QUAT_TDM_RX_1"
137#define LPASS_BE_QUAT_TDM_TX_1 "QUAT_TDM_TX_1"
138#define LPASS_BE_QUAT_TDM_RX_2 "QUAT_TDM_RX_2"
139#define LPASS_BE_QUAT_TDM_TX_2 "QUAT_TDM_TX_2"
140#define LPASS_BE_QUAT_TDM_RX_3 "QUAT_TDM_RX_3"
141#define LPASS_BE_QUAT_TDM_TX_3 "QUAT_TDM_TX_3"
142#define LPASS_BE_QUAT_TDM_RX_4 "QUAT_TDM_RX_4"
143#define LPASS_BE_QUAT_TDM_TX_4 "QUAT_TDM_TX_4"
144#define LPASS_BE_QUAT_TDM_RX_5 "QUAT_TDM_RX_5"
145#define LPASS_BE_QUAT_TDM_TX_5 "QUAT_TDM_TX_5"
146#define LPASS_BE_QUAT_TDM_RX_6 "QUAT_TDM_RX_6"
147#define LPASS_BE_QUAT_TDM_TX_6 "QUAT_TDM_TX_6"
148#define LPASS_BE_QUAT_TDM_RX_7 "QUAT_TDM_RX_7"
149#define LPASS_BE_QUAT_TDM_TX_7 "QUAT_TDM_TX_7"
150#define LPASS_BE_QUIN_TDM_RX_0 "QUIN_TDM_RX_0"
151#define LPASS_BE_QUIN_TDM_TX_0 "QUIN_TDM_TX_0"
152#define LPASS_BE_QUIN_TDM_RX_1 "QUIN_TDM_RX_1"
153#define LPASS_BE_QUIN_TDM_TX_1 "QUIN_TDM_TX_1"
154#define LPASS_BE_QUIN_TDM_RX_2 "QUIN_TDM_RX_2"
155#define LPASS_BE_QUIN_TDM_TX_2 "QUIN_TDM_TX_2"
156#define LPASS_BE_QUIN_TDM_RX_3 "QUIN_TDM_RX_3"
157#define LPASS_BE_QUIN_TDM_TX_3 "QUIN_TDM_TX_3"
158#define LPASS_BE_QUIN_TDM_RX_4 "QUIN_TDM_RX_4"
159#define LPASS_BE_QUIN_TDM_TX_4 "QUIN_TDM_TX_4"
160#define LPASS_BE_QUIN_TDM_RX_5 "QUIN_TDM_RX_5"
161#define LPASS_BE_QUIN_TDM_TX_5 "QUIN_TDM_TX_5"
162#define LPASS_BE_QUIN_TDM_RX_6 "QUIN_TDM_RX_6"
163#define LPASS_BE_QUIN_TDM_TX_6 "QUIN_TDM_TX_6"
164#define LPASS_BE_QUIN_TDM_RX_7 "QUIN_TDM_RX_7"
165#define LPASS_BE_QUIN_TDM_TX_7 "QUIN_TDM_TX_7"
166
167#define LPASS_BE_SLIMBUS_7_RX "SLIMBUS_7_RX"
168#define LPASS_BE_SLIMBUS_7_TX "SLIMBUS_7_TX"
169#define LPASS_BE_SLIMBUS_8_RX "SLIMBUS_8_RX"
170#define LPASS_BE_SLIMBUS_8_TX "SLIMBUS_8_TX"
171
172#define LPASS_BE_USB_AUDIO_RX "USB_AUDIO_RX"
173#define LPASS_BE_USB_AUDIO_TX "USB_AUDIO_TX"
174
175#define LPASS_BE_INT0_MI2S_RX "INT0_MI2S_RX"
176#define LPASS_BE_INT0_MI2S_TX "INT0_MI2S_TX"
177#define LPASS_BE_INT1_MI2S_RX "INT1_MI2S_RX"
178#define LPASS_BE_INT1_MI2S_TX "INT1_MI2S_TX"
179#define LPASS_BE_INT2_MI2S_RX "INT2_MI2S_RX"
180#define LPASS_BE_INT2_MI2S_TX "INT2_MI2S_TX"
181#define LPASS_BE_INT3_MI2S_RX "INT3_MI2S_RX"
182#define LPASS_BE_INT3_MI2S_TX "INT3_MI2S_TX"
183#define LPASS_BE_INT4_MI2S_RX "INT4_MI2S_RX"
184#define LPASS_BE_INT4_MI2S_TX "INT4_MI2S_TX"
185#define LPASS_BE_INT5_MI2S_RX "INT5_MI2S_RX"
186#define LPASS_BE_INT5_MI2S_TX "INT5_MI2S_TX"
187#define LPASS_BE_INT6_MI2S_RX "INT6_MI2S_RX"
188#define LPASS_BE_INT6_MI2S_TX "INT6_MI2S_TX"
189/* For multimedia front-ends, asm session is allocated dynamically.
190 * Hence, asm session/multimedia front-end mapping has to be maintained.
191 * Due to this reason, additional multimedia front-end must be placed before
192 * non-multimedia front-ends.
193 */
194
195enum {
196 MSM_FRONTEND_DAI_MULTIMEDIA1 = 0,
197 MSM_FRONTEND_DAI_MULTIMEDIA2,
198 MSM_FRONTEND_DAI_MULTIMEDIA3,
199 MSM_FRONTEND_DAI_MULTIMEDIA4,
200 MSM_FRONTEND_DAI_MULTIMEDIA5,
201 MSM_FRONTEND_DAI_MULTIMEDIA6,
202 MSM_FRONTEND_DAI_MULTIMEDIA7,
203 MSM_FRONTEND_DAI_MULTIMEDIA8,
204 MSM_FRONTEND_DAI_MULTIMEDIA9,
205 MSM_FRONTEND_DAI_MULTIMEDIA10,
206 MSM_FRONTEND_DAI_MULTIMEDIA11,
207 MSM_FRONTEND_DAI_MULTIMEDIA12,
208 MSM_FRONTEND_DAI_MULTIMEDIA13,
209 MSM_FRONTEND_DAI_MULTIMEDIA14,
210 MSM_FRONTEND_DAI_MULTIMEDIA15,
211 MSM_FRONTEND_DAI_MULTIMEDIA16,
212 MSM_FRONTEND_DAI_MULTIMEDIA17,
213 MSM_FRONTEND_DAI_MULTIMEDIA18,
214 MSM_FRONTEND_DAI_MULTIMEDIA19,
215 MSM_FRONTEND_DAI_MULTIMEDIA20,
216 MSM_FRONTEND_DAI_MULTIMEDIA21,
217 MSM_FRONTEND_DAI_MULTIMEDIA22,
218 MSM_FRONTEND_DAI_MULTIMEDIA28,
219 MSM_FRONTEND_DAI_MULTIMEDIA29,
220 MSM_FRONTEND_DAI_VOIP,
221 MSM_FRONTEND_DAI_AFE_RX,
222 MSM_FRONTEND_DAI_AFE_TX,
223 MSM_FRONTEND_DAI_VOICE_STUB,
224 MSM_FRONTEND_DAI_DTMF_RX,
225 MSM_FRONTEND_DAI_QCHAT,
226 MSM_FRONTEND_DAI_VOLTE_STUB,
227 MSM_FRONTEND_DAI_LSM1,
228 MSM_FRONTEND_DAI_LSM2,
229 MSM_FRONTEND_DAI_LSM3,
230 MSM_FRONTEND_DAI_LSM4,
231 MSM_FRONTEND_DAI_LSM5,
232 MSM_FRONTEND_DAI_LSM6,
233 MSM_FRONTEND_DAI_LSM7,
234 MSM_FRONTEND_DAI_LSM8,
235 MSM_FRONTEND_DAI_VOICE2_STUB,
236 MSM_FRONTEND_DAI_VOICEMMODE1,
237 MSM_FRONTEND_DAI_VOICEMMODE2,
238 MSM_FRONTEND_DAI_MAX,
239};
240
241#define MSM_FRONTEND_DAI_MM_SIZE (MSM_FRONTEND_DAI_MULTIMEDIA29 + 1)
242#define MSM_FRONTEND_DAI_MM_MAX_ID MSM_FRONTEND_DAI_MULTIMEDIA29
243
244enum {
245 MSM_BACKEND_DAI_PRI_I2S_RX = 0,
246 MSM_BACKEND_DAI_PRI_I2S_TX,
247 MSM_BACKEND_DAI_SLIMBUS_0_RX,
248 MSM_BACKEND_DAI_SLIMBUS_0_TX,
249 MSM_BACKEND_DAI_HDMI_RX,
250 MSM_BACKEND_DAI_INT_BT_SCO_RX,
251 MSM_BACKEND_DAI_INT_BT_SCO_TX,
252 MSM_BACKEND_DAI_INT_FM_RX,
253 MSM_BACKEND_DAI_INT_FM_TX,
254 MSM_BACKEND_DAI_AFE_PCM_RX,
255 MSM_BACKEND_DAI_AFE_PCM_TX,
256 MSM_BACKEND_DAI_AUXPCM_RX,
257 MSM_BACKEND_DAI_AUXPCM_TX,
258 MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
259 MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
260 MSM_BACKEND_DAI_INCALL_RECORD_RX,
261 MSM_BACKEND_DAI_INCALL_RECORD_TX,
262 MSM_BACKEND_DAI_MI2S_RX,
263 MSM_BACKEND_DAI_MI2S_TX,
264 MSM_BACKEND_DAI_SEC_I2S_RX,
265 MSM_BACKEND_DAI_SLIMBUS_1_RX,
266 MSM_BACKEND_DAI_SLIMBUS_1_TX,
267 MSM_BACKEND_DAI_SLIMBUS_2_RX,
268 MSM_BACKEND_DAI_SLIMBUS_2_TX,
269 MSM_BACKEND_DAI_SLIMBUS_3_RX,
270 MSM_BACKEND_DAI_SLIMBUS_3_TX,
271 MSM_BACKEND_DAI_SLIMBUS_4_RX,
272 MSM_BACKEND_DAI_SLIMBUS_4_TX,
273 MSM_BACKEND_DAI_SLIMBUS_5_RX,
274 MSM_BACKEND_DAI_SLIMBUS_5_TX,
275 MSM_BACKEND_DAI_SLIMBUS_6_RX,
276 MSM_BACKEND_DAI_SLIMBUS_6_TX,
277 MSM_BACKEND_DAI_SLIMBUS_7_RX,
278 MSM_BACKEND_DAI_SLIMBUS_7_TX,
279 MSM_BACKEND_DAI_SLIMBUS_8_RX,
280 MSM_BACKEND_DAI_SLIMBUS_8_TX,
281 MSM_BACKEND_DAI_EXTPROC_RX,
282 MSM_BACKEND_DAI_EXTPROC_TX,
283 MSM_BACKEND_DAI_EXTPROC_EC_TX,
284 MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
285 MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
286 MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
287 MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
288 MSM_BACKEND_DAI_PRI_MI2S_RX,
289 MSM_BACKEND_DAI_PRI_MI2S_TX,
290 MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
291 MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
292 MSM_BACKEND_DAI_AUDIO_I2S_RX,
293 MSM_BACKEND_DAI_SEC_AUXPCM_RX,
294 MSM_BACKEND_DAI_SEC_AUXPCM_TX,
295 MSM_BACKEND_DAI_SPDIF_RX,
296 MSM_BACKEND_DAI_SECONDARY_MI2S_RX_SD1,
297 MSM_BACKEND_DAI_QUINARY_MI2S_RX,
298 MSM_BACKEND_DAI_QUINARY_MI2S_TX,
299 MSM_BACKEND_DAI_SENARY_MI2S_TX,
300 MSM_BACKEND_DAI_PRI_TDM_RX_0,
301 MSM_BACKEND_DAI_PRI_TDM_TX_0,
302 MSM_BACKEND_DAI_PRI_TDM_RX_1,
303 MSM_BACKEND_DAI_PRI_TDM_TX_1,
304 MSM_BACKEND_DAI_PRI_TDM_RX_2,
305 MSM_BACKEND_DAI_PRI_TDM_TX_2,
306 MSM_BACKEND_DAI_PRI_TDM_RX_3,
307 MSM_BACKEND_DAI_PRI_TDM_TX_3,
308 MSM_BACKEND_DAI_PRI_TDM_RX_4,
309 MSM_BACKEND_DAI_PRI_TDM_TX_4,
310 MSM_BACKEND_DAI_PRI_TDM_RX_5,
311 MSM_BACKEND_DAI_PRI_TDM_TX_5,
312 MSM_BACKEND_DAI_PRI_TDM_RX_6,
313 MSM_BACKEND_DAI_PRI_TDM_TX_6,
314 MSM_BACKEND_DAI_PRI_TDM_RX_7,
315 MSM_BACKEND_DAI_PRI_TDM_TX_7,
316 MSM_BACKEND_DAI_SEC_TDM_RX_0,
317 MSM_BACKEND_DAI_SEC_TDM_TX_0,
318 MSM_BACKEND_DAI_SEC_TDM_RX_1,
319 MSM_BACKEND_DAI_SEC_TDM_TX_1,
320 MSM_BACKEND_DAI_SEC_TDM_RX_2,
321 MSM_BACKEND_DAI_SEC_TDM_TX_2,
322 MSM_BACKEND_DAI_SEC_TDM_RX_3,
323 MSM_BACKEND_DAI_SEC_TDM_TX_3,
324 MSM_BACKEND_DAI_SEC_TDM_RX_4,
325 MSM_BACKEND_DAI_SEC_TDM_TX_4,
326 MSM_BACKEND_DAI_SEC_TDM_RX_5,
327 MSM_BACKEND_DAI_SEC_TDM_TX_5,
328 MSM_BACKEND_DAI_SEC_TDM_RX_6,
329 MSM_BACKEND_DAI_SEC_TDM_TX_6,
330 MSM_BACKEND_DAI_SEC_TDM_RX_7,
331 MSM_BACKEND_DAI_SEC_TDM_TX_7,
332 MSM_BACKEND_DAI_TERT_TDM_RX_0,
333 MSM_BACKEND_DAI_TERT_TDM_TX_0,
334 MSM_BACKEND_DAI_TERT_TDM_RX_1,
335 MSM_BACKEND_DAI_TERT_TDM_TX_1,
336 MSM_BACKEND_DAI_TERT_TDM_RX_2,
337 MSM_BACKEND_DAI_TERT_TDM_TX_2,
338 MSM_BACKEND_DAI_TERT_TDM_RX_3,
339 MSM_BACKEND_DAI_TERT_TDM_TX_3,
340 MSM_BACKEND_DAI_TERT_TDM_RX_4,
341 MSM_BACKEND_DAI_TERT_TDM_TX_4,
342 MSM_BACKEND_DAI_TERT_TDM_RX_5,
343 MSM_BACKEND_DAI_TERT_TDM_TX_5,
344 MSM_BACKEND_DAI_TERT_TDM_RX_6,
345 MSM_BACKEND_DAI_TERT_TDM_TX_6,
346 MSM_BACKEND_DAI_TERT_TDM_RX_7,
347 MSM_BACKEND_DAI_TERT_TDM_TX_7,
348 MSM_BACKEND_DAI_QUAT_TDM_RX_0,
349 MSM_BACKEND_DAI_QUAT_TDM_TX_0,
350 MSM_BACKEND_DAI_QUAT_TDM_RX_1,
351 MSM_BACKEND_DAI_QUAT_TDM_TX_1,
352 MSM_BACKEND_DAI_QUAT_TDM_RX_2,
353 MSM_BACKEND_DAI_QUAT_TDM_TX_2,
354 MSM_BACKEND_DAI_QUAT_TDM_RX_3,
355 MSM_BACKEND_DAI_QUAT_TDM_TX_3,
356 MSM_BACKEND_DAI_QUAT_TDM_RX_4,
357 MSM_BACKEND_DAI_QUAT_TDM_TX_4,
358 MSM_BACKEND_DAI_QUAT_TDM_RX_5,
359 MSM_BACKEND_DAI_QUAT_TDM_TX_5,
360 MSM_BACKEND_DAI_QUAT_TDM_RX_6,
361 MSM_BACKEND_DAI_QUAT_TDM_TX_6,
362 MSM_BACKEND_DAI_QUAT_TDM_RX_7,
363 MSM_BACKEND_DAI_QUAT_TDM_TX_7,
364 MSM_BACKEND_DAI_QUIN_TDM_RX_0,
365 MSM_BACKEND_DAI_QUIN_TDM_TX_0,
366 MSM_BACKEND_DAI_QUIN_TDM_RX_1,
367 MSM_BACKEND_DAI_QUIN_TDM_TX_1,
368 MSM_BACKEND_DAI_QUIN_TDM_RX_2,
369 MSM_BACKEND_DAI_QUIN_TDM_TX_2,
370 MSM_BACKEND_DAI_QUIN_TDM_RX_3,
371 MSM_BACKEND_DAI_QUIN_TDM_TX_3,
372 MSM_BACKEND_DAI_QUIN_TDM_RX_4,
373 MSM_BACKEND_DAI_QUIN_TDM_TX_4,
374 MSM_BACKEND_DAI_QUIN_TDM_RX_5,
375 MSM_BACKEND_DAI_QUIN_TDM_TX_5,
376 MSM_BACKEND_DAI_QUIN_TDM_RX_6,
377 MSM_BACKEND_DAI_QUIN_TDM_TX_6,
378 MSM_BACKEND_DAI_QUIN_TDM_RX_7,
379 MSM_BACKEND_DAI_QUIN_TDM_TX_7,
380 MSM_BACKEND_DAI_INT_BT_A2DP_RX,
381 MSM_BACKEND_DAI_USB_RX,
382 MSM_BACKEND_DAI_USB_TX,
383 MSM_BACKEND_DAI_DISPLAY_PORT_RX,
384 MSM_BACKEND_DAI_TERT_AUXPCM_RX,
385 MSM_BACKEND_DAI_TERT_AUXPCM_TX,
386 MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
387 MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
388 MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
389 MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
390 MSM_BACKEND_DAI_INT0_MI2S_RX,
391 MSM_BACKEND_DAI_INT0_MI2S_TX,
392 MSM_BACKEND_DAI_INT1_MI2S_RX,
393 MSM_BACKEND_DAI_INT1_MI2S_TX,
394 MSM_BACKEND_DAI_INT2_MI2S_RX,
395 MSM_BACKEND_DAI_INT2_MI2S_TX,
396 MSM_BACKEND_DAI_INT3_MI2S_RX,
397 MSM_BACKEND_DAI_INT3_MI2S_TX,
398 MSM_BACKEND_DAI_INT4_MI2S_RX,
399 MSM_BACKEND_DAI_INT4_MI2S_TX,
400 MSM_BACKEND_DAI_INT5_MI2S_RX,
401 MSM_BACKEND_DAI_INT5_MI2S_TX,
402 MSM_BACKEND_DAI_INT6_MI2S_RX,
403 MSM_BACKEND_DAI_INT6_MI2S_TX,
Anver sadhique276e2a42021-02-16 11:35:57 +0530404 MSM_BACKEND_DAI_PROXY_RX,
405 MSM_BACKEND_DAI_PROXY_TX,
Alexander Martinz28de9412021-09-09 17:05:05 +0200406 MSM_BACKEND_DAI_MAX,
407};
408
409enum msm_pcm_routing_event {
410 MSM_PCM_RT_EVT_BUF_RECFG,
411 MSM_PCM_RT_EVT_DEVSWITCH,
412 MSM_PCM_RT_EVT_MAX,
413};
414
415enum {
416 EXT_EC_REF_NONE = 0,
417 EXT_EC_REF_PRI_MI2S_TX,
418 EXT_EC_REF_SEC_MI2S_TX,
419 EXT_EC_REF_TERT_MI2S_TX,
420 EXT_EC_REF_QUAT_MI2S_TX,
421 EXT_EC_REF_QUIN_MI2S_TX,
422 EXT_EC_REF_SLIM_1_TX,
423};
424
425#define INVALID_SESSION -1
426#define SESSION_TYPE_RX 0
427#define SESSION_TYPE_TX 1
428#define MAX_SESSION_TYPES 2
429#define INT_RX_VOL_MAX_STEPS 0x2000
430#define INT_RX_VOL_GAIN 0x2000
431
432#define RELEASE_LOCK 0
433#define ACQUIRE_LOCK 1
434
435#define MSM_BACKEND_DAI_PP_PARAMS_REQ_MAX 2
436#define HDMI_RX_ID 0x8001
437#define ADM_PP_PARAM_MUTE_ID 0
438#define ADM_PP_PARAM_MUTE_BIT 1
439#define ADM_PP_PARAM_LATENCY_ID 1
440#define ADM_PP_PARAM_LATENCY_BIT 2
441#define BE_DAI_PORT_SESSIONS_IDX_MAX 4
442#define BE_DAI_FE_SESSIONS_IDX_MAX 2
443
444enum {
445 ADM_TOPOLOGY_CAL_TYPE_IDX = 0,
446 ADM_LSM_TOPOLOGY_CAL_TYPE_IDX,
447 MAX_ROUTING_CAL_TYPES
448};
449
450struct msm_pcm_routing_evt {
451 void (*event_func)(enum msm_pcm_routing_event, void *);
452 void *priv_data;
453};
454
455struct msm_pcm_routing_bdai_data {
456 u16 port_id; /* AFE port ID */
457 u8 active; /* track if this backend is enabled */
458
459 /* Front-end sessions */
460 unsigned long fe_sessions[BE_DAI_FE_SESSIONS_IDX_MAX];
461 /*
462 * Track Tx BE ports -> Rx BE ports.
463 * port_sessions[0] used to track BE 0 to BE 63.
464 * port_sessions[1] used to track BE 64 to BE 127.
465 * port_sessions[2] used to track BE 128 to BE 191.
466 * port_sessions[3] used to track BE 192 to BE 255.
467 */
468 u64 port_sessions[BE_DAI_PORT_SESSIONS_IDX_MAX];
469
470 unsigned int sample_rate;
471 unsigned int channel;
472 unsigned int format;
473 unsigned int adm_override_ch;
474 u32 passthr_mode[MSM_FRONTEND_DAI_MAX];
475 char *name;
476};
477
478struct msm_pcm_routing_fdai_data {
479 u16 be_srate; /* track prior backend sample rate for flushing purpose */
480 int strm_id; /* ASM stream ID */
481 int perf_mode;
482 struct msm_pcm_routing_evt event_info;
483};
484
485#define MAX_APP_TYPES 16
486struct msm_pcm_routing_app_type_data {
487 int app_type;
488 u32 sample_rate;
489 int bit_width;
490};
491
492struct msm_pcm_stream_app_type_cfg {
493 int app_type;
494 int acdb_dev_id;
495 int sample_rate;
496};
497
498/* dai_id: front-end ID,
499 * dspst_id: DSP audio stream ID
500 * stream_type: playback or capture
501 */
502int msm_pcm_routing_reg_phy_stream(int fedai_id, int perf_mode, int dspst_id,
503 int stream_type);
504void msm_pcm_routing_reg_psthr_stream(int fedai_id, int dspst_id,
505 int stream_type);
506int msm_pcm_routing_reg_phy_compr_stream(int fedai_id, int perf_mode,
507 int dspst_id, int stream_type,
508 uint32_t compr_passthr);
509
510int msm_pcm_routing_reg_phy_stream_v2(int fedai_id, int perf_mode,
511 int dspst_id, int stream_type,
512 struct msm_pcm_routing_evt event_info);
513
514void msm_pcm_routing_dereg_phy_stream(int fedai_id, int stream_type);
515
516int msm_routing_check_backend_enabled(int fedai_id);
517
518
519void msm_pcm_routing_get_bedai_info(int be_idx,
520 struct msm_pcm_routing_bdai_data *bedai);
521void msm_pcm_routing_get_fedai_info(int fe_idx, int sess_type,
522 struct msm_pcm_routing_fdai_data *fe_dai);
523void msm_pcm_routing_acquire_lock(void);
524void msm_pcm_routing_release_lock(void);
525
526int msm_pcm_routing_reg_stream_app_type_cfg(
527 int fedai_id, int session_type, int be_id,
528 struct msm_pcm_stream_app_type_cfg *cfg_data);
529int msm_pcm_routing_get_stream_app_type_cfg(
530 int fedai_id, int session_type, int *be_id,
531 struct msm_pcm_stream_app_type_cfg *cfg_data);
532#endif /*_MSM_PCM_H*/